KR20020056341A - Method of forming inter-metal dielectric in a semiconductor device - Google Patents
Method of forming inter-metal dielectric in a semiconductor device Download PDFInfo
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- KR20020056341A KR20020056341A KR1020000085670A KR20000085670A KR20020056341A KR 20020056341 A KR20020056341 A KR 20020056341A KR 1020000085670 A KR1020000085670 A KR 1020000085670A KR 20000085670 A KR20000085670 A KR 20000085670A KR 20020056341 A KR20020056341 A KR 20020056341A
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 title description 40
- 239000002184 metal Substances 0.000 title description 40
- 239000010410 layer Substances 0.000 claims abstract description 63
- 239000011229 interlayer Substances 0.000 claims abstract description 39
- 238000009792 diffusion process Methods 0.000 claims abstract description 33
- 230000009977 dual effect Effects 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 102
- 229910052802 copper Inorganic materials 0.000 claims description 101
- 239000010949 copper Substances 0.000 claims description 101
- 238000009832 plasma treatment Methods 0.000 claims description 20
- 238000000151 deposition Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 7
- 239000003292 glue Substances 0.000 claims description 4
- 238000011065 in-situ storage Methods 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 3
- 239000005751 Copper oxide Substances 0.000 description 3
- 229910000431 copper oxide Inorganic materials 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 층간 절연막 형성 방법에 관한 것으로, 특히 듀얼 다마신 패턴 형성 후 금속 확산 방지 금속층 없이 바로 상부 배선을 형성함으로써 초미세 구조의 듀얼 다마신 패턴 내부에 상부 배선을 균일하고 용이하게 매립하여 전기적 특성을 향상시킬 수 있는 반도체 소자의 층간 절연막 형성 방법에 관한 것이다.The present invention relates to a method for forming an interlayer insulating film of a semiconductor device, and in particular, by forming an upper wiring immediately without forming a metal diffusion preventing metal layer after forming a dual damascene pattern, the upper wiring is uniformly and easily embedded in the dual damascene pattern having an ultrafine structure. The present invention relates to an interlayer insulating film forming method of a semiconductor device capable of improving electrical characteristics.
구리는 특유의 낮은 저항값 때문에 반도체 소자의 금속 배선 재료로 많이 사용되고 있다.Copper is widely used as a metal wiring material for semiconductor devices because of its unique low resistance value.
종래의 구리 금속 배선 형성 방법은 기본적으로 트랜치와 비아(또는 콘택홀)로 이루어진 이중 구조의 듀얼 다마신 패턴이 형성된 층간 절연막 상에 금속 확산 방지 금속층을 형성한 후 층간 절연막 상의 구리 확산 방지 금속층을 제거하고, 듀얼 다마신 패턴 내부에 구리를 매립하여 구리 배선을 형성한다. 이러한 구리 배선이 다층으로 적층되어 있을 경우 층간 배선을 연결하는 비아 콘택 하부는 하부 구리 배선/금속 확산 방지 금속층/상부 구리 배선의 적층 구조를 이루고있다. 여기서, 형성되는 금속 확산 방지 금속층은 구리가 절연막으로 확산되어 구리 배선의 전기적 특성이 저하되는 것을 방지하기 위하여 필수적으로 형성된다.Conventional copper metal wiring forming method basically forms a metal diffusion preventing metal layer on the interlayer insulating film having a dual damascene pattern having a dual structure consisting of trenches and vias (or contact holes), and then removes the copper diffusion preventing metal layer on the interlayer insulating film. Then, copper is embedded in the dual damascene pattern to form a copper wiring. When the copper wirings are stacked in multiple layers, the bottom of the via contact connecting the interlayer wirings has a laminated structure of a lower copper wiring / metal diffusion preventing metal layer / upper copper wiring. Here, the metal diffusion prevention metal layer formed is essentially formed to prevent copper from diffusing into the insulating film to lower the electrical characteristics of the copper wiring.
이러한 구리 확산 방지 금속층은 구리에 비하여 높은 저항값을 가진다. 이 경우, 비아 저항이 높고, 전류 흐름에 따른 구리 원자 이동이 구리 확산 방지 금속층에 의해 방해되어 비아 하부에서 불량이 발생된다. 이는 상부 구리 배선에서의구리 원자 이동이 구리 확산 방지 금속층에 의해 방해를 받기 때문이다. 다시 말해, 하부 구리 배선과 상부 구리 배선 사이에 형성된 구리 확산 방지 금속층은 구리의 저저항 특성을 열화시켜 전기적 특성이 저하되는 문제점이 있다.This copper diffusion preventing metal layer has a higher resistance value than copper. In this case, the via resistance is high, and copper atom movement due to the current flow is hindered by the copper diffusion preventing metal layer, thereby causing a defect in the bottom of the via. This is because copper atom movement in the upper copper wiring is hindered by the copper diffusion preventing metal layer. In other words, the copper diffusion preventing metal layer formed between the lower copper wiring and the upper copper wiring has a problem of deteriorating the low resistance characteristics of copper and lowering electrical characteristics.
또한, 소자의 고집적화에 따라 비아과 트랜치의 단차비가 증가하게 되어 금속 확산 방지 금속층의 층덮힘이 매우 중요하게 되어 새로운 기술의 도입을 요구하고 있다. 또한, 금속 확산 방지 금속층이 차지하는 비율이 증가함에 따라 트랜치에서의 유효(Effective) 저항 값이 증가하게 되어 알루미늄 합금 대신 저항이 낮은 구리 배선을 형성하는 효과가 감소하거나 없어진다. 그리고, 금속 확산 방지 금속층에 의해 구리 배선을 위한 화학적 기계적 연마 시 다단계 연마 공정이 필요하여 공정이 복잡하고, 높은 생산 단가를 요한다. 또한, 금속 확산 방지 금속층을 증착함으로 인해 비아와 트랜치 상부 입구가 협소해져 구리 시드층 증착 시 비아 내부에 균일한 구리막을 증착하기 어려워 전기 화학적 구리 증착 시 비아 내부에 동공이 형성되어 배선 신뢰성에 악영향을 미치는 문제점이 있다.In addition, as the high integration of the device increases the step ratio between the via and the trench, the layer covering of the metal diffusion preventing metal layer becomes very important, requiring the introduction of a new technology. In addition, as the proportion of the metal diffusion preventing metal layer increases, the effective resistance value in the trench increases, thereby reducing or eliminating the effect of forming a low resistance copper wiring instead of an aluminum alloy. In addition, when the mechanical mechanical polishing for copper wiring is performed by the metal diffusion preventing metal layer, a multi-step polishing process is required, and the process is complicated and a high production cost is required. In addition, the deposition of the metal diffusion preventing metal layer makes the via and the trench upper opening narrow, which makes it difficult to deposit a uniform copper film inside the via when the copper seed layer is deposited. There is a problem.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 금속 확산 방지 금속층 없이 듀얼 다마신 패턴 내부에 구리를 매립하여 구리 배선을 형성하되 구리를 매립하기 전에 플라즈마 처리를 실시하여 층간 절연막으로의 구리 확산을 방지함으로써 비아에서의 접촉 저항을 줄이고, 듀얼 다마신 패턴 내부로의 구리 매립을 용이하게 실시하여 소자의 전기적 특성을 향상시키고, 배선 형성 공정을 용이하게 실시할 수있는 반도체 소자의 층간 절연막 형성 방법을 제공하는데 그 목적이 있다.Accordingly, in order to solve the above problem, the present invention provides a copper wiring by embedding copper in a dual damascene pattern without a metal diffusion preventing metal layer, but prevents copper diffusion into an interlayer insulating film by performing a plasma treatment before embedding copper. This provides a method for forming an interlayer insulating film of a semiconductor device, which reduces contact resistance in a via, facilitates copper filling into a dual damascene pattern, and improves electrical characteristics of the device, and facilitates a wiring forming process. Its purpose is to.
도 1a 내지 도 1c는 본 발명에 따른 반도체 소자의 층간 절연막 형성 방법을 설명하기 위하여 순차적으로 도시한 소자의 단면도.1A to 1C are cross-sectional views of devices sequentially shown to explain a method for forming an interlayer insulating film of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
1 : 반도체 기판2 : 하부 구리 배선1 semiconductor substrate 2 lower copper wiring
2a : 구리 산화막3 : 구리 확산 방지막2a copper oxide film 3: copper diffusion preventing film
4 : 제 1 절연막5 : 식각 방지막4: first insulating film 5: etching prevention film
6 : 제 2 절연막7 : 하드 마스크용 절연막6: second insulating film 7: insulating film for hard mask
40 : 층간 절연막40a : 플라즈마 처리막40: interlayer insulating film 40a: plasma treatment film
8a : 시드 구리층8b : 배선용 구리층8a: seed copper layer 8b: wiring copper layer
8 : 상부 구리 배선8: upper copper wiring
본 발명에 따른 반도체 소자의 층간 절연막 형성 방법은 하부 구리 배선을 포함하여 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판 상에 층간 절연막을 형성한 후 트렌치 및 비아로 이루어진 듀얼 다마신 패턴을 형성하여 상기 하부 구리 배선을 노출시키는 단계, 듀얼 다마신 패턴 내벽 전체를 플라즈마 처리하여 트렌치 및 비아 측벽 쪽 층간 절연막의 소정 두께를 구리 확산을 방지하기 위한 플라즈마 처리막으로 형성하는 단계 및 듀얼 다마신 패턴 내부에 구리를 매립하여 상부 구리 배선을 형성하는 단계를 포함하여 이루어진다.In the method for forming an interlayer insulating film of a semiconductor device according to the present invention, an interlayer insulating film is formed on a semiconductor substrate on which various elements for forming a semiconductor device, including lower copper wirings, are formed to form a dual damascene pattern consisting of trenches and vias. Exposing the lower copper interconnections, plasma treating the entire inner wall of the dual damascene pattern to form a predetermined thickness of the interlayer insulating layer on the trench and via sidewalls as a plasma treatment layer to prevent copper diffusion; and Embedding copper to form an upper copper interconnect.
층간 절연막은 상기 트렌치과 비아의 경계에 식각 방지막으로 SiN 또는 SiC 절연막층을 포함하여 이루어진다. 플라즈마 처리를 실시하기 전에는 Ar 가스 또는 Ar + N2혼합 가스를 이용하여 비아 하부를 식각한다. 이후 플라즈마 처리는 인-시투로 상온 내지 400℃의 온도 범위에서 H2, H2+He, H2+Ar, H2+N2, NH3또는 NH3+N2혼합 가스를 이용하여 실시하며, 플라즈마 처리막은 상기 듀얼 다마신 패턴 측벽의 SiOC층을 10 내지 50Å 두께의 SiCN, SiOCN 또는 SiN막으로 만들어 형성한다. 플라즈마 처리 시 반도체 기판에는 0V 내지 -100V 범위의 바이어스를 인가하다.The interlayer insulating layer includes an SiN or SiC insulating layer as an etch stop layer at the boundary between the trench and the via. Prior to the plasma treatment, the bottom of the via is etched using Ar gas or Ar + N 2 mixed gas. The plasma treatment is then carried out using H 2 , H 2 + He, H 2 + Ar, H 2 + N 2 , NH 3 or NH 3 + N 2 mixed gas at room temperature to 400 ° C. in-situ. The plasma treatment film is formed by forming the SiOC layer on the sidewall of the dual damascene pattern into a SiCN, SiOCN or SiN film having a thickness of 10 to 50 GPa. In the plasma treatment, a bias in the range of 0V to -100V is applied to the semiconductor substrate.
상부 구리 배선은 듀얼 다마신 패턴을 포함한 층간 절연막 상에 시드 구리층을 형성하고, 전기 화학적 구리 증착법으로 듀얼 다마신 패턴 내부를 구리로 매립한 후 화학적 기계적 연마를 실시하여 층간 절연막 상의 구리 및 시드 구리층을 제거하여 형성한다. 시드 구리층을 증착하기 전에 시드 구리층의 증착을 용이하게 하기 위하여 물리 기상 증착법으로 글루 구리층을 형성할 수도 있다.The upper copper wiring forms a seed copper layer on the interlayer insulating film including the dual damascene pattern, embeds the inside of the dual damascene pattern with copper by electrochemical copper deposition, and chemically polishes the copper and the seed copper on the interlayer insulating film. Form by removing the layer. The glue copper layer may be formed by physical vapor deposition to facilitate the deposition of the seed copper layer prior to depositing the seed copper layer.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 더욱 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.
도 1a 내지 도 1c는 본 발명에 따른 반도체 소자의 층간 절연막 형성 방법을 설명하기 위하여 순차적으로 도시한 소자의 단면도이다.1A to 1C are cross-sectional views of devices sequentially illustrated to explain a method for forming an interlayer insulating film of a semiconductor device according to the present invention.
도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판(1) 상에 소정의 패턴으로 하부 구리 배선(2)을 형성한 후 전체 상에 구리 확산 방지막(3) 및 층간 절연막(40)을 순차적으로 형성한다. 층간 절연막(40)에는 하부 구리 배선(2)의 수직 배선을 위하여 소정 영역에 트랜치와 비아(또는 콘택홀)로 이루어진 듀얼 다마신 패턴을 형성하여 하부 구리 배선(2)이 노출되도록 한다. 노출된 하부 구리 배선(2)의 표면에는 기생적으로 구리 산화막(2a)이 형성된다.Referring to FIG. 1A, after forming a lower copper wiring 2 in a predetermined pattern on a semiconductor substrate 1 on which various elements for forming a semiconductor device are formed, a copper diffusion barrier film 3 and an interlayer insulating film ( 40) are formed sequentially. In the interlayer insulating layer 40, a dual damascene pattern formed of trenches and vias (or contact holes) is formed in a predetermined region for vertical wiring of the lower copper interconnection 2 so that the lower copper interconnection 2 is exposed. On the surface of the exposed lower copper wiring 2, a copper oxide film 2a is formed parasitically.
구리 확산 방지막(3)은 하부 구리 배선(2)이 층간 절연막(40)으로 확산되어 배선의 전기적 특성이 저하되는 것을 방지하기 위하여 형성한다. 층간 절연막(40)은 제 1 절연막(4), 식각 방지막(5), 제 2 절연막(6) 및 하부 마스크용 절연막(7)이 순차적으로 적층되어 형성된다.The copper diffusion preventing film 3 is formed to prevent the lower copper wiring 2 from diffusing into the interlayer insulating film 40 so that the electrical characteristics of the wiring are degraded. The interlayer insulating film 40 is formed by sequentially stacking the first insulating film 4, the etch stop film 5, the second insulating film 6, and the lower mask insulating film 7.
하드 마스크용 절연막(7)은 트랜치를 형성하기 위한 마스크로 이용하기 위하여 형성한다. 1차 식각 공정으로 하드 마스크용 절연막(7)과 제 2 절연막(6)을 식각하여 트랜치를 형성한다. 이때, 제 1 절연막(4)은 식각 방지막(5)에 의해 보호되어 1차 식각 공정 시 식각되지 않는다. 이후 비아(또는 콘택홀)를 형성하기 위한 2차 식각 공정 시 식각 방지막(5), 제 1 절연막(4) 및 구리 확산 방지막(3)을 식각하여 하부 구리 배선(2)이 노출되도록 한다. 식각 방지막(5)은 SiN 또는 SiC 절연막층으로 형성한다.The hard mask insulating film 7 is formed for use as a mask for forming trenches. A trench is formed by etching the hard mask insulating film 7 and the second insulating film 6 by a primary etching process. In this case, the first insulating layer 4 is protected by the etch stop layer 5 and is not etched during the primary etching process. Subsequently, during the second etching process for forming the via (or contact hole), the etch stop layer 5, the first insulating layer 4, and the copper diffusion barrier 3 are etched to expose the lower copper wiring 2. The etch stop film 5 is formed of a SiN or SiC insulating film layer.
도 1b를 참조하면, 듀얼 다마신 패턴 내벽 전체를 플라즈마 처리하여 트렌치 및 비아 측벽 쪽의 제 1 및 제 2 절연막(4 및 6)을 구리 확산을 방지하기 위한 플라즈마 처리막(40a)으로 형성한다.Referring to FIG. 1B, the entire inner wall of the dual damascene pattern is plasma treated to form the first and second insulating layers 4 and 6 on the sidewalls of the trench and the via as a plasma treatment layer 40a for preventing copper diffusion.
플라즈마 처리막(40a)은 층간 절연막(40)에 금속 확산 방지 금속층을 형성하지 않고도 듀얼 다마신 패턴 내부에 형성될 배선용 금속이 층간 절연막(40)으로 확산되지 않도록 하기 위하여 형성하며, 듀얼 다마신 패턴 측벽의 SiOC층을 10 내지 50Å 두께의 SiCN, SiOCN 또는 SiN막으로 만들어 형성한다.The plasma processing film 40a is formed so that the wiring metal to be formed inside the dual damascene pattern does not diffuse into the interlayer insulating film 40 without forming a metal diffusion preventing metal layer in the interlayer insulating film 40, and the dual damascene pattern. The SiOC layer on the sidewall is made of a SiCN, SiOCN or SiN film with a thickness of 10 to 50 GPa.
플라즈마 처리는 Ar 가스 또는 Ar + N2혼합 가스를 이용하여 비아 하부를 식각한 후 진공의 파괴 없이 인-시투(In-situ)로 상온 내지 400℃의 온도 범위에서 H2, H2+He, H2+Ar, H2+N2, NH3또는 NH3+N2혼합 가스를 이용하여 실시한다. 상기의 혼합 가스는 식각 조건 또는 플라즈마 처리 조건에 따라 혼합비를 적당한 조건으로 변화시켜 사용한다. 플라즈마 처리 시에는 반도체 기판(1)에 0V 내지 -100V 범위의 바이어스를 인가해 주어 플라즈마 처리 효과를 극대화한다.Plasma treatment is performed by etching the lower portion of the via using Ar gas or Ar + N 2 mixed gas, and then in-situ without breaking the vacuum, in the range of H 2 , H 2 + He, It is carried out using H 2 + Ar, H 2 + N 2 , NH 3 or NH 3 + N 2 mixed gas. The mixed gas is used by changing the mixing ratio to appropriate conditions according to etching conditions or plasma treatment conditions. In the plasma treatment, a bias in the range of 0V to -100V is applied to the semiconductor substrate 1 to maximize the plasma treatment effect.
플라즈마 처리를 실시하는 동안, 하부 구리 배선(2)의 표면에 기생적으로 형성된 구리 산화막(2a)은 환원되어 구리로 변환돼 하부 구리 배선(2)의 일부가 된다.During the plasma treatment, the copper oxide film 2a parasially formed on the surface of the lower copper wiring 2 is reduced and converted to copper to become a part of the lower copper wiring 2.
도 1c를 참조하면, 듀얼 다마신 패턴 내부를 구리로 매립하여 상부 구리 배선(8)을 형성한다.Referring to FIG. 1C, the inside of the dual damascene pattern is filled with copper to form the upper copper wiring 8.
상부 구리 배선(8)은 도 1b의 플라즈마 처리를 실시한 후 진공의 파괴 없이 인-시투로 전체 상에 화학 기상 증착법으로 시드 구리층(8a)을 증착한 후 전기 화학적 구리 증착법을 이용하여 배선용 구리층(8a)을 형성한 뒤 화학적 기계적 연마를 실시하여 듀얼 다마신 패턴의 내부에만 구리 금속층을 매립하여 형성한다.The upper copper wiring 8 is the copper layer for wiring using the electrochemical copper deposition after depositing the seed copper layer 8a by chemical vapor deposition on the entire in-situ after the plasma treatment of FIG. After forming (8a), chemical mechanical polishing is performed to form a copper metal layer embedded only in the dual damascene pattern.
시드 구리층(8a)을 형성하기 전에, 시드 구리층(8a)의 증착이 원할하게 이루어질 수 있도록 하기 위하여 물리 기상 증착법으로 글루(Glue) 구리층(도시되지 않음)을 먼저 증착할 수도 있다. 이때, 글루 구리층은 도 1b의 플라즈마 처리를 실시한 후 인-시투로 전체 상에 물리 기상 증착법으로 -50 내지 0℃의 온도 범위에서 20 내지 100Å의 두께로 형성한다.Prior to forming the seed copper layer 8a, a glue copper layer (not shown) may be deposited first by physical vapor deposition in order to facilitate the deposition of the seed copper layer 8a. At this time, the glue copper layer is formed to a thickness of 20 to 100 kPa in the temperature range of -50 to 0 ℃ by the physical vapor deposition method after the plasma treatment of FIG.
본 발명에 따른 반도체 소자의 층간 절연막 형성 방법은 저항이 높은 확산 방지 금속층 대신에 플라즈마 처리를 실시하여 층간 절연막(40)에 형성된 듀얼 다마신 패턴 측벽을 구리 확산 방지막으로 사용할 플라즈마 처리막(40a)으로 바꾸어 줌으로써 고저항 값을 가지는 구리 확산 방지 금속층 없이 하부 구리 배선 및 상부 구리 배선이 직접 연결되어 구리 금속 배선의 실제 저항을 낮게 유지할 수 있다.또한, 구리 확산 방지층 역할을 하는 플라즈마 처리막(40a)인 SiCN, SiOCN 또는 SiN막이 듀얼 다마신 패턴의 측벽을 보호하고 있어 배선간 누설 전류를 억제할 수 있다.In the method for forming an interlayer insulating film of a semiconductor device according to the present invention, a plasma treatment is performed in place of a high diffusion resistant metal layer to use a dual damascene pattern sidewall formed in the interlayer insulating film 40 as a copper diffusion preventing film. The lower copper wiring and the upper copper wiring can be directly connected without the copper diffusion preventing metal layer having a high resistance value, thereby keeping the actual resistance of the copper metal wiring low. In addition, the plasma processing film 40a serving as the copper diffusion preventing layer Since the SiCN, SiOCN or SiN film protects the sidewall of the dual damascene pattern, leakage current between wirings can be suppressed.
SiCN, SiOCN 또는 SiN막 위에서의 구리 금속 결정성이 구리 금속 확산 방지 금속층 위에서 보다 (111) 우선 방위가 강하게 얻을 수 있어 배선 신뢰성을 개선한다. 그리고, 구리 확산 방지 금속층을 사용하지 않기 때문에 화학적 기계적 구리 연마 시에 1개의 슬러리를 가지고 빠른 시간 내에 저 비용으로 연마가 가능하여 연마공정을 손쉽게 하는 기술이다.The copper metal crystallinity on the SiCN, SiOCN or SiN film can obtain a stronger (111) preferred orientation on the copper metal diffusion preventing metal layer, thereby improving wiring reliability. In addition, since the copper diffusion preventing metal layer is not used, it is possible to have a single slurry during chemical mechanical copper polishing and to polish at a low cost within a short time, thereby facilitating the polishing process.
상기에서 서술한, 반도체 소자의 층간 절연막 형성 방법은 구리 이외의 다른 금속을 이용해 배선을 형성할 경우에도 적용할 수 있다.The interlayer insulation film formation method of the semiconductor element mentioned above can be applied also when forming wiring using metal other than copper.
상술한 바와 같이, 본 발명은 구리 확산 방지 금속층 없이 듀얼 다마신 패턴 측벽의 플라즈마 처리를 통해 구리 확산을 억제할 수 있어 배선간의 접촉 저항을 낮게 유지할 수 있고, 구리 확산 방지 금속층에 의한 트랜치 상부가 좁아지는 것을 방지하여 구리 매립시 용이하게 실시할 수 있어 공정의 난이도를 낮추면서 소자의 전기적 특성을 향상시키는 효과가 있다.As described above, the present invention can suppress the copper diffusion through the plasma treatment of the dual damascene pattern sidewall without the copper diffusion preventing metal layer, thereby keeping the contact resistance between the wires low, and the upper portion of the trench by the copper diffusion preventing metal layer is narrow. It can be easily carried out at the time of embedding copper by preventing the fall, thereby reducing the difficulty of the process and improving the electrical characteristics of the device.
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| KR100947458B1 (en) * | 2003-07-18 | 2010-03-11 | 매그나칩 반도체 유한회사 | Method of manufacturing inductor in a semiconductor device |
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| KR101138082B1 (en) | 2004-06-14 | 2012-04-24 | 매그나칩 반도체 유한회사 | A method for forming a dual damascene pattern in semiconductor device |
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| KR100947458B1 (en) * | 2003-07-18 | 2010-03-11 | 매그나칩 반도체 유한회사 | Method of manufacturing inductor in a semiconductor device |
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