CN103187358B - A kind of copper barrier layer manufacture method - Google Patents
A kind of copper barrier layer manufacture method Download PDFInfo
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- CN103187358B CN103187358B CN201110452147.0A CN201110452147A CN103187358B CN 103187358 B CN103187358 B CN 103187358B CN 201110452147 A CN201110452147 A CN 201110452147A CN 103187358 B CN103187358 B CN 103187358B
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Abstract
The invention provides a kind of copper barrier layer manufacture method, adopt pulse plasma body chemical vapor phase growing to make copper barrier layer, thus reduce the charge accumulation of plasma thereunder on copper interconnecting line, avoid semiconductor device failure.
Description
Technical field
The present invention relates to a kind of semiconductor making method, particularly a kind of copper barrier layer manufacture method.
Background technology
Along with the development of semiconductor fabrication process, the area of semiconductor chip is more and more less, and meanwhile, the quantity of semiconductor device on a semiconductor chip in a also gets more and more.Semiconductor device is interconnected the Signal transmissions realized between semiconductor device by metal interconnecting layer, forms semiconductor circuit.Described metal interconnecting layer is jointly made up of the inter-level dielectric (Inter-LayerDielectric, ILD) between highdensity metal interconnecting wires and described metal interconnecting wires.In the manufacture of large scale integrated circuit (VLSI) and very lagre scale integrated circuit (VLSIC) (ULSI), can make multiple metal interconnecting layer above semiconductor device, its manufacture craft is also referred to as multilayer interconnection technology.The metal interconnected line length of multilayer interconnection fabrication techniques is considerably beyond dimensions of semiconductor devices, the signal transmission rate of semiconductor circuit depends on the dead resistance (ParasiticResistance of metal interconnecting layer, R) with parasitic capacitance (ParasiticCapacitance, C) both products, namely RC delays (the ResistanceCapacitanceDelay of metal interconnecting layer, RCDelay), this phenomenon makes the signal transmission rate of semiconductor circuit decline, and reduces the operating rate of semiconductor device.Wherein, dead resistance problem is that metallic aluminium is large as the resistance of metal interconnecting wires, and the material of low resistance, high conductance therefore must be used as metal interconnecting wires.In prior art, generally adopt metallic copper substituted metal aluminium as metal interconnecting wires, be called copper interconnecting line, because metallic copper has higher conductibility, lower resistance than metallic aluminium, dead resistance problem can be solved.
Parasitic capacitance is directly proportional to the dielectric constant k of ILD, and when k is less, parasitic capacitance is less.Silicon dioxide (SiO always as ILD in semiconductor technology
2) dielectric constant be about 3.9 ~ 4.5.Along with the continuous progress of semiconductor technology, silicon dioxide moves closer to limits of application, in order to the signal disturbing that the semiconductor device of the Interaction Law of Electric Current initiation being reduced by metal interconnecting wires transmission is mutual, promote the signaling rate of semiconductor circuit and the operating rate of semiconductor device, the ILD (low-kILD) started with low-k replaces the ILD of traditional silicon dioxide.The method reducing ILD dielectric constant has two kinds: 1. adopt the material that valence electron closely fetters; 2. the porous membrane with a large amount of cavity is adopted, such as: porous SiC O.Prior art generally adopts the method for doping carbon atom in silicon dioxide, increase space between silica atoms, make the lattice structure of silicon dioxide become loose, its dielectric constant is reduced to less than 3, or be less than the black diamond (BD) of 3 as low-kILD with dielectric constant.
The manufacture method of the metal interconnecting layer of low-kILD and copper interconnecting line is adopted to be called copper wiring technique in prior art, because metallic copper is not easy to dry etching, so traditional wiring technique can not be used, current copper wiring technique generally adopts embedded process, namely the technique of dual damascene.Dual damascene process for copper-connection is generally divided into two kinds: one first does through hole, then does groove (Viafirst); One is also had to be first do groove, rear formation through hole (LineFirst).Although the resistivity of metallic copper is low, be limited to the restriction of its material itself, make its application on very lagre scale integrated circuit (VLSIC), until just come into focus because of the breakthrough of CMP technology.The difficulty that copper is applied in very lagre scale integrated circuit (VLSIC) by copper wiring technique mainly because: 1, the halid vapour pressure of copper is not high enough, therefore not easily with the existing definition carrying out copper-connection figure in method lithographic technique; 2, the oxidation of copper has self limit (Self-limiting) unlike aluminium, if therefore dealt with improperly, whole piece copper interconnecting line will be made to be oxidized to cupric oxide (CuO).Cu-W ore deposit is an important topic of very lagre scale integrated circuit (VLSIC) always.3, utilize cmp (CMP) technology of copper, adopt dual damascene to carry out the realization of copper-connection.For second and thirdly difficulty, then must use and can stop that copper atom spreads, and the barrier layer (BarrierLayer) of copper surface oxidation can be prevented.
We are for viaFirst dual damascene process below, simply introduce multilayer interconnection technology.Composition graphs 2 ~ 9 is introduced viafirst multilayer interconnection technological process flow chart as shown in Figure 1, and in prior art, the technological process of viafirst multilayer interconnection comprises the following steps:
Step 101, Fig. 2 is the cross-sectional view of the step 101 of metal interconnecting method in prior art, as shown in Figure 2, interlayer dielectric on the first metal interconnecting layer;
Wherein, the first metal interconnecting layer is copper interconnecting line, at this, is only described metal interconnecting method of the prior art for the first metal interconnecting layer, and shown first metal interconnecting layer can be any layer of metal interconnection layer in actual applications.Inter-level dielectric is low-k (1ow-k) material, such as: SiC.
Step 102, Fig. 3 is the cross-sectional view of the step 102 of metal interconnecting method in prior art, as shown in Figure 3, applies the first photoresistance glue (PR) on inter-level dielectric, and a PR is exposed, developed, thus form the first photoengraving pattern;
Wherein, the first photoengraving pattern is used for the A/F of the through hole (via) defined in subsequent step.
In actual applications, under a PR, bottom antireflective coating (BARC) is also coated with.
Step 103, Fig. 4 is the cross-sectional view of the step 103 of metal interconnecting method in prior art, as shown in Figure 4, carries out partial etching according to the first photoengraving pattern to inter-level dielectric, thus forming section through hole;
In this step, after etching forming section through hole, the first photoengraving pattern is peeled off.Specifically, main employing two kinds of methods remove PR, the first, adopt oxygen (O
2) carry out dry etching, there is chemical reaction in oxygen and PR, PR can be removed; The second, also can adopt wet method ashing method, such as, adopt the mixed solution of sulfuric acid and hydrogen peroxide PR can be removed.
Step 104, Fig. 5 is the cross-sectional view of the step 104 of metal interconnecting method in prior art, and as shown in Figure 5, coating the 2nd PR, exposes the 2nd PR, develop, thus forms the second photoengraving pattern.Wherein, the second photoengraving pattern is used for defining the A/F of groove in subsequent step;
Wherein, a part of the 2nd PR is present on inter-level dielectric, and other of the 2nd PR are partially filled in partial through holes.In actual applications, under the 2nd PR, also BARC is coated with.
Step 105, Fig. 6 is the cross-sectional view of the step 105 of metal interconnecting method in prior art, as shown in Figure 6, etches inter-level dielectric according to the second photoengraving pattern, thus forms groove and through hole;
In this step, after etching forms groove and through hole, the second photoengraving pattern is peeled off.
The method of photoresist lift off can refer to description relevant in step 103.
Step 106, Fig. 7 is the cross-sectional view of the step 106 of metal interconnecting method in prior art, as shown in Figure 7, after through hole, groove and inter-level dielectric surface deposition copper seed layer, adopt electrochemistry depositing process (ECP) growing metal copper in through-holes;
Fall to diffusing in inter-level dielectric and inter-level dielectric to prevent the metallic copper deposited in through-holes at subsequent step, before copper seed crystal layer (not shown in FIG.), physical vapour deposition (PVD) (PVD) technique can also be adopted at through hole and inter-level dielectric surface deposition diffusion impervious layer (not shown in FIG.).
Step 107, Fig. 8 is the cross-sectional view of the step 111 of metal interconnecting method in prior art, as shown in Figure 8, adopts chemical mechanical milling tech (CMP) metallic copper, copper seed layer to be polished to the surface of inter-level dielectric;
In this step, after CMP, also has cleaning step.After CMP and cleaning, be arranged in the metallic copper of first medium and copper seed crystal jointly as copper interconnecting line.
Step 108, Fig. 9 is the cross-sectional view of the step 112 of metal interconnecting method in prior art, as shown in Figure 9, adopt the method for ion enhanced chemical vapor deposition (PECVD) at inter-level dielectric and copper interconnecting line surface deposition copper barrier layer (copperdiffusionbarrier);
In this step when metallic copper and low-k dielectric material are introduced in copper wiring technique, special construction due to copper-connection: the diffusion impervious layer that the left and right of copper interconnecting line and bottom have TaN/Ta namely to prevent copper to spread, the surface of copper interconnecting line is then after CMP and cleaning, one deck copper barrier layer is deposited above, the material of copper barrier layer is N doping diamond dust (NDC, NitrogenDopedsiliconCarbide), such as: BN, SiCN or SiN, copper barrier layer can prevent the diffusion of copper on the one hand, on the other hand, because the etch rate of NDC and low-k medium differs greatly, in subsequent step, NDC can also as the etching stop layer (etchstoplayer) of etching through hole in its upper metal interconnection layer.
So far, this flow process terminates.
Although copper interconnecting line substitution of Al interconnection line decreases the electromigration on crystal boundary, but because copper has very strong diffusion property, and new material SiCN instead of the copper barrier layer of SiN as copper interconnecting line surface, the electromigratory predominating path of copper interconnecting line is the surface at copper interconnecting line, the surface characteristic of good copper interconnecting line, and the interface performance between copper and SiCN can greatly improve the electromigratory life-span.
In prior art, at inter-level dielectric and copper interconnecting line surface in the process by PECVD copper blocking layer, due to plasma in PECVD with electric charge can be gathered in the surface of copper interconnecting line, this electrical damage caused due to plasma process is also called plasma damage (Plasmainduceddamage, PID), PID has cumulative bad, and therefore, the PECVD of NDC can cause plasma damage to copper interconnecting line.
Summary of the invention
In view of this, the technical problem that the present invention solves is: in metal interconnected technique, the PECVD of copper barrier layer can cause plasma damage to copper interconnecting line.
For solving the problem, technical scheme of the present invention is specifically achieved in that
A kind of copper barrier layer manufacture method, be applied to the metal interconnecting layer adopting low-k interlayer medium and copper interconnecting line, the wafer with metal interconnecting layer is provided, described metal interconnecting layer comprises described inter-level dielectric and described copper interconnecting line, described copper interconnecting line is arranged in described inter-level dielectric, described copper interconnecting line surface is exposed and parallel with described inter-level dielectric surface, and the method comprises:
Described wafer is placed in chemical vapour deposition reaction chamber;
Keep the vacuum state in described chemical vapour deposition reaction chamber;
Reacting gas is passed in described chemical vapour deposition reaction chamber;
Described reacting gas is made to produce pulse ion body by the pulse power, at copper interconnecting line surface and inter-level dielectric surface pulsed plasma deposition copper barrier layer.
Described reacting gas is the mist containing alkane gas and nitrogenous gas.
Described copper barrier layer is N doping diamond dust.
Described N doping diamond dust is boron nitride, silicon carbon nitride or silicon nitride.
The described pulse power is AC power.
The frequency of the described pulse power is 10 to 100 hertz.
The action time of described pulsed plasma is 1 ~ 98% than scope.
The power bracket of described pulsed plasma deposition is 80 ~ 120 watts.
Also comprise lower powered pre-deposition step before described pulsed plasma deposition, the power bracket of described lower powered pre-deposition is less than or equal to 50 watts.
As seen from the above technical solutions, the invention provides a kind of manufacture method of copper barrier layer, the method pulse plasma chemical vapour deposition (CVD) makes copper barrier layer on same interconnection line surface, can effectively avoid causing plasma damage to copper interconnecting line.
Accompanying drawing explanation
Fig. 1 is multilayer interconnection technological process flow chart in prior art;
Fig. 2 ~ 9 are the cross-sectional view of multilayer interconnection technique in prior art;
Figure 10 is the section structural scheme of mechanism with metal interconnected layer wafer of the present invention;
Figure 11 is copper barrier layer fabrication processing figure of the present invention.
Embodiment
For making object of the present invention, technical scheme and advantage clearly understand, to develop simultaneously embodiment referring to accompanying drawing, the present invention is described in more detail.
The present invention proposes a kind of copper barrier layer manufacture method, the method adopts the surface deposition copper barrier layer of method at copper interconnecting line of PPECVD.
Specific embodiment one
The present invention proposes a kind of copper barrier layer manufacture method, be applied to the metal interconnecting layer adopting low-k interlayer medium and copper interconnecting line.
The following detailed description of copper barrier layer fabrication processing figure of the present invention as shown in figure 11.
As shown in Figure 10, provide the wafer of the metal interconnecting layer had, the making step of described metal interconnecting layer comprises: on the first metal interconnecting layer, first deposit the thin silicon nitride (Si of one deck
3n
4) as diffusion impervious layer and etch stop layer (not shown in FIG.), wherein, first metal interconnecting layer is copper interconnecting line, at this, only be described metal interconnecting method of the prior art for the first metal interconnecting layer, shown first metal interconnecting layer can be any layer of metal interconnection layer in actual applications.Then on the silicon nitride of the first metal interconnecting layer, deposit the inter-level dielectric (ILD) of certain thickness low-k dielectric substance, then make by lithography and make groove (Trench) again by lithography after through hole (via) carries out partial etching to through hole and continue to etch complete through hole and groove; Then be exactly use electroless plating (Electroplating) technique growing metal copper in through hole and groove after being sputtering (PVD) diffusion impervious layer (TaN layer BarrierLayer) and copper seed layer (Seedlayer), finally carry out annealing and chemico-mechanical polishing (CMP, ChemicalMechanicalPolishing), copper surface is carried out planarization and cleaning, form copper interconnecting line, copper interconnecting line surface is exposed and parallel with inter-level dielectric surface.
Step 1101, is placed in chemical vapour deposition (CVD) (CVD) reaction chamber by the wafer with metal interconnecting layer;
Step 1102, keeps the vacuum state in CVD reaction chamber;
This step is identical with prior art PECVD, is prior art, repeats no more.
Step 1103, passes into reacting gas in CVD reaction chamber;
In this step, reacting gas is the mist containing alkane gas and nitrogenous gas; The parameters such as reaction gas flow are prior aries, repeat no more.
In this step, for there is chemical reaction in reacting gas, at medium with low dielectric constant and the copper interconnecting line Surface Creation N doping diamond dust (NDC of metal interconnecting layer, NitrogenDopedsiliconCarbide), such as: boron nitride (BN), silicon carbon nitride (SiCN) or silicon nitride (SiN), as copper barrier layer;
Step 1104, makes reacting gas produce pulse ion body by the pulse power, at copper interconnecting line surface and inter-level dielectric surface pulsed plasma deposition (PPECVD) copper barrier layer;
In this step, control reacting gas by the pulse power (PulsingRFpowersupply) and produce opening (On) and closing (Off) of plasma, when the pulse power is in RFOn state, reacting gas forms plasma, and namely plasma is opened; When the pulse power is in RFOff state, reacting gas does not form plasma.Pulsed plasma action time is 1 ~ 98% than the scope of Pr (ion is opened (On) time/(ion is opened (On) time+plasma close (Off) time)), such as: 1%, 50% or 98%; Owing to alternately opening and closing plasma, inhibit plasma with the accumulation of electric charge.
In this step, the pulse power is AC power (DC), and the relevant parameter of the pulse power comprises: the frequency of the pulse power is 10 to 100 hertz (Hz).
The power bracket of the pulsed plasma deposition in this step is 80 ~ 120 watts, such as: 80 watts, 100 watts or 120 watts.Pre-deposition step can also be comprised before PPECVD, described pre-deposition step is identical with PPECVD is also the PPECVD passing into reacting gas, carry out under low-power unlike described pre-deposition, the power bracket of described pre-deposition is less than or equal to 50 watts, such as 10 watts, 30 watts or 50 watts.
The copper barrier layer manufacture method that the present invention proposes, adopts pulse plasma body chemical vapor phase growing to make copper barrier layer, thus reduces the charge accumulation of plasma thereunder on copper interconnecting line, avoids semiconductor device failure (devicefailure).
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (8)
1. a copper barrier layer manufacture method, be applied to the metal interconnecting layer adopting low-k interlayer medium and copper interconnecting line, the wafer with metal interconnecting layer is provided, described metal interconnecting layer comprises described inter-level dielectric and described copper interconnecting line, described copper interconnecting line is arranged in described inter-level dielectric, described copper interconnecting line surface is exposed and parallel with described inter-level dielectric surface, and it is characterized in that, the method comprises:
Described wafer is placed in chemical vapour deposition reaction chamber;
Keep the vacuum state in described chemical vapour deposition reaction chamber;
Reacting gas is passed in described chemical vapour deposition reaction chamber;
Described reacting gas is made to produce pulse ion body by the pulse power, at copper interconnecting line surface and inter-level dielectric surface pulsed plasma deposition copper barrier layer;
Wherein, the frequency of the described pulse power is 10 to 100 hertz.
2. method according to claim 1, is characterized in that, described reacting gas is the mist containing alkane gas and nitrogenous gas.
3. method according to claim 1, is characterized in that, described copper barrier layer is N doping diamond dust.
4. method according to claim 3, is characterized in that, described N doping diamond dust is silicon carbon nitride.
5. method according to claim 1, is characterized in that, the described pulse power is AC power.
6. method according to claim 1, is characterized in that, the action time of described pulsed plasma is 1 ~ 98% than scope.
7. method according to claim 1, is characterized in that, the power bracket of described pulsed plasma deposition is 80 ~ 120 watts.
8. method according to claim 1, is characterized in that, also comprises lower powered pre-deposition step before described pulsed plasma deposition, and the power bracket of described lower powered pre-deposition is less than or equal to 50 watts.
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