KR20020017171A - method for fabricating semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a semiconductor device is provided to prevent a short circuit between a local interconnection(LI) layer and a nested contact(NC) layer, by making a pair of the first and second NC's shifted to one direction by a misalign error. CONSTITUTION: A gate electrode(106) is formed in a metal-oxide-semiconductor(MOS) transistor formation part(A) on a semiconductor substrate(100) having an active region(102) by interposing a gate insulation layer(104). The first interlayer dielectric(110) is formed on the resultant structure. A predetermined thickness of the first interlayer dielectric is selectively etched to form the first concave part(s1) in a side of the upper edge of the gate electrode. The first interlayer dielectric is selectively etched to expose a part of the upper surface of the gate electrode and the surface of the upper surface. Simultaneously, the second NC(h2) connected to the first NC(h1) and the active region connected to the first concave part and the gate electrode is formed. The LI layer, the first NC plug(112b) and the second NC plug(112c) are respectively formed in the first concave part, the first NC and the second NC by a metal layer deposition process and a planarization process for the metal layer. An etch stopper layer is formed and selectively etched to expose the second NC plug. The second interlayer dielectric is formed, and is etched to expose the etch stopper layer so that the second concave part is formed. A molybdenum metal layer is formed in the second concave part.

Description

Method for fabricating semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, the present invention relates to a method of preventing short circuits between local interconnection (LI) layers and S / N (Nested Contact) plugs forming SRAMs, and to prevent contact not open. The present invention relates to a method for manufacturing a semiconductor device capable of preventing short circuiting between the LI layer and the Mo metal layer due to overetching.

As high integration of semiconductor integrated circuits proceeds, technology development is being made in a direction that minimizes chip size while enabling high speed. Accordingly, in recent years, a finer level of process progress is required for fine pattern processing. However, when manufacturing devices (particularly SRAMs) in accordance with the high speed and high integration trends that are currently oriented in the semiconductor process, various problems arise in the micro pattern processing due to the limitation of the photo process. Among them, the problem of securing short margin between the LI layer and the NC plug and the problem of NC contact open failure due to high contact step have a fatal effect on the integration and scale down of semiconductor devices. It is greatly highlighted.

This will be described in detail with reference to the process flowchart showing the conventional SRAM manufacturing method shown in FIGS. 1A to 1E. According to the process purity, it can be seen that the conventional SRAM device is manufactured through the following fifth step process.

As a first step, as shown in FIG. 1A, the active region 12 is formed near the surface of the silicon substrate 10 through an ion implantation process, and the active region 12 is formed in the MOS transistor forming portion A on the substrate 10. ) To form a gate electrode 16 of polysilicon by partially interposing the gate insulating layer 14 to form a portion thereof, and then forming an insulating spacer 18 on the sidewall thereof.

As a second step, as shown in FIG. 1B, the first interlayer insulating layer 20 is formed on the resultant and then planarized by CMP treatment, and then the first interlayer insulating layer 20 is formed using a mask defining a LI layer forming unit. Selectively etching a predetermined thickness to form a first groove portion (S1) on the top of one side edge portion of the gate electrode (16). Subsequently, the first interlayer insulating layer 20 is selectively etched so as to expose a predetermined portion of the top surface of the gate electrode 16 by using a mask defining the first NC forming portion, thereby being integrally connected to the first recess S1. The first NC h1 is formed. Thereafter, a metal layer of W material is formed on the resultant product so as to sufficiently fill the first recess S1 and the inside of the first NC h1, and the CMP process is performed on the resultant product. 22b) and the LI layer 22a are formed in the 1st recessed part S1.

As a third step, as shown in FIG. 1C, a second interlayer insulating layer 24 is formed on the resultant product, and a second thickness of the second interlayer insulating layer 24 is selectively etched using a mask defining a Mo metal layer forming portion. 1 A second recess S2 is formed at the upper end of the NC plug 22b and at the upper end of the active region between the gate electrodes 16 adjacent to each other.

As a fourth step, as shown in FIG. 1D, the first and second portions of the lower end of the second recess portion S2 are exposed using a mask defining the second NC forming portion to partially expose the surface of the active region 12 between the gate electrodes 16. The second interlayer insulating films 20 and 24 are selectively etched to form a second NC h2 having a structure in which the second interlayer insulating films 20 and 24 are integrally connected to the second recess h2. At this time, the second NC (h2) is formed in a width smaller than the second groove portion (S2) in order to secure a short margin between the LI layer (22a) and the NC plug to be formed later.

As a fifth step, as shown in FIG. 1E, a metal layer of W material is formed on the resultant material so that the inside of the second recess S2 and the second NC h2 are sufficiently filled, and the CMP process is performed to form the metal layer of the second recess S2. ), The process proceeds by completing the Mo metal layer 26a and the second NC plug 26b in the second NC h2.

As a result, the LI layer 22a in the first recess S1 and the first NC plug 22b in the first NC h1 are electrically connected, and the Mo metal layer 26a in the second recess S2 is electrically connected. And an SRAM element having a structure in which the second NC plug 26b in the second NC h2 is electrically connected to each other.

However, in the case of forming a pattern using a pair of the LI layer 22a and the first NC plug 22b and a pair of the Mo metal layer 26a and the second NC plug 26b as described above, The same problem occurs.

First, when a misalignment occurs when forming the first recessed part S1, the first NC is automatically pushed to one side by the error value, so that the pattern is formed, thereby etching the second NC. Even if a slight alignment error occurs during the process, the possibility of a short is generated between the LI layer 22a and the plug 26b in the second NC h2.

Second, since the second NC (h2) is formed by sequentially etching the first and second interlayer insulating films 20 and 24 at the bottom after the formation of the second recess portion h2, Due to the step difference, a contact open failure occurs in which the active region is not opened properly.

Third, the thickness of the remaining interlayer insulating layer 24 between the Mo metal layer 26a and the LI layer 22a is thin so that the LI layer 22a may be formed even when only a little overetch occurs during the etching process for forming the second recess. ) And Mo metal layer 26a are short-circuited.

Accordingly, an object of the present invention is to simultaneously form the first NC and the second NC in a single photo process when forming an SRAM, thereby preventing short circuits between the LI layer and the second NC plug due to misalignment, resulting in a large step difference. The present invention provides a method of manufacturing a semiconductor device capable of preventing the occurrence of contact open defects.

Another object of the present invention is to overetch by performing a second recessed part forming process for forming a Mo metal layer in a state where an etch stopper layer having a higher etching selectivity compared to an interlayer insulating layer is additionally provided between the Mo metal layer and the LI layer. The present invention provides a method of manufacturing a semiconductor device capable of preventing the occurrence of a short between the LI layer and the Mo metal layer caused by

1A to 1E are process flowcharts showing a conventional SRAM manufacturing method;

2A to 2D are process flowcharts showing a SRAM manufacturing method according to the present invention.

In order to achieve the above object, the present invention includes the steps of forming a gate electrode by interposing a gate insulating layer in the MOS transistor forming portion on the semiconductor substrate provided with an active region; Forming a first interlayer insulating layer on the resultant; Selectively etching the first interlayer dielectric layer to form a first recess on an edge portion of the gate electrode; The first recessed layer may be selectively etched to partially expose an upper surface of the gate electrode and a surface of the active region therebetween by using a mask defining a first NC forming portion and a second NC forming portion. Forming a first NC connected to the gate electrode and a second NC connected to the active region; Forming a LI layer in the first recess, a first NC plug in the first NC, and a second NC plug in the second NC through metal layer deposition and planarization; Forming an etch stopper layer of insulating material on the resultant material; Selectively etching the etch stopper layer to expose the second NC plug; Forming a second interlayer insulating layer on the resultant; Forming a second recess by selectively etching the second interlayer insulating layer until the surface of the etch stopper layer is exposed using a mask defining a Mo metal layer forming portion; And forming a Mo metal layer in the second recess through the metal layer deposition and the planarization thereof.

When manufacturing the SRAM based on the process procedure, since the second NC is also formed at the time of forming the first NC, the step difference caused in the process of forming the second NC can be significantly reduced than before. It is possible to prevent the occurrence of open failures. Also, even if misalignment is caused in the process of forming the first recess, the LI layer and the second layer are shifted in one direction by the error value of the first NC and the second NC in a subsequent process. Short defects between the NC plugs do not occur. In addition, since the etching process of the interlayer insulating layer for forming the second recess is further performed between the Mo metal layer and the LI layer, an etch stopper layer of an insulating material having a higher etching selectivity relative to the interlayer insulating layer is further formed. This can prevent over-etching from occurring.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2A to 2D illustrate a process flowchart showing the SRAM fabrication method proposed in the present invention. Referring to this, the fabrication method is classified into a fourth step as follows.

As a first step, as shown in FIG. 2A, an active region 102 is formed near the surface of the silicon substrate 100 through an ion implantation process, and the active region 102 is formed in the MOS transistor forming unit A on the substrate 100. ) To form a gate electrode 106 of polysilicon by partially interposing the gate insulating layer 104 to form an insulating spacer 108 on the sidewall of the gate insulating layer 104.

As a second step, as shown in FIG. 2B, the first interlayer insulating layer 110 is formed on the resultant and then planarized by CMP treatment, and then the first interlayer insulating layer 110 is formed using a mask defining a LI layer forming unit. Selectively etching a predetermined thickness to form a first groove portion (S1) on the top of one side edge portion of the gate electrode (16). Next, the first interlayer insulating layer 110 is selected to partially expose the top surface of the gate electrode 106 and the surface of the active region 102 therebetween by using a mask defining the first NC forming portion and the second NC forming portion. By etching, a first NC h1 connected to the first recess S1 and the gate electrode 106 and 2 NC h2 connected to the active region 102 are simultaneously formed. As such, the first NC (h1) and the second NC (h2) are simultaneously formed in one photo process, even if a misalignment is caused in the process of forming the first recess (S1). Since the second NC h2 is paired and shifted simultaneously in one direction by the error value, a short between the LI layer formed in the first recess S1 and the plug formed in the second NC h2 during the subsequent process. This can be prevented from occurring. Subsequently, a metal layer of W material is formed on the resultant product so as to sufficiently fill the first recessed portion S1 and the first NC h1 and the second NC h2, and the CMP process is performed to process the first NC h1. The 1st NC plug 112b is formed in inside, the 2nd NC plug 112c is formed in 2nd NC h2, and the LI layer 22a is formed in 1st recessed part S1.

As a third step, an etch stopper layer 114 of nitride film material is formed on the resultant product as shown in FIG. 2C and selectively etched to expose the surface of the second NC plug 112c. As such, the additional formation of the etch stopper layer 114 of the nitride film material having a relatively high etching selectivity relative to the interlayer insulating layer 110 may be performed by increasing the thickness of the remaining interlayer insulating layer between the Mo metal layer to be formed and the LI layer 112a. This is to fundamentally prevent a defect caused by thinness (for example, a defect in which the LI layer 112a and the Mo metal layer are shorted even if only a little overetch occurs during the etching process for forming the second recessed portion).

As a fourth step, as shown in FIG. 2D, a second interlayer insulating layer 116 is formed on the resultant and selected until the surface of the etch stopper layer 114 is exposed using a mask defining a Mo metal layer forming portion. By etching, second recesses S2 are formed at the upper end of the first NC plug 112b and the upper end of the active region between the gate electrodes 106 adjacent to each other. Subsequently, the metal layer of W material is formed on the resultant material so that the inside of the second recess S2 is sufficiently filled, and the CMP process is performed to form the Mo metal layer 118 in the second recess S2. To complete.

As a result, the LI layer 112a in the first recess S1 and the first NC plug 112b in the first NC h1 are electrically connected, and the Mo metal layer 118 in the second recess S2 is electrically connected. And the SRAM element having a structure in which the second NC plug 112c in the second NC h2 is electrically connected.

In this case, since the first NC and the second NC are simultaneously formed by one photo process, even if a misalignment is caused in the process of forming the first recess, the first NC and the second NC are used during the subsequent process. The pattern is formed to be shifted in one direction at the same time by the error value. Therefore, the short between the LI layer and the second NC plug does not occur.

In addition, in this case, since the step difference caused in the process of forming the second NC can be significantly reduced than before, it is possible to prevent contact open defects caused by the depth of focus limitation during the photo process.

In addition, since the etching process for forming the second recess is further performed between the Mo metal layer and the LI layer, an etch stopper layer having a higher etching selectivity compared to the interlayer insulating layer is additionally formed. The additional effect of preventing the occurrence of a short between the LI layer and the Mo metal layer can be obtained by blocking the occurrence.

As described above, according to the present invention, 1) since the SRAM is made so that the second NC is also formed at the time of forming the first NC, even if a misalignment is caused, the first NC and the second NC are paired with each other as much as the error value. Simultaneously shifted in one direction, it is possible not only to prevent short circuit between the LI layer and the second NC plug, but also to prevent contact open failure due to a step difference, and (2) an interlayer insulating layer between the Mo metal layer and the LI layer. The second groove forming process for forming the Mo metal layer is performed while the etch stopper layer having a higher etching selectivity with a higher ratio is added. Therefore, it is possible to fundamentally prevent over-etching during the interlayer insulating layer etching. It is possible to prevent the occurrence of short between the metal layers.

Claims (3)

Forming a gate electrode by interposing a gate insulating layer on the MOS transistor forming portion on the semiconductor substrate provided with the active region; Forming a first interlayer insulating layer on the resultant; Selectively etching the first interlayer dielectric layer to form a first recess on an edge portion of the gate electrode; The first recessed layer may be selectively etched to partially expose an upper surface of the gate electrode and a surface of the active region therebetween by using a mask defining a first NC forming portion and a second NC forming portion. And simultaneously forming a first NC connected to the gate electrode and a 2 NC connected to the active region; Forming a LI layer in the first recess, a first NC plug in the first NC, and a second NC plug in the second NC through metal layer deposition and planarization; Forming an etch stopper layer of insulating material on the resultant material; Selectively etching the etch stopper layer to expose the second NC plug; Forming a second interlayer insulating layer on the resultant; Forming a second recess by selectively etching the second interlayer insulating layer until the surface of the etch stopper layer is exposed using a mask defining a Mo metal layer forming portion; And Forming a Mo metal layer in the second recess through the metal layer deposition and planarization thereof. The method of claim 1, wherein the etch stopper layer is formed of a nitride film. The method of claim 1, wherein the LI layer, the Mo metal layer, and the first and second NC plugs are formed of a W material.