KR20020004767A - Method of Driving Plasma Display Panel with Five Electrodes - Google Patents

Abstract

PURPOSE: A method for driving a five electrode plasma display panel is provided to improve efficiency of a five electrode plasma display panel by generating a long cap sustain discharge. CONSTITUTION: A five electrode plasma display panel is formed with an address electrode, a scan electrode formed to a vertical direction of the address electrode, a trigger electrode parallel to the scan electrode, and the first and the second sustain electrodes parallel to the scan electrode. An address discharge process is performed to select a display cell from a panel by supplying simultaneously pulses to the address electrode, the scan electrode, and the first sustain electrode. A sustain discharge process is performed to generate a sustain discharge by supplying the pulses to the first and the second sustain electrodes in order to maintain discharge of the selected cell.

Description

Method of Driving Plasma Display Panel with Five Electrodes

The present invention relates to a driving method of a five-electrode plasma display panel, and more particularly, to a driving method of a five-electrode plasma display panel having a long gap sustain discharge for obtaining high efficiency and capable of stable addressing at low voltage and at high speed. Recently, a plasma display panel (hereinafter referred to as "PDP"), which is easy to manufacture a large panel, has attracted attention as a flat panel display device. As a PDP, a three-electrode AC surface discharge type PDP having three electrodes and driven by an alternating voltage is typical.

Referring to FIG. 1, a discharge cell of a three-electrode alternating surface discharge type PDP is formed on a scan / hold electrode 12Y and a common sustain electrode 12Z formed on an upper substrate 10, and a lower substrate 18. An address electrode 20X is provided. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan / suspension electrode 12Y and the common sustain electrode 12Z side by side. Wall charges generated during plasma discharge are accumulated in the upper dielectric layer 14. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge, and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the scan / sustain electrode 12Y and the common sustain electrode 12Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space provided between the upper and lower plates and the partition wall.

These discharge cells are arranged in the form of a matrix as shown in FIG. In FIG. 2, the discharge cell 1 is provided at the intersection of the scan / sustain electrode lines Y1 to Ym, the common sustain electrode line Z, and the address electrode lines X1 to Xn. The scan / sustain electrode lines Y1 to Ym are sequentially driven, and the common sustain electrode line Z is commonly driven. The address electrode lines X1 to Xn are driven by being divided into odd-numbered lines and even-numbered lines.

The three-electrode AC surface discharge type PDP is driven by being divided into a plurality of subfields, and gray scale display is performed by emitting light a number of times proportional to the weight of video data in each subfield period. For example, when an image is displayed in 256 gray scales using 8-bit video data, one frame display period (for example, 1/60 second = about 16.7 msec) in each discharge cell 1 is shown in FIG. As shown in the figure, the data is divided into eight subfields SF1 to SF8. Each subfield SF1 to SF8 is further divided into a reset period, an address period and a sustain period, and 1: 2: 4: 8:... The weight is given at the ratio of 128. Here, the reset period is a period for initializing the discharge cells, the address period is a period during which selective address discharge occurs according to the logic value of the video data, and the sustain period is such that discharge is maintained in the discharge cells in which the address discharge has occurred. It is a period. The reset period and the address period are equally assigned to each subfield period.

4, a driving waveform diagram supplied to the PDP shown in FIG. 2 during an arbitrary subfield period is shown according to the conventional PDP driving method. First, all discharges are generated by supplying writing pulses to the scan / hold electrode lines Y1 to Ym and the common sustain electrode lines Z1 to Zm in a reset period (not shown) to cause discharge to occur in all discharge cells. Initialize the cells. Following the reset period, in the address period, the scan pulse SP is sequentially supplied to the scan / sustain electrode lines Y1 to Ym, and the data pulse DP synchronized with the scan pulse SP is applied to the address electrode lines. Supplying to (X1 to Xn) causes selective address discharge to occur. Subsequently, in the discharge sustain period, the address discharge is generated by alternately supplying the sustain pulse SUSP to the scan / hold electrode lines Y1 to Ym and the common sustain electrode lines Z1 to Zm. The discharge in the cells is maintained for a predetermined period of time.

However, in the conventional three-electrode PDP, since the sustain discharge between the scan / sustain electrode 5 and the common sustain electrode 8 causing the sustain discharge occurs only at the center of the discharge cell, the space of the discharge cell was not sufficiently utilized. Accordingly, there is a problem that the luminance of the discharge cells is lowered and the luminous efficiency is lowered. In order to solve this problem, the scan / sustain electrode 5 and the common sustain electrode 8 which cause a sustain discharge are provided at both edges of the discharge cell or the width of the discharge electrode is widened. However, when the distance between the scan / sustain electrode 5 and the common sustain electrode 8 increases, the discharge voltage increases, and when the width of the discharge electrode is widened, the discharge current also increases, thereby increasing power consumption.

In order to solve this problem, a 5-electrode AC surface discharge type PDP has been developed and commercialized as shown in FIG. 5.

Fig. 5 is a perspective view showing a five-electrode alternating surface discharge type PDP.

Referring to FIG. 5, a discharge cell of a 5-electrode PDP includes a scan / sustain electrode 45, a common sustain electrode 58, a scan electrode 40, and a trigger electrode 66 on an upper substrate 50. In addition, an address electrode 60 is provided on the lower substrate 55. The scan electrode 40 and the trigger electrode 66 are composed of transparent electrodes 48A and 66A and bus electrodes 48B and 64B. The scan electrode 40 and the trigger electrode 66 are arranged in parallel between the scan / sustain electrode 45 and the common sustain electrode 58 at narrow intervals, and the electrodes 45, 40, 66, and 58 are formed. An upper dielectric layer 51 and a protective layer 52 are stacked on the upper substrate 50. The wall charges generated during the plasma discharge are accumulated in the upper dielectric layer 51. The protective layer 52 prevents damage to the upper dielectric layer 51 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective layer 52, magnesium oxide (MgO) is usually used. The lower dielectric layer 64 and the partition wall 53 are formed on the lower substrate 55 on which the address electrode 60 is formed, and the phosphor layer 62 is coated on the surfaces of the lower dielectric layer 64 and the partition wall 53. The address electrode 60 is formed in a direction crossing the scan / sustain electrode 45, the common sustain electrode 58, the scan electrode 40, and the trigger electrodes 66. The partition wall 53 is formed in parallel with the address electrode 60 to prevent the ultraviolet rays and the visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 62 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space 62 provided between the upper and lower plates 50 and 55 and the partition wall 53.

Briefly, the process of emitting light is first performed in one of the scan / sustain electrode 45 or the scan electrode 40 and the trigger electrode 66 disposed inside all the discharge cells in order to initialize all the discharge cells of the panel. Reset pulse is supplied to reset discharge. During the reset discharge, wall charges are generated for each discharge cell to lower the discharge voltage required for the subsequent address discharge. Then, a scan pulse is supplied to the scan / sustain electrode 45, and a data pulse is applied to the address electrode 60 in synchronization with the scan / sustain electrode 45 so that an address discharge occurs between the two electrodes, so that wall charges are applied to the upper and lower dielectric layers 50 and 55. Is formed. In the discharge cells selected by the address discharge, the scan electrode 40 and the trigger electrode 66 provided between the scan / sustain electrode 45 and the common sustain electrode 58 respond to the trigger pulse voltage which is an alternating pulse voltage during the sustain period. To cause secondary discharge. Immediately after the auxiliary discharge occurs, sustain pulses are supplied to the scan / sustain electrodes 45 and the common sustain electrodes 58. Then, the scan / sustain electrode 45 and the common sustain electrode 58 can cause discharge in the center portion of the cell due to the wall charge accumulated in the discharge cell by the auxiliary discharge and the voltage difference caused by the sustain pulse. Such sustain discharge is continuously generated by the sustain pulse and the trigger pulse.

As described above, a PDP having a five-electrode structure has been proposed for high efficiency, but since a driving method is not provided, it is difficult to actually implement.

Accordingly, an object of the present invention is to provide a driving method having a long gap sustain discharge for obtaining high efficiency in a 5-electrode surface discharge AC plasma display panel, and capable of stable addressing at low voltage and at high speed.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge plasma display panel.

FIG. 2 is an electrode arrangement diagram of the plasma display panel shown in FIG. 1. FIG.

3 is a frame diagram illustrating a method of driving a subfield of a discharge cell shown in FIG. 1.

4 is a driving waveform diagram of the discharge cell shown in FIG.

5 is a perspective view showing a discharge cell structure of a conventional 5-electrode AC surface discharge plasma display panel.

FIG. 6 is a sectional view of the plasma display panel shown in FIG. 5; FIG.

7 is an electrode arrangement diagram of the plasma display panel shown in FIG.

8 is a driving waveform diagram of a plasma display panel driving method according to an embodiment of the present invention;

<Description of Symbols for Main Parts of Drawings>

10, 50: upper substrate 12Y, Ys, 45: first sustain electrode

12Z, Zs, 58: second sustain electrode 14: upper dielectric layer

16: protective film 18, 55: lower substrate

20X, X, 60: address electrode 22, 64: lower dielectric layer

24, 61: partition 26, 62: phosphor

1: discharge cell 30: PDP

34A, 36A, 44A, 48A, 52A, 54A, 57A, 64A, Transparent electrode

34B, 36B, 44B, 48B, 52B, 54B, 57B, 64B: Bus electrodes

34C, 36C, 521C, 54C: pad electrode

In order to achieve the above objects, the present invention provides an address electrode, a scan electrode formed in a direction orthogonal to the address electrode, a trigger electrode formed in parallel with the scan electrode, and first and second electrodes formed in parallel with the scan electrode. A driving method of a five-electrode plasma display panel having a sustain electrode, comprising: an addressing discharge step of supplying pulses to the address electrode, the scan electrode, and the first sustain electrode simultaneously to generate an addressing discharge for selecting a display cell in the panel Wow; And a sustain discharge step of supplying pulses to the first and second sustain electrodes to sustain the discharge of the selected display cell.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 6 to 8.

6 is a cross-sectional view illustrating an electrode structure of the five-electrode PDP illustrated in FIG. 5, and FIG. 7 is a diagram illustrating an electrode arrangement of the five-electrode PDP illustrated in FIG. 5.

6 to 7, first, the discharge cells of the 5-electrode PDP include the scan / sustain electrode 45, the common sustain electrode 58, the scan electrode 40, and the trigger on the upper substrate 50. The electrode 66 is provided, and the address electrode 60 is provided on the lower substrate 55. The scan electrode 40 and the trigger electrode 66 are composed of transparent electrodes 48A and 64A and bus electrodes 48B and 64B. The scan electrode 40 and the trigger electrode 66 are arranged in parallel between the scan / sustain electrode 45 and the common sustain electrode 58 at narrow intervals, and the electrodes 45, 40, 66, and 58 are formed. An upper dielectric layer and a protective layer (not shown) are stacked on the upper substrate 50. Wall charges generated during plasma discharge are accumulated in the upper dielectric layer. The protective layer prevents damage to the upper dielectric layer due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. Magnesium oxide (MgO) is normally used as a protective layer. A dielectric layer and a partition wall (not shown) are formed on the lower substrate 55 on which the address electrode 60 is formed, and a phosphor layer (not shown) is applied to the lower dielectric layer and the partition wall surface. The address electrode 60 is formed in a direction crossing the scan / sustain electrode 45, the common sustain electrode 58, the scan electrode 40, and the trigger electrodes 66. The partition wall is formed in parallel with the address electrode 60 to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space 24 provided between the upper and lower plates 50 and 55 and the partition wall.

8 shows driving waveforms of a five-electrode PDP according to the present invention.

Referring to FIG. 8, first, in the reset period, negative wall charges are accumulated on the scan / sustain electrode Ys and the scan electrode Yt, and the common electrode Zs and the trigger electrode Zt. A reset pulse is commonly supplied to accumulate positive wall charges in the wall, so that reset discharge is generated so that the wall charge remains uniformly so as not to cause false discharge inside the discharge cells. Following the reset period, the scan pulse is simultaneously supplied to both the scan / sustain electrode Ys and the scan electrode Yt in the address period, and the data pulse is supplied to the address electrode to scan / sustain electrode Ys. And the discharge area between the scan electrode Yt and the address electrode is increased to generate stable address discharge at low voltage and at high speed. In addition, a negative voltage for sustain discharge during addressing discharge is applied to the common electrode Zs and the trigger electrode Zt by applying a high voltage bias to the scan / sustain electrode Ys and the scan electrode Yt. ) Forms a wall charge. In the sustain period, the sustain pulse is applied to the scan / sustain electrode Ys and the scan electrode Yt in the sustain period, and the common electrode Zs and the trigger electrode Zt are applied to the common electrode Zs and the trigger electrode Zt. The scan pulse is applied between the scan electrode Yt and the trigger electrode Zt by applying a sustain pulse of the same phase having a phase opposite to that of the sustain pulse applied to the scan / sustain electrode Ys and the scan electrode Yt. The discharge voltage is lowered while facilitating long-gap sustain discharge between the sustain electrode Ys and the common electrode Zs. The first sustain pulse is applied to the scan / sustain electrode Ys and the scan electrode Yt, and the sustain pulse voltages of the scan / sustain electrode Ys and the common electrode Zs are the scan electrode Yt and the trigger electrode Zt. Higher level causes longer gap sustain discharge. In addition, scan / sustain electrode Ys and scan electrode Yt are applied to scan / sustain electrode Ys and scan electrode Yt to prevent scan driver ICs from increasing due to different sustain voltages. The scan / sustain electrode Ys and the scan electrode Yt are grouped together to drive the same sustain voltage. In the last erasing period, an erasing discharge occurs by supplying an erase pulse to the common electrode Zs and the trigger electrode Zt, thereby erasing the sustain discharge in the previous step.

As described above, the present invention provides a long gap sustain discharge to obtain high efficiency while simultaneously supplying the same pulses to the first sustain electrode and the scan electrode in the 5-electrode surface discharge AC plasma display panel, and at the same time provides stable addressing at low voltage and high speed. This is possible.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (5)

A five-electrode plasma display panel having an address electrode, a scan electrode formed in a direction orthogonal to the address electrode, a trigger electrode formed parallel to the scan electrode, and first and second sustain electrodes formed parallel to the scan electrode In the driving method of, An addressing discharge step of simultaneously supplying pulses to the address electrode, the scan electrode and the first sustain electrode to generate an addressing discharge for selecting a display cell in the panel; And a sustain discharge step of supplying a pulse to the first and second sustain electrodes to cause a sustain discharge so that the discharge of the selected display cell is maintained. The method of claim 1, In the sustain discharge step, a pulse having the same phase is supplied to the first sustain electrode and the scan electrode, And a pulse of opposite phase is applied to the second sustain electrode and the trigger electrode. The method of claim 1, Simultaneously supplying the same pulse to the first sustain electrode and the scan electrode to generate a reset discharge; And simultaneously supplying pulses to the second sustain electrode and the trigger electrode to generate an erasing discharge. The method of claim 1, And supplying an erase pulse to any one of the first sustain electrode and the scan electrode and the second sustain electrode and the trigger electrode to generate an erase discharge. The method of claim 1, And a magnitude of the pulse voltage applied to the common electrode rather than the pulse voltage supplied to the trigger electrode.