KR20020003043A - Method for forming contact in semiconductor device - Google Patents
Method for forming contact in semiconductor device Download PDFInfo
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- KR20020003043A KR20020003043A KR1020000037442A KR20000037442A KR20020003043A KR 20020003043 A KR20020003043 A KR 20020003043A KR 1020000037442 A KR1020000037442 A KR 1020000037442A KR 20000037442 A KR20000037442 A KR 20000037442A KR 20020003043 A KR20020003043 A KR 20020003043A
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- contact
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 150000004767 nitrides Chemical class 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000004140 cleaning Methods 0.000 claims abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 125000006850 spacer group Chemical group 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract description 3
- 239000002019 doping agent Substances 0.000 abstract 1
- 230000004888 barrier function Effects 0.000 description 7
- 239000002184 metal Substances 0.000 description 6
- 239000012535 impurity Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 BLC(BorderLess Contact)의 하부면적을 확보하도록 한 콘택의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact for securing a lower area of a borderless contact (BLC).
최근에, 소자의 집적도가 증가함에 따라 콘택 마진(contact margin)을 확보하기 위해 활성영역과 필드 영역 또는 도전층패턴과 활성영역을 동시에 오픈하는 보더리스 콘택(Boderless Contact)공정이 이용된다.Recently, a borderless contact process of simultaneously opening an active region and a field region or a conductive layer pattern and an active region is used in order to secure a contact margin as the degree of integration of the device increases.
도 1a 내지 도 1c는 종래기술에 따른 BLC의 형성 방법을 도시한 도면이다.1A to 1C illustrate a method of forming a BLC according to the prior art.
도 1a에 도시된 바와 같이, 반도체기판(11)상에 스페이서(12a)를 구비한 게이트전극(12)을 형성한 후, 상기 반도체기판(11)에 고농도 불순물 이온주입을 실시하여 소오스/드레인(13)을 형성한다. 이어 상기 구조 전면에 질화막(14), 산화막 (15)을 순차적으로 형성한 다음, 상기 산화막(15)상에 감광막을 도포하고 노광 및 현상으로 패터닝한다. 이어 상기 패터닝된 감광막(도시 생략)을 마스크로 이용하여 상기 산화막을 선택적으로 식각한다.As shown in FIG. 1A, after the gate electrode 12 having the spacers 12a is formed on the semiconductor substrate 11, a high concentration of impurity ions are implanted into the semiconductor substrate 11 to obtain a source / drain ( 13). Subsequently, the nitride film 14 and the oxide film 15 are sequentially formed on the entire structure, and then a photosensitive film is coated on the oxide film 15 and patterned by exposure and development. Subsequently, the oxide film is selectively etched using the patterned photoresist (not shown) as a mask.
도 1b에 도시된 바와 같이, 계속해서 상기 질화막(14)을 선택식각하여 소오스/드레인(13)이 노출되는 콘택홀을 형성한다. 이 때, 상기 콘택홀 형성시 산화막 (15), 질화막(14), 반도체기판(11)과의 선택비를 향상시키기 위해 슬로프식각 (Slope etch)을 실시한다. 이 때, 상기 슬로프식각으로 인해 콘택바닥에 질화막의 잔막(Residue)(14a)이 형성된다.As shown in FIG. 1B, the nitride layer 14 is selectively etched to form a contact hole through which the source / drain 13 is exposed. At this time, a slope etch is performed to improve the selectivity with respect to the oxide film 15, the nitride film 14, and the semiconductor substrate 11 when forming the contact hole. At this time, a residual film 14a of a nitride film is formed on the contact bottom due to the slope etching.
도 1c에 도시된 바와 같이, 후속 배리어메탈 증착전에 전세정(Pre cleaning)을 실시하면, 상기 질화막(14)의 측면방향으로 산화막(16)이 형성되므로써 콘택오픈영역이 감소되어 콘택오픈오류(Contact open fail) 및 잔막으로 인한 콘택저항이 증가하는 문제점이 있다.As shown in FIG. 1C, when pre-cleaning is performed before the subsequent barrier metal deposition, the contact open area is reduced by forming the oxide film 16 in the lateral direction of the nitride film 14, thereby causing a contact open error (Contact). There is a problem that the contact resistance due to the open fail) and the residual film increases.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 배리어메탈 전세정공정에 의해 오픈될 콘택영역을 미리 확보하여 콘택오픈의 불량 및 콘택저항의 증가를 방지하는데 적합한 반도체소자의 콘택 형성 방법을 제공함에 그 목적이 있다.The present invention has been made to solve the problems of the prior art, a method for forming a contact of a semiconductor device suitable for preventing contact open defects and increase in contact resistance by securing a contact area to be opened by a barrier metal pre-cleaning process in advance. The purpose is to provide.
도 1a 내지 도 1c는 종래기술에 따른 BLC의 형성 방법을 나타낸 도면,1a to 1c is a view showing a method of forming a BLC according to the prior art,
도 2a 내지 도 2c는 본 발명의 실시예에 따른 BLC의 형성 방법을 나타낸 도면.2A-2C illustrate a method of forming a BLC according to an embodiment of the invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체기판 22 : 게이트전극21 semiconductor substrate 22 gate electrode
23 : 소오스/드레인 24 : 질화막23 source / drain 24 nitride layer
25 : 산화막25: oxide film
상기의 목적을 달성하기 위한 본 발명은 게이트전극이 형성된 반도체기판상에 질화막, 산화막을 순차적으로 형성하는 제 1 단계; 상기 산화막상에 감광막을 도포하고 노광 및 현상으로 선택적으로 패터닝하여 콘택마스크를 형성하는 제 2 단계; 상기 콘택마스크를 이용하여 슬로프 프로파일을 갖도록 상기 산화막을 선택적으로 식각하는 제 3 단계; 상기 제 3 단계후 노출된 상기 질화막을 습식식각하여 상기 게이트전극과 상기 반도체기판을 동시에 노출시키되, 후속 세정에 의해 오픈될 영역만큼 콘택홀의 측면방향으로 상기 질화막을 손실시키는 제 4 단계; 및 상기 제 4 단계후 손실된 영역만큼 세정공정을 실시하여 수직프로파일을 갖는 콘택홀을 형성하는 제 5 단계를 포함하여 이루어짐을 특징으로 한다.The present invention for achieving the above object is a first step of sequentially forming a nitride film and an oxide film on a semiconductor substrate on which a gate electrode is formed; Applying a photoresist film on the oxide film and selectively patterning the photoresist film by exposure and development to form a contact mask; Selectively etching the oxide layer to have a slope profile using the contact mask; A fourth step of wet-etching the exposed nitride film after the third step to expose the gate electrode and the semiconductor substrate at the same time, but to lose the nitride film in the lateral direction of the contact hole by an area to be opened by subsequent cleaning; And a fifth step of forming a contact hole having a vertical profile by performing the cleaning process as much as the lost area after the fourth step.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2c는 종래기술에 따른 BLC(Borderless Contact)의 형성 방법을 도시한 도면이다.2A to 2C are diagrams illustrating a method for forming borderless contacts according to the prior art.
도 2a에 도시된 바와 같이, 반도체기판(21)상에 스페이서(22a)를 구비한 게이트전극(22)을 형성한 후, 상기 반도체기판(22)에 고농도 불순물 이온주입을 실시하여 소오스/드레인(23)을 형성한다. 이어 상기 구조 전면에 질화막(24), 산화막 (25)을 순차적으로 형성한 다음, 상기 산화막(25)상에 감광막을 도포하고 노광 및 현상으로 패터닝한다. 이어 상기 패터닝된 감광막(도시 생략)을 마스크로 이용하여 상기 산화막(25)을 선택적으로 식각하여 슬로프(Slope)를 갖도록 한다. 이 때, 상기 산화막(25) 식각시 종래와 달리, 1차로 산화막(25)을 식각한 다음, 후속 질화막을 식각하기 위해 산화막(25)의 식각은 질화막(24)상에서 멈추도록 식각선택비를 유지하여야 한다.As shown in FIG. 2A, after the gate electrode 22 having the spacers 22a is formed on the semiconductor substrate 21, a high concentration of impurity ions are implanted into the semiconductor substrate 22 to obtain a source / drain ( 23). Subsequently, the nitride film 24 and the oxide film 25 are sequentially formed on the entire structure, and then a photosensitive film is coated on the oxide film 25 and patterned by exposure and development. Subsequently, the oxide layer 25 is selectively etched using the patterned photoresist (not shown) as a mask to have a slope. At this time, unlike the prior art when etching the oxide film 25, after etching the oxide film 25 first, the etching of the oxide film 25 to maintain the etching selectivity to stop on the nitride film 24 to etch the subsequent nitride film shall.
도 2b에 도시된 바와 같이, 상기 산화막(25)식각후, 감광막패턴을 스트립하고 노출된 질화막(24)을 습식식각하는데, 이 때, 산화막(25) 하부에 배리어메탈 전세정에 의해 오픈될 영역(△x)만큼 안쪽으로 식각되도록 질화막(24)을 습식식각한다.As shown in FIG. 2B, after the oxide layer 25 is etched, the photoresist pattern is stripped and the exposed nitride layer 24 is wet etched. At this time, a region to be opened by barrier metal pre-cleaning under the oxide layer 25. The nitride film 24 is wet etched so as to be etched inward by (Δx).
상기한 바와 같이, 상기 산화막(25)을 식각하여 콘택영역을 오픈할 시, 반도체기판(21)과의 선택비를 향상시키기 위해 슬로프식각(Slope etch)을 실시하고, 질화막(24)을 식각할 시, 산화막(25)하부의 질화막(24)을 배리어메탈 전세정에 의해 오픈될 영역만큼 즉, 50Å∼150Å의 폭만큼 손실시키고, 질화막(24)을 습식식각하므로 게이트전극 및 스페이서의 측면에 잔막을 발생시키지 않는다.As described above, when the oxide layer 25 is etched to open the contact region, a slope etch is performed to improve the selectivity with the semiconductor substrate 21 and the nitride layer 24 is etched. In this case, the nitride film 24 under the oxide film 25 is lost as much as the area to be opened by the barrier metal pre-cleaning, that is, by a width of 50 kPa to 150 kPa, and the nitride film 24 is wet etched so that it remains on the side of the gate electrode and spacer. It does not generate a film.
도 2c에 도시된 바와 같이, 상기 손실된 영역만큼 배리어메탈전세정을 실시하여 손실된 질화막(24)을 채워(26) 수직프로파일을 갖도록 한다. 이와 같이, 배리어메탈 전세정(Pre cleaning)까지 진행된 콘택오픈영역은 종래와 달리 △x/side 만큼 확보하여 콘택면적을 증가시킨다. 또한, 질화막(24)의 습식식각시 잔막이 발생하지 않으므로 잔막에 의한 콘택저항의 증가를 방지한다.As shown in FIG. 2C, barrier metal pre-cleaning is performed as much as the lost region to fill the lost nitride layer 24 to have a vertical profile. As described above, the contact open region, which has undergone the preliminary cleaning of the barrier metal, is secured by Δx / side, and the contact area is increased. In addition, since the residual film does not occur during wet etching of the nitride film 24, an increase in contact resistance caused by the residual film is prevented.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 반도체소자의 콘택 형성 방법은 질화막을 습식식각하여 후속 배리어메탈전세정에 의해 오픈될 영역을 확보하므로써, 질화막의 슬로프 프로파일 및 잔막을 제거하여 콘택오픈 불량을 방지하고 콘택저항을 감소시킬 수 있는 효과가 있다.The method for forming a contact of the semiconductor device of the present invention as described above, by wet etching the nitride film to secure the area to be opened by subsequent barrier metal pre-cleaning, by removing the slope profile and residual film of the nitride film to prevent contact open failure and contact resistance There is an effect that can reduce.
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| KR1020000037442A KR20020003043A (en) | 2000-06-30 | 2000-06-30 | Method for forming contact in semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100491458B1 (en) * | 2001-12-10 | 2005-05-25 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device |
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2000
- 2000-06-30 KR KR1020000037442A patent/KR20020003043A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100491458B1 (en) * | 2001-12-10 | 2005-05-25 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device |
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