KR20020002555A - Al interconection line with TiAlN wetting layer and method for forming the same - Google Patents
Al interconection line with TiAlN wetting layer and method for forming the same Download PDFInfo
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- KR20020002555A KR20020002555A KR1020000036763A KR20000036763A KR20020002555A KR 20020002555 A KR20020002555 A KR 20020002555A KR 1020000036763 A KR1020000036763 A KR 1020000036763A KR 20000036763 A KR20000036763 A KR 20000036763A KR 20020002555 A KR20020002555 A KR 20020002555A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
Description
본 발명은 반도체소자 및 그 제조 방법에 관한 것으로, 더욱 상세하게는 비아홀(via hole)내에 알루미늄(Al) 배선 증착전 적용되는 웨팅층(wetting layer)에관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a wetting layer applied before deposition of aluminum (Al) wiring in a via hole.
잘 알려진 바와 같이, 반도체 소자의 Al 금속 배선 공정시 웨팅층으로 Ti 또는 Ti/TiN을 적용하고 있다. 이러한 웨팅층은 Al 증착시 Al층의 결정성 및 대립 특성을 향상시키게 된다.As is well known, Ti or Ti / TiN is applied as a wetting layer in an Al metal wiring process of a semiconductor device. This wetting layer improves the crystallinity and opposing properties of the Al layer during Al deposition.
그러나 Ti만 웨팅층으로 적용하는 경우 그위에 증착되는 Al의 고온 증착 공정시 Ti가 Al과의 반응에 의한 높은 비저항을 갖는 TiAl3등의 계면 반응물을 형성하여 비아 저항 증가 및 배선 저항 증가의 원인이 된다. 즉, Ti와 Al과의 계면 반응물인 TiAl3형성은 높은 비저항 특성에 의해 Al 배선의 실제 비저항 값을 증가시키고, 계면 반응물 형성에 따른 Al배선의 스트레스 유발에 기인하여 SM(Stress Migration) 및 EM(Electro Migration) 특성을 악화시킨다.However, when only Ti is applied as a wetting layer, Ti forms an interfacial reactant such as TiAl 3 having high specific resistance due to the reaction with Al during the high temperature deposition process of Al deposited thereon, which causes the increase of via resistance and wiring resistance. do. That is, the formation of TiAl 3 , an interfacial reactant between Ti and Al, increases the actual resistivity of the Al interconnection due to its high resistivity, and the stress migration (SM) and EM ( Deteriorates the Electro Migration characteristic.
도1은 금속층간절연막(103)을 식각하여 하부금속배선(101)을 일부 노출시키므로써 비아홀을 형성하고, 그 결과물 전면에 웨팅층으로서 Ti를 증착하고 그 상부에 Al층(105)을 증착한 상태로서, Ti가 Al과의 반응에 의해 높은 비저항을 갖는 TiAl3등의 계면 반응물(107)로 형성되어 있음을 도시하고 있다.FIG. 1 shows a portion of the lower metal wiring 101 by etching the interlayer dielectric film 103 to form a via hole, depositing Ti as a wetting layer on the entire surface of the resultant layer, and depositing an Al layer 105 thereon. As a state, it is shown that Ti is formed of an interfacial reactant 107 such as TiAl 3 having a high specific resistance by reaction with Al.
아와 같이 TiAl3등의 계면 반응물 생성을 이유로 Ti만이 아닌 Ti/TiN을 웨팅층으로 사용하여 TiAl3등의 형성을 억제하는 방법등이 시도되고 있으나, 이경우에는 TiN과 Al과의 격자 상수 차이가 Ti와 Al과의 격자 상수 차이보다 커서 결정성이 다소 감소하며 Ti/TiN 2중 증착에 따른 공정 복잡화 및 제조 단가 증가 등의 단점이 발생된다.As described above, due to the generation of interfacial reactants such as TiAl 3 , a method of suppressing the formation of TiAl 3 and the like by using Ti / TiN as a wetting layer, not only Ti, has been attempted, but in this case, there is a difference in lattice constant between TiN and Al. The crystallinity is slightly reduced due to the lattice constant difference between Ti and Al, and disadvantages such as complicated process and increased manufacturing cost due to Ti / TiN double deposition are caused.
본 발명의 목적은 TiAl3등과 같은 계면 반응물을 생성하지 않으면서 Al의 격자상수와 유사한 격자상수를 같도록 증착하는 것이 가능하여 Al 배선의 결정 특성을 개선하는데 적합한 웨팅층을 갖는 Al 금속 배선 및 그 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide an Al metal interconnection having a wetting layer suitable for improving the crystallinity of Al interconnection by making it possible to deposit a lattice constant similar to Al lattice constant without generating an interfacial reactant such as TiAl 3 and the like. It is to provide a manufacturing method.
도1은 종래기술에 따른 Al 배선 구조를 보여주는 단면도.1 is a cross-sectional view showing an Al wiring structure according to the prior art.
도2a 및 도2b는 본 발명의 바람직한 실시예에 따른 이중 Al 배선 공정을 보여주는 단면도.2A and 2B are cross-sectional views showing a double Al wiring process according to a preferred embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
201 : 제1 Al 배선 203 : 절연막201: first Al wiring 203: insulating film
205 : TiAlN층 207 : 제2 Al배선205 TiAlN layer 207 Second Al wiring
상기 목적을 달성하기 위한 본 발명의 반도체소자는, 제1 Al배선; 상기 제1 Al배선 상에 형성되되 상기 제1 Al배선의 일부가 노출되도록 오픈부를 갖는 절연막; 상기 절연막 및 상기 노출된 제1 Al배선 표면에 형성된 웨팅층으로서의 TiAlN층; 및 상기 TiAlN층 상에 형성되는 제2 Al배선을 포함하는 것을 특징으로 한다.The semiconductor device of the present invention for achieving the above object, the first Al wiring; An insulating layer formed on the first Al wiring and having an open portion to expose a portion of the first Al wiring; A TiAlN layer as a wetting layer formed on the insulating film and the exposed first Al wiring surface; And a second Al wiring formed on the TiAlN layer.
또한 본 발명의 반도체소자 제조방법은, 제1 Al배선 상에 절연막을 증착하고 상기 절연막을 선택식각하여 비아홀을 형성하는 제1단계; 상기 제1단계가 완료된 결과물의 단차를 따라 일정두께로 웨팅층으로서의 TiAlN층을 증착하는 제2단계; 및 상기 TiAlN층 상에 제2 Al배선을 형성하는 제3단계를 포함하여 이루어진 것을 특징으로 한다.In addition, the semiconductor device manufacturing method of the present invention, the first step of depositing an insulating film on the first Al wiring and forming a via hole by selectively etching the insulating film; A second step of depositing a TiAlN layer as a wetting layer at a predetermined thickness along the level difference of the result of the first step; And a third step of forming a second Al wiring on the TiAlN layer.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도2a 및 도2b는 본 발명의 바람직한 실시예에 따른 이중 Al 배선 형성 공정을 보여준다. 먼저 도2a를 참조하여 본 발명에 따른 Al 배선 구조의 반도체소자를 살펴보고 그 제조 공정을 살펴보도록 한다.2A and 2B show a double Al wiring formation process according to a preferred embodiment of the present invention. First, a semiconductor device having an Al wiring structure according to the present invention will be described with reference to FIG. 2A and a manufacturing process thereof.
도2b를 참조하면, 본 발명에 따른 Al 배선 구조는 하부배선인 제1 Al배선(201)과, 상기 제1 Al배선(201) 상에 형성되되 상기 제1 Al배선(201)의 일부가 노출되도록 오픈부를 갖는 절연막(203)과, 상기 절연막(203) 및 상기 노출된 제1 Al배선(201) 표면에 형성된 웨팅층인 TiAlN층(205)과, 상기 TiAlN층 상에 형성되는 상부배선용의 제2 Al배선(207)을 포함하는 구조를 갖는다.Referring to FIG. 2B, the Al wiring structure according to the present invention is formed on the first Al wiring 201, which is a lower wiring, and the first Al wiring 201, but a part of the first Al wiring 201 is exposed. An insulating film 203 having an open portion, a TiAlN layer 205 which is a wetting layer formed on the surface of the insulating film 203 and the exposed first Al wiring 201, and an upper wiring formed on the TiAlN layer. It has a structure including 2 Al wiring 207.
이렇듯, 본 발명은 이중 Al 금속배선 공정시 웨팅층을 TiAlN층(205)으로 형성하는 것에 그 특징을 갖는 것으로서, TiAlN은 증착시 Al의 조성 변화에 의해 증착되는 TiAlN층의 격자 상수를 조정할 수 있어 Al과 격자 상부를 유사하게 일치시키는 것이 가능하다. 따라서 결정 특성과 밀접한 관계를 갖는 Al 배선의 EM(Electro Migration) 특성이 크게 향상 된다. 또한 TiAl3과 같은 계면 반응물의 형성을 억제 또는 방지할 수 있어, 계면 반응물로 인해 발생되는 스트레스 유발에 의한 SM 및 EM 특성 약화의 문제, 그리고 Al 배선의 비저항 값 증가 문제를 방지하는 것이 가능하다.As described above, the present invention is characterized in that the wetting layer is formed of the TiAlN layer 205 during the double Al metal wiring process, and TiAlN can adjust the lattice constant of the TiAlN layer deposited by the change of Al composition during deposition. It is possible to match Al and the lattice top similarly. Therefore, the EM (Electro Migration) characteristics of the Al wiring, which is closely related to the crystal characteristics, are greatly improved. In addition, it is possible to suppress or prevent the formation of interfacial reactants, such as TiAl 3 , it is possible to prevent the problem of weakening the SM and EM characteristics caused by the stress caused by the interfacial reactants, and the problem of increasing the specific resistance value of the Al wiring.
여기서, Al의 격자상수와 실질적으로 유사한 값을 가져야 되는 TiAlN의 각 원자 조성비에 대해 살펴본다. Al의 격자상수는 4.049Å 이고 FCC 구조이다. Ti (002)면이 Al (111) 면과 면간 간격이 거의 같아서 Ti 증착후 Al을 증착하게 되면 Al이 (111) 면으로 우선 성장하게 된다. 그러나 면간 거리 ( Ti(002) 면 면간 거리 = 2.95Å, Al(111) 면 면간 거리 = 2.86Å) 에서 약간의(약 3% ) 미스매치(mistmatch)가 있고, 또한 고온 Al 공정시 Ti/Al 계면에서 높은 저항을 갖는 TiAl3상이 형성된다는 단점이 있다. TiAlN은 TiN 구조에서 Al원자가 Ti과 치환된 구조로 Al 함유 정도에 따라 격자 상수가 바뀌게 되며, 대략 Ti : Al이 1 : 1 근방에서 Al(111) 면간 거리와 거의 같은 2.86Å 정도 가지게 된다. TiAlN 증착 방식에 따라 같은 면간 거리를 갖는 Al 조성이 다를 수 있어 이를 감안하면 Ti : Al의 조성이 2 : 1 ∼ 1 : 2 정도를 갖는 것이 바람직하다.Here, each atomic composition ratio of TiAlN, which should have a value substantially similar to the lattice constant of Al, will be described. The lattice constant of Al is 4.049 Å and has an FCC structure. Since the Ti (002) planes have almost the same spacing between the Al (111) planes and Al is deposited after Ti deposition, Al will first grow to the (111) planes. However, there is a slight (approximately 3%) mismatch in the interplanar distance (Ti (002) interplanar distance = 2.95Å, Al (111) interplanar distance = 2.86Å), and also Ti / Al during high temperature Al process. The disadvantage is that a TiAl 3 phase having a high resistance is formed at the interface. TiAlN is a structure in which the Al atom is substituted with Ti in the TiN structure, and the lattice constant is changed according to the degree of Al containing, and the Ti: Al has about 2.86 같은 which is almost equal to the distance between Al (111) planes in the vicinity of 1: 1. According to the TiAlN deposition method, the Al composition having the same interplanar distance may be different, and in consideration of this, it is preferable that the Ti: Al composition has a ratio of about 2: 1 to about 1: 2.
그러면, 상기한 구조의 배선 및 TiAlN 웨팅층 형성 방법을 설명한다.Next, the wiring and the TiAlN wetting layer forming method of the above structure will be described.
도2a를 참조하면, 소정 공정이 완료된 기판(DRAM의 경우는 트랜지스터, 비트라인 및 커패시터 등이 형성된 구조이다) 상에 제1 Al배선(201)을 형성하고, 절연막(203)을 증착한 다음 콘택영역의 절연막(203)을 식각하여 비아홀을 형성한다. 절연막은 산화막/SOG/산화막이 적층된 구조의 절연막 등 알려진 모든 절연막을 적용하는 것이 가능하다.Referring to FIG. 2A, a first Al wiring 201 is formed on a substrate on which a predetermined process is completed (in the case of DRAM, a structure in which transistors, bit lines, capacitors, etc. are formed), an insulating film 203 is deposited, and then a contact is made. The insulating layer 203 in the region is etched to form via holes. As the insulating film, it is possible to apply all known insulating films such as an insulating film having a structure in which an oxide film / SOG / oxide film is laminated.
이어서 결과물의 단차를 따라 일정두께로 TiAlN층(205)을 증착하는 바, TiAlN층(203)을 증착하는 방법은 여러가지 방법이 있을 수 있다. 그 예로써 한가지 방법은 물리적 기상 증착 방법으로서 Ti-Al 합금 타겟 및 질소 플라즈마를 사용하는 스퍼터링 방법이다. 다른 방법은 화학기상증착(CVD) 방식이다. 스퍼터링 방식 및 화학기상증착 방식 모두에서, TiAlN층 증착전 웨이퍼의 온도를 충분히 냉각하여 TiAlN층 증착이 200℃ 이하의 저온에서 수행되도록 하는 것이 바람직한 바, 이는 Al의 용융점(melting point)이 낮기 때문에 TiAlN층 증착후 바로 Al이 증착되도록 할 수 있기 때문이다. 그리고, 화학기상증착 방식으로 TiAlN 웨팅층을 형성할 때 작은 사이즈의 비아홀에 20 ∼ 200Å 정도의 얇은 웨팅층을 증착하여 주므로써 낮은 메탈 콘택 저항 및 우수한 매립 특성을 확보하는 것이 바람직하다.Subsequently, the TiAlN layer 205 is deposited at a predetermined thickness along the resultant step. There may be various methods for depositing the TiAlN layer 203. As an example, one method is a sputtering method using a Ti-Al alloy target and nitrogen plasma as a physical vapor deposition method. Another method is chemical vapor deposition (CVD). In both the sputtering method and the chemical vapor deposition method, it is preferable to sufficiently cool the wafer temperature before the TiAlN layer deposition so that the TiAlN layer deposition is performed at a low temperature of 200 ° C. or lower, since the AlAl melting point is low. This is because Al can be deposited immediately after layer deposition. In addition, when forming the TiAlN wetting layer by chemical vapor deposition, it is desirable to deposit a thin wetting layer of about 20 to about 200 microseconds in a small via hole to secure a low metal contact resistance and excellent buried characteristics.
이어서, 도2b에 도시된 바와 같이 TiAlN층(205) 상에 제2 Al배선(207)을 형성한다. 제2 Al배선(207)을 형성하는 방법 역시 여러가지 방법이 있을 수 있다. 그예로써 한가지 방법은, Al을 증착한 다음 비아홀 내의 매립을 위해 불활성 기체를 사용하여 웨이퍼에 열을 공급하므로써 웨이퍼를 300 ∼ 500℃ 정도로 승온시켜 열에너지에 의해 Al이 비아홀내로 이동하여 매립되도록 하는 방법이다. 다른 방법은 낮은 온도 증착 및 높은 온도 증착의 이단계 증착을 실시하여 비아홀 내에 Al이 용이하게 매립되도록 하는 방법이다. 이러한 방법들은 Al의 매립 특성을 향상시킬 수 있기 때문이다. 낮은 온도 증착 및 높은 온도 증착은 하나의 챔버에서 연속적으로 수행할 수 있으며, 이 경우 챔버 히터 온도는 400 ∼ 500℃ 정도로 유지하면서, 챔버 장입전에 충분히 웨이퍼 온도를 낮춘후 장입후 빠른 시간내에 Al을 증착하는 낮은 온도 증착을 수행하고, 히터 온도를 전달하기 위해 Ar으로 웨이퍼를 승온시키면서 Al을 증착하는 높은 온도 증착을 수행한다. 한편, 낮은 온도 증착 및 높은 온도 증착을 각각 다른 챔버에서 수행하는 방법을 사용할 수 있으며 이 경우 낮은 온도 증착 챔버는 200℃ 미만으로, 높은 온도 증착 챔버는 400 ∼ 500℃로 유지한다.Next, as shown in FIG. 2B, a second Al wiring 207 is formed on the TiAlN layer 205. The method of forming the second Al wiring 207 may also have various methods. For example, one method is to deposit Al and then heat the wafer to 300 to 500 ° C by supplying heat to the wafer using an inert gas for embedding in the via hole so that Al moves into the via hole by thermal energy and is buried. . Another method is to perform a two-step deposition of low temperature deposition and high temperature deposition so that Al is easily embedded in the via hole. This is because these methods can improve the embedding properties of Al. Low temperature deposition and high temperature deposition can be carried out continuously in one chamber. In this case, while maintaining the chamber heater temperature at about 400 to 500 ° C., the wafer temperature is sufficiently lowered before the chamber charging and Al is deposited quickly after the charging. A low temperature deposition is performed, and a high temperature deposition is performed to deposit Al while raising the wafer to Ar to transfer the heater temperature. On the other hand, a method of performing low temperature deposition and high temperature deposition in different chambers can be used. In this case, the low temperature deposition chamber is maintained at less than 200 ° C., and the high temperature deposition chamber is maintained at 400 to 500 ° C. FIG.
이렇게 Al 증착이 완료되면 반사방지막을 증착한 후 포토리소그래피 공정에 의해 금속배선 공정을 완료한다.When Al deposition is completed, the anti-reflection film is deposited and the metallization process is completed by the photolithography process.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명에 의한 Al 금속배선은 비아(via)나 배선에서 낮은 유효 비저항의 특성 및 신뢰성있는 금속 배선 공정을 가능케하여 차세대 반도체 소자의 특성을 향상시키는 효과가 있다.The Al metal wiring according to the present invention enables a low effective resistivity characteristic and a reliable metal wiring process in vias or wirings, thereby improving the characteristics of next-generation semiconductor devices.
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| CN103022101A (en) * | 2011-09-24 | 2013-04-03 | 台湾积体电路制造股份有限公司 | Metal gate stack having TIALN blocking/wetting layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103022101A (en) * | 2011-09-24 | 2013-04-03 | 台湾积体电路制造股份有限公司 | Metal gate stack having TIALN blocking/wetting layer |
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