KR20080062556A - Method for forming metal plug of semiconductor device - Google Patents

Method for forming metal plug of semiconductor device Download PDF

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KR20080062556A
KR20080062556A KR1020060138497A KR20060138497A KR20080062556A KR 20080062556 A KR20080062556 A KR 20080062556A KR 1020060138497 A KR1020060138497 A KR 1020060138497A KR 20060138497 A KR20060138497 A KR 20060138497A KR 20080062556 A KR20080062556 A KR 20080062556A
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film
tibn
tib2
aluminum
layer
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KR1020060138497A
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KR100914975B1 (en
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정동하
김백만
김수현
이영진
김정태
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for forming a metal wire of a semiconductor device is provided to improve the reflow characteristic of an aluminum layer by using a TiB2/TiBN layer as a barrier layer. A dielectric(102) having a contact hole(H) and a trench(T) is formed on a semiconductor substrate(100). A TiB2 layer(104) is formed on the dielectric including the contact hole and the trench surface. A TiBN layer is formed on the TiB2 layer to form a barrier layer of TiB2/TiBN. Aluminum layers are formed on the barrier layer of TiB2/TiBN to gap-fill the contact hole and the trench. CMP(Chemical Mechanical Polishing) is performed on the aluminum layer and the barrier layer of TiB2/TiBN so that the dielectric is exposed. The TiB2 layer is formed through PVD(Plasma Vapor Deposition). The TiBN layer is formed by a reactive sputtering method. A thickness of the TiBN layer is 5 to 15 % of a thickness of the TiB2 layer.

Description

반도체 소자의 금속배선 형성방법{Method for forming metal plug of semiconductor device}Method for forming metal plug of semiconductor device

도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 공정별 단면도.1A to 1D are cross-sectional views illustrating processes for forming metal wirings of a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100 : 반도체기판 102 : 층간절연막100 semiconductor substrate 102 interlayer insulating film

104 : TiB2막 106 : TiBN막104: TiB2 film 106: TiBN film

108 : 제1알루미늄막 110 : 제2알루미늄막108: first aluminum film 110: second aluminum film

H : 콘택홀 T : 트렌치  H: Contact hole T: Trench

본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 보다 자세하게는, 알루미늄의 리플로우(reflow) 특성을 향상시킬 수 있는 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring of a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device capable of improving reflow characteristics of aluminum.

반도체 소자의 전기적 연결 통로를 제공하는 콘택홀의 매립 플러그 물질을 비롯한 금속배선의 재료로서는 전기 전도도가 매우 우수한 알루미늄(Al)이 주로 이 용되어 왔다. 그런데, 반도체 소자의 집적도 향상에 기인한 소자의 미세화 및 알루미늄의 우수한 반사 특성으로 인해 포토 및 식각공정에서의 마진부족으로 한계에 달해 종래의 반응성이온식각법(Reactive Ion Etching)은 사용할 수 없게 되었다. Aluminum (Al), which has excellent electrical conductivity, has been mainly used as a material for metal wiring, including a buried plug material of a contact hole providing an electrical connection passage of a semiconductor device. However, due to the refinement of the semiconductor device and the excellent reflection characteristics of aluminum due to the integration of semiconductor devices, the margin of the photo and etching processes has reached a limit, and thus, the conventional reactive ion etching method cannot be used.

따라서, 현재에는 이러한 콘택홀 매립의 문제를 해결하기 위해, 알루미늄의 금속배선을 형성하기 위해서는 다마신(Damascene)이라는 새로운 공정 기술이 사용된다. Therefore, in order to solve such problems of contact hole filling, a new process technology called damascene is used to form metal wiring of aluminum.

상기 다마신 공정은 절연막을 식각하여 층간절연막 내에 금속배선용 홀을 먼저 형성한 후, 상기 홀 표면에 층간절연막과 금속막의 확산을 방지하기 위한 베리어막(Diffusion Barrier)으로서 Ti막, TiN막 및 Ti/TiN막을 증착하고 나서, 상기 베리어막 상에 화학기상증착법(chemical vapor deposition)으로 금속막을 증착하며, 이후, 상기 금속막 및 베리어막을 CMP(chemical mechanical deposition)하여 금속배선을 형성한다.In the damascene process, the insulating film is etched to form a metal wiring hole in the interlayer insulating film first, and then a Ti film, a TiN film, and a Ti / Ti as a barrier film to prevent diffusion of the interlayer insulating film and the metal film on the hole surface. After depositing a TiN film, a metal film is deposited on the barrier film by chemical vapor deposition. Then, the metal film and the barrier film are chemically deposited by CMP to form metal wires.

여기서, 상기 Ti막을 베리어막으로 사용하여 금속배선을 형성하면 베리어막 상부에 증착된 알루미늄의 두께 및 Rs(resistance sheet)의 균일특성은 뛰어나게 된다.In this case, when the Ti film is used as the barrier film to form a metal wiring, the thickness of aluminum deposited on the barrier film and the uniformity of Rs (resistance sheet) are excellent.

한편, 상기 다마신 공정을 이용한 알루미늄 금속배선의 형성은, 상기 베리어막 상에 제1알루미늄막을 증착하고, 상기 증착된 제1알루미늄막 상에 고온의 스퍼터(sputter) 방식으로 상기 콘택홀을 완전히 매립하도록 구리가 포함된 제2알루미늄을 매립시킨 다음, 상기 구리가 포함된 제2알루미늄막, 제1알루미늄막 및 베리어막을 CMP하여 형성한다. On the other hand, forming the aluminum metal wiring using the damascene process, depositing a first aluminum film on the barrier film, and completely filling the contact hole on the deposited first aluminum film by a hot sputter method. The second aluminum containing copper is embedded, and then the second aluminum film, the first aluminum film, and the barrier film containing copper are formed by CMP.

그러나, 전술한 바와 같이 알루미늄 금속배선 형성시 베리어막을 Ti, TiN 및 Ti/TiN막으로 사용하게 되면, 트렌치 및 비아의 입구에서 좁아진 선폭 마진으로 인하여 오버행(overhang) 현상이 발생하여 상기 트렌치 또는 비아의 하부를 채우지 못하고 보이드가 형성되는 경우가 발생할 수 있으며, 이와 같은 보이드(void)는 후속의 리플로우(reflow) 공정을 통하여 매립이 되지만, 400℃ 이상의 온도에서는 리플로우 공정을 실시하여도 상기 보이드는 완전히 제거되지 않고 잔류하여 상기 보이드로 인해 반도체 소자의 동작 특성에 오류를 발생시키게 된다.However, when the barrier film is used as the Ti, TiN, and Ti / TiN films when forming the aluminum metal wiring as described above, an overhang phenomenon occurs due to narrowed line width margins at the inlets of the trenches and vias. A void may be formed without filling the lower portion, and such voids may be buried through a subsequent reflow process, but the voids may be formed even when the reflow process is performed at a temperature of 400 ° C. or higher. These voids, rather than being completely removed, cause errors in the operating characteristics of the semiconductor device.

또한, 상기와 같은 TiN 베리어막에서는 알루미늄막의 완전한 [1 1 1]의 배향성을 구현하기 어려워, 알루미늄막이 [1 1 1]의 배향성을 벗어나게 되어 EM에 의하여 소자특성이 저하되게 된다.In addition, in the TiN barrier film as described above, it is difficult to realize the complete [1 1 1] orientation of the aluminum film, so that the aluminum film is out of the [1 1 1] orientation and the device characteristics are degraded by EM.

한편, 점점 좁아지는 선폭에 의해 알류미늄의 비저항에 비하여 상대적으로 비저항이 높은 베리어막의 비저항 때문에 상기 베리어막의 두께를 최소화시키게 되어도, 마진 부족으로 인하여 라인의 저항 증가 요인에 영향을 미치게 된다. On the other hand, even if the thickness of the barrier film is minimized due to the resistivity of the barrier film having a relatively high resistivity compared to the resistivity of the aluminum due to the narrower line width, the increase in line resistance is affected due to the lack of margin.

결과적으로, 상기와 같은 문제점들로 인하여 전체 반도체 소자의 수율이 저하되게 된다.As a result, the yield of the entire semiconductor device is lowered due to the above problems.

따라서, 본 발명은 보이드의 발생을 방지하여 반도체 소자의 동작 특성 오류를 방지할 수 있는 반도체 소자의 금속배선 형성방법을 제공한다.Accordingly, the present invention provides a method for forming metal wirings of a semiconductor device, which can prevent generation of voids and thereby prevent errors in operating characteristics of the semiconductor device.

또한, 본 발명은 EM(ElectroMigration)에 의한 소자특성이 저하되는 것을 방지할 수 있는 반도체 소자의 금속배선 형성방법을 제공한다. In addition, the present invention provides a method for forming metal wirings of a semiconductor device that can prevent the device characteristics from being lowered due to EM (ElectroMigration).

게다가, 본 발명은 전체 반도체 소자의 수율 저하를 방지할 수 있는 반도체 소자의 금속배선 형성방법을 제공한다.In addition, the present invention provides a method for forming metal wirings of a semiconductor device capable of preventing a decrease in yield of the entire semiconductor device.

일 실시예에 있어서, 반도체 소자의 금속배선 형성방법은, 반도체 기판 상에 콘택홀 및 트렌치를 갖는 절연막을 형성하는 단계; 상기 콘택홀 및 트렌치 표면을 포함한 절연막 상에 TiB2막을 형성하는 단계; 상기 TiB2막 상에 TiBN막을 형성해서 TiB2/TiBN의 베리어막을 형성하는 단계; 상기 TiB2/TiBN의 베리어막 상에 콘택홀 및 트렌치를 매립하도록 알루미늄막을 형성하는 단계; 및 상기 절연막이 노출되도록 알루미늄막과 TiB2/TiBN의 베리어막을 CMP하는 단계;를 포함한다.In an embodiment, a method of forming metal wirings of a semiconductor device may include forming an insulating film having contact holes and trenches on a semiconductor substrate; Forming a TiB 2 film on the insulating film including the contact hole and the trench surface; Forming a barrier film of TiB2 / TiBN by forming a TiBN film on the TiB2 film; Forming an aluminum film to fill contact holes and trenches on the barrier film of TiB 2 / TiBN; And CMP the aluminum film and the barrier film of TiB2 / TiBN to expose the insulating film.

상기 TiB2막은, PVD 방식으로 형성한다.The TiB 2 film is formed by the PVD method.

상기 TiBN막은 상기 TiB2막의 표면을 NH3 및 N2 중에서 어느 하나의 분위기로 질화 처리하여 형성한다.The TiBN film is formed by nitriding the surface of the TiB2 film with any one of NH3 and N2.

상기 질화 처리는 열처리 및 플라즈마 중에서 어느 하나의 방식으로 수행한다.The nitriding treatment is performed in any one of heat treatment and plasma.

상기 TiBN막은 반응성 스퍼터링 방식으로 형성한다.The TiBN film is formed by a reactive sputtering method.

상기 TiBN막은 상기 TiB2막 두께의 5∼15%의 두께를 갖도록 형성한다.The TiBN film is formed to have a thickness of 5 to 15% of the thickness of the TiB2 film.

상기 알루미늄막을 형성하는 단계는, 상기 TiB2/TiBN의 베리어막 상에 MOCVD 공정에 따라 제1알루미늄막을 증착하는 단계; 상기 제1알루미늄막을 열처리하는 단계; 및 상기 열처리된 제1알루미늄막 상에 콘택홀 및 트렌치를 완전 매립하도록 스퍼터링 공정에 따라 제2알루미늄막을 증착하는 단계;로 구성된다.The forming of the aluminum film may include depositing a first aluminum film on a barrier film of TiB 2 / TiBN by a MOCVD process; Heat-treating the first aluminum film; And depositing a second aluminum film according to a sputtering process to completely fill the contact hole and the trench on the heat treated first aluminum film.

상기 제1알루미늄막을 열처리하는 단계는, 400∼530℃의 온도에서 수행한다.The heat treatment of the first aluminum film is performed at a temperature of 400 to 530 ° C.

상기 제2알루미늄막은, 구리를 포함하도록 형성한다.The second aluminum film is formed to contain copper.

상기 제2알루미늄막은, 350∼560℃의 온도에서 형성한다.The second aluminum film is formed at a temperature of 350 to 560 ° C.

(실시예)(Example)

이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예을 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명은 알루미늄 금속 배선 형성시 베리어막으로 TiB2/TiBN막을 사용한다.In the present invention, a TiB2 / TiBN film is used as a barrier film in forming an aluminum metal wiring.

즉, 층간절연막 상에 TiB2막을 형성하고 나서, 상기 TiB2막 상에 TiBN막을 형성시켜 상기와 같은 TiB2/TiBN막이 형성되도록 한다.That is, after the TiB2 film is formed on the interlayer insulating film, the TiBN film is formed on the TiB2 film to form the TiB2 / TiBN film as described above.

이렇게 하면, 상기 TiB2막 상에서 알루미늄의 리플로우 특성이 향상되어, 알루미늄막 매립시 보이드(void)의 발생을 방지할 수 있어, 그에 따른 반도체 소자의 동작 특성에서의 오류 발생을 방지할 수 있다.In this way, the reflow characteristic of aluminum is improved on the TiB2 film, thereby preventing the generation of voids when the aluminum film is embedded, thereby preventing an error in the operating characteristics of the semiconductor device.

또한, TiB2/TiBN막과 같이 베리어막에 질소가 함유하게 되면, TiB2 구조가 비정질 형태로 존재하여 그에 따라 하부층의 영향이 미약해져 알루미늄막의 [1 1 1]의 배향성을 강화시킬 수 있음에 따라, 알루미늄 금속배선의 신뢰성을 향상시켜 EM(ElectroMigration)에 의한 소자특성의 저하를 방지할 수 있다.In addition, when nitrogen is contained in the barrier film, such as the TiB2 / TiBN film, the TiB2 structure is present in an amorphous form, and accordingly, the influence of the lower layer is weakened, thereby enhancing the orientation of [1 1 1] of the aluminum film. It is possible to prevent the deterioration of device characteristics due to EM (ElectroMigration) by improving the reliability of the aluminum metal wiring.

게다가, 베리어막으로 비저항이 낮은 TiB2막을 사용함으로써, 베리어막의 높은 비저항에 의한 저항 증가 효과를 감소시킬 수 있다. In addition, by using the TiB2 film having a low specific resistance as the barrier film, the effect of increasing the resistance due to the high specific resistance of the barrier film can be reduced.

자세하게, 도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 금속 배선을 형성하기 위한 공정별 단면도로서, 이를 설명하면 다음과 같다.1A to 1D are cross-sectional views of processes for forming metal wirings of a semiconductor device according to an exemplary embodiment of the present invention.

도 1a를 참조하면, 트랜지스터, 비트라인 및 캐패시터 등의 하부구조물이 형성된 반도체기판(100) 상에 층간절연막(102)을 형성하고, 상기 층간절연막(102)을 싱글다마신 또는 듀얼다마신 공정으로 식각하여 후속의 금속배선 및 플러그 형성을 위한 패턴을 형성한다. 여기서, 상기 패턴은 콘택홀(H), 트렌치(T) 및 콘택홀(H)을 포함한 트렌치(T)로 형성하도록 한다.Referring to FIG. 1A, an interlayer insulating film 102 is formed on a semiconductor substrate 100 on which substructures such as transistors, bit lines, and capacitors are formed, and the interlayer insulating film 102 is subjected to a single damascene or dual damascene process. Etching forms a pattern for subsequent metallization and plug formation. The pattern may be formed as a trench T including a contact hole H, a trench T, and a contact hole H.

도 1b를 참조하면, 상기 콘택홀(H) 및 트렌치(T) 표면을 포함하는 층간절연막(102)상에 PVD(plasma vapor deposition) 방식으로 TiB2막(104)을 형성한다. 이때, 접합을 이루고 있는 하부층이 폴리-실리콘일 경우 먼저 Ti를 증착하고 그 다음에 Ti 실리사이드를 형성한 후에 TiB2막을 형성하며, 한편, 하부층이 상기와 같은 폴리-실리콘이 아니라 금속일 경우에는 바로 TiB2막을 형성하도록 한다.Referring to FIG. 1B, the TiB 2 film 104 is formed on the interlayer insulating film 102 including the contact hole H and the trench T surface by plasma vapor deposition (PVD). In this case, when the lower layer forming the junction is poly-silicon, Ti is deposited first and then Ti silicide is formed, followed by the formation of the TiB 2 film. Meanwhile, when the lower layer is a metal instead of poly-silicon, the TiB 2 is immediately Make a film.

그런 다음, 상기 TiB2막(104) 상에 TiBN막(106)을 형성한다. Then, a TiBN film 106 is formed on the TiB2 film 104.

여기서, 바람직하게는 상기 TiBN막(106)의 형성은 NH3 도는 N2의 분위기에서 어닐링 방식 또는 플라즈마 방식으로 질화처리하여 형성하도록 한다. Here, the TiBN film 106 is preferably formed by nitriding by annealing or plasma in an atmosphere of NH 3 or N 2.

또는, 상기 TiB2막(106) 상에 반응성 스퍼터링 방식으로 피를로우 특성에는 영향을 미치지 않을 정도로 상기 TiB2막(104)보다 약 1/10 정도의 두께를 갖도록 TiBN막을 형성하도록 한다. Alternatively, the TiBN film may be formed on the TiB2 film 106 to have a thickness about 1/10 of the TiB2 film 104 to the extent that it does not affect the Pirlow characteristics by the reactive sputtering method.

도 1c를 참조하면, 상기 TiB2/TiBN막(104, 106) 상에 MOCVD 방식을 이용하여 제1알루미늄막(108)을 증착한다.Referring to FIG. 1C, a first aluminum film 108 is deposited on the TiB 2 / TiBN films 104 and 106 by MOCVD.

이때, 상기 제1알루미늄막(108)의 웨팅(wetting) 특성 향상 및 상기 콘택 홀(H) 및 트렌치(T)의 패턴 내부로 제1알루미늄막(108)이 보이드 없이 매립되도록 상기 제1알루미늄막(108)이 증착된 콘택홀(H) 및 트렌치(T)를 400∼530℃ 정도의 온도로 가열하도록 한다.In this case, the first aluminum film is improved to improve the wetting property of the first aluminum film 108 and to fill the first aluminum film 108 without voids into the pattern of the contact hole H and the trench T. The contact hole H and the trench T on which the 108 is deposited are heated to a temperature of about 400 to about 530 ° C.

그런다음, 상기 제1알루미늄막(108) 상에 콘택홀(H) 및 트렌치(T)를 매립하도록 구리가 포함된 제2알루미늄막(110)을 스퍼터링(sputtering) 방법으로 증착한다. 여기서, 상기 제2알루미늄막(110)의 증착은 350∼560℃ 정도의 온도에서 수행하도록 한다.Thereafter, a second aluminum film 110 including copper is deposited on the first aluminum film 108 by sputtering to fill the contact hole H and the trench T. Here, the deposition of the second aluminum film 110 is performed at a temperature of about 350 to 560 ℃.

도 1d를 참조하면, 상기 제2알루미늄막(110), 제1알루미늄막(108), TiBN막(106) 및 TiB2막(104)을 상기 층간절연막(102)이 노출될때가지 CMP하여, 본 발명의 실시예에 따른 반도체 소자의 금속배선을 완성한다.Referring to FIG. 1D, the second aluminum film 110, the first aluminum film 108, the TiBN film 106, and the TiB2 film 104 are CMP until the interlayer insulating film 102 is exposed, thereby providing the present invention. The metal wiring of the semiconductor device according to the embodiment of the present invention is completed.

이 경우, 본 발명은 알루미늄 금속배선 형성시, 베리어막으로 TiB2/TiBN막을 사용함으로써, 알루미늄막의 리플로우 특성이 향상되어, 알루미늄막 매립시 보이드(void)의 발생을 방지할 수 있어, 그에 따른 반도체 소자의 동작 특성에의 오류 발생을 방지할 수 있다.In this case, the present invention improves the reflow characteristics of the aluminum film by using the TiB2 / TiBN film as the barrier film when forming the aluminum metal wiring, thereby preventing the generation of voids when the aluminum film is buried, and thus the semiconductor The occurrence of an error in the operating characteristics of the device can be prevented.

또한, TiB2/TiBN막과 같이 베리어막에 질소를 함유시켜, TiB2 구조가 비정질 형태로 존재하여 그에 따라 하부층의 영향이 미약해져 알루미늄막의 [1 1 1]의 배향성을 강화시킬 수 있음에 따라, 알루미늄 금속배선의 신뢰성을 향상시켜 EM(ElectroMigration)에 의한 소자특성의 저하를 방지할 수 있다.In addition, by containing nitrogen in the barrier film as in the TiB2 / TiBN film, the TiB2 structure is present in an amorphous form, and thus the influence of the lower layer is weakened, thereby enhancing the orientation of [1 1 1] of the aluminum film. It is possible to prevent the deterioration of device characteristics due to EM (ElectroMigration) by improving the reliability of the metal wiring.

게다가, 베리어막으로 비저항이 낮은 TiB2막을 사용함으로써, 베리어막의 높은 비저항에 의한 저항 증가 효과를 감소시킬 수 있다. In addition, by using the TiB2 film having a low specific resistance as the barrier film, the effect of increasing the resistance due to the high specific resistance of the barrier film can be reduced.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

이상에서와 같이 본 발명은, 베리어막으로 TiB2/TiBN막을 사용함으로써, 알루미늄막의 리플로우 특성을 향상시켜 알루미늄막 매립시 보이드(void)의 발생을 방지하여, 그에 따른 반도체 소자의 동작 특성에의 오류 발생을 방지할 수 있다.As described above, the present invention improves the reflow characteristics of the aluminum film by preventing the generation of voids when the aluminum film is embedded by using the TiB2 / TiBN film as the barrier film, thereby resulting in an error in the operation characteristics of the semiconductor device. It can prevent occurrence.

또한, 본 발명은 알루미늄막의 [1 1 1]의 배향성이 강화됨에 따라, 알루미늄 금속배선의 신뢰성을 향상시켜 EM(ElectroMigration)에 의한 소자특성의 저하를 방지할 수 있다.In addition, according to the present invention, as the orientation of the [1 1 1] of the aluminum film is enhanced, the reliability of the aluminum metal wiring can be improved to prevent deterioration of device characteristics due to EM (ElectroMigration).

게다가, 본 발명은 비저항이 낮은 TiB2막 베리어막으로 사용함으로써, 베리어막의 높은 비저항에 의한 저항 증가 효과를 감소시킬 수 있다. In addition, the present invention can reduce the resistance increase effect due to the high specific resistance of the barrier film by using it as the TiB2 film barrier film having a low specific resistance.

따라서, 본 발명은 소자 전체의 수율을 향상시킬 수 있다.Therefore, this invention can improve the yield of the whole element.

Claims (10)

반도체 기판 상에 콘택홀 및 트렌치를 갖는 절연막을 형성하는 단계;Forming an insulating film having a contact hole and a trench on the semiconductor substrate; 상기 콘택홀 및 트렌치 표면을 포함한 절연막 상에 TiB2막을 형성하는 단계;Forming a TiB 2 film on the insulating film including the contact hole and the trench surface; 상기 TiB2막 상에 TiBN막을 형성해서 TiB2/TiBN의 베리어막을 형성하는 단계;Forming a barrier film of TiB2 / TiBN by forming a TiBN film on the TiB2 film; 상기 TiB2/TiBN의 베리어막 상에 콘택홀 및 트렌치를 매립하도록 알루미늄막을 형성하는 단계; 및Forming an aluminum film to fill contact holes and trenches on the barrier film of TiB 2 / TiBN; And 상기 절연막이 노출되도록 알루미늄막과 TiB2/TiBN의 베리어막을 CMP하는 단계;CMPing the aluminum film and the barrier film of TiB2 / TiBN to expose the insulating film; 를 포함하는 반도체 소자의 금속배선 형성방법.Metal wiring forming method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 TiB2막은, PVD 방식으로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The TiB 2 film is formed by the PVD method. 제 1 항에 있어서,The method of claim 1, 상기 TiBN막은 상기 TiB2막의 표면을 NH3 및 N2 중에서 어느 하나의 분위기로 질화 처리하여 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.And wherein the TiBN film is formed by nitriding the surface of the TiB2 film with any one of NH3 and N2 atmospheres. 제 3 항에 있어서,The method of claim 3, wherein 상기 질화 처리는 열처리 및 플라즈마 중에서 어느 하나의 방식으로 수행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The nitriding treatment is performed by any one of heat treatment and plasma. 제 1 항에 있어서,The method of claim 1, 상기 TiBN막은 반응성 스퍼터링 방식으로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The TiBN film is a metal wiring forming method of a semiconductor device, characterized in that formed by a reactive sputtering method. 제 1 항에 있어서,The method of claim 1, 상기 TiBN막은 상기 TiB2막 두께의 5∼15%의 두께를 갖도록 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.And the TiBN film is formed to have a thickness of 5 to 15% of the thickness of the TiB2 film. 제 1 항에 있어서,The method of claim 1, 상기 알루미늄막을 형성하는 단계는,Forming the aluminum film, 상기 TiB2/TiBN의 베리어막 상에 MOCVD 공정에 따라 제1알루미늄막을 증착하는 단계; 상기 제1알루미늄막을 열처리하는 단계; 및 상기 열처리된 제1알루미늄막 상에 콘택홀 및 트렌치를 완전 매립하도록 스퍼터링 공정에 따라 제2알루미늄막을 증착하는 단계;Depositing a first aluminum film on the barrier film of TiB 2 / TiBN by a MOCVD process; Heat-treating the first aluminum film; And depositing a second aluminum film according to a sputtering process to completely fill contact holes and trenches on the heat treated first aluminum film. 로 구성되는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.Metal wiring forming method of a semiconductor device, characterized in that consisting of. 제 7 항에 있어서,The method of claim 7, wherein 상기 제1알루미늄막을 열처리하는 단계는, 400∼530℃의 온도에서 수행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The heat treatment of the first aluminum film, the metal wiring forming method of a semiconductor device, characterized in that performed at a temperature of 400 ~ 530 ℃. 제 7 항에 있어서,The method of claim 7, wherein 상기 제2알루미늄막은, 구리를 포함하도록 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.And the second aluminum film is formed to contain copper. 제 7 항에 있어서,The method of claim 7, wherein 상기 제2알루미늄막은, 350∼560℃의 온도에서 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법. The second aluminum film is formed at a temperature of 350 to 560 占 폚.
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KR101029107B1 (en) * 2008-08-29 2011-04-13 주식회사 하이닉스반도체 Metal wiring of semiconductor device and method for forming the same
US10530030B2 (en) 2015-06-24 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having first and second transmission lines with a high-K dielectric material disposed between the first and second transmission lines

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* Cited by examiner, † Cited by third party
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JPH05267220A (en) * 1992-03-19 1993-10-15 Sony Corp Method of forming sealing layer and metal plug in semiconductor device
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KR100327595B1 (en) * 1999-12-30 2002-03-15 박종섭 Semiconductor device with metal line and method for forming thereof
KR100424714B1 (en) * 2001-06-28 2004-03-27 주식회사 하이닉스반도체 Method for fabricating copper interconnect in semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
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KR101029107B1 (en) * 2008-08-29 2011-04-13 주식회사 하이닉스반도체 Metal wiring of semiconductor device and method for forming the same
US8053895B2 (en) 2008-08-29 2011-11-08 Hynix Semiconductor Inc. Metal line of semiconductor device having a multilayer molybdenum diffusion barrier and method for forming the same
US10530030B2 (en) 2015-06-24 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having first and second transmission lines with a high-K dielectric material disposed between the first and second transmission lines
US11258151B2 (en) 2015-06-24 2022-02-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a high-k dielectric material disposed beyween first and second transmission lines and a dielectric directly contacting the high-k dielectric material
US11664566B2 (en) 2015-06-24 2023-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method, where a dielectric material directly contacts a high-k dielectric material and first and second transmission lines

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