KR200160933Y1 - Lead frame of semiconductor package type - Google Patents

Lead frame of semiconductor package type Download PDF

Info

Publication number
KR200160933Y1
KR200160933Y1 KR2019970010650U KR19970010650U KR200160933Y1 KR 200160933 Y1 KR200160933 Y1 KR 200160933Y1 KR 2019970010650 U KR2019970010650 U KR 2019970010650U KR 19970010650 U KR19970010650 U KR 19970010650U KR 200160933 Y1 KR200160933 Y1 KR 200160933Y1
Authority
KR
South Korea
Prior art keywords
tape
tie bar
mounting plate
lead frame
semiconductor package
Prior art date
Application number
KR2019970010650U
Other languages
Korean (ko)
Other versions
KR19980066267U (en
Inventor
김동영
Original Assignee
김규현
아남반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김규현, 아남반도체주식회사 filed Critical 김규현
Priority to KR2019970010650U priority Critical patent/KR200160933Y1/en
Publication of KR19980066267U publication Critical patent/KR19980066267U/en
Application granted granted Critical
Publication of KR200160933Y1 publication Critical patent/KR200160933Y1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 고안은 반도체패키지용 리드프레임에 관한 것이다.The present invention relates to a lead frame for a semiconductor package.

종래에는 리드프레임(LF)의 인너리드(L) 상에 테이프(TP)를 접착함에 있어서, 사각형태의 띠상으로 테이프(TP)를 구성하여 인너리드(L) 및 타이바(TB)를 지지고정시켜 인너리드(L)와 타이바(TB)의 변형 방지가 이루어지도록 해 왔으나, 네 모퉁이에 설치되는 타이바(TB)를 테이프의 사각 에지부분이 그것도 댐바부위에 치우쳐 잡아 주게 되는 관계로 그 지지력이 미약하여 성형시 탑재판(T)의 유동 및 위치변형으로 인한 반도체패키지의 제조불량을 야기시기는 일 요인이 되어 왔었다.Conventionally, in bonding the tape TP on the inner lead L of the lead frame LF, the tape TP is formed in the shape of a rectangular band to support the inner lead L and the tie bar TB. In order to prevent deformation of inner lead (L) and tie bar (TB), the tie bar (TB) installed at the four corners of the tape has the square edge part of the taper, which also biases the dam bar area. This weakness has been a factor that causes the manufacturing failure of the semiconductor package due to the flow and position deformation of the mounting plate (T) during molding.

본 고안에서는 리드프레임의 인너리드들 위에 각 인너리드를 잡아 주는 테이프(TP)를 일체적으로 연결시켜 부착하되, 탑재판(T)을 잡아 주는 타이바(TB)의 지지력을 보강해 주기 위하여, 종래 사각의 띠상으로 부착되는 테이프(TP)의 형상을 팔각형태를 구성하여 인너리드상에 부착시킨 것으로, 팔각형태의 테이프(TP) 구성을 통하여 네 모퉁이에 위치한 타이바(TB)를 보다 견고하게 지지해 줄 수 있도록 함으로써 반도체칩이 탑재되는 탑재판의 유동 및 변형으로 인한 불량을 사전에 예방할 수 있도록 한 것이다.In the present invention, in order to reinforce the bearing capacity of the tie bar (TB) for holding the mounting plate (T) attached to the inner frame of the lead frame by connecting the tape (TP) for holding each inner lead integrally, The shape of the tape (TP) attached in the form of a square band is attached to the inner lead by forming the octagonal shape, and the tie bar (TB) at four corners is more firmly formed through the octagonal tape (TP) configuration. By supporting it, defects caused by flow and deformation of the mounting plate on which the semiconductor chip is mounted can be prevented in advance.

[색인어][Index]

반도체패키지의 리드프레임Lead frame of semiconductor package

Description

반도체패키지용 리드프레임(LEAD FRAME FOR SEMICONDUCTOR PACKAGES)LEAD FRAME FOR SEMICONDUCTOR PACKAGES

본 고안은 반도체패키지용 리드프레임에 대한 것으로서, 특히 반도체패키지의 리드프레임에 형성된 다수의 인너리드와 타이바의 중앙부분에 테이프를 부착시켜 타이바의 지지견고성을 보강시켜 성형시 탑재판의 유동 및 위치변형을 방지할 수 있게 한 반도체패키지용 리드프레임에 관한 것이다.The present invention relates to a lead frame for a semiconductor package, and in particular, a plurality of inner leads and tie bars formed on the lead frame of the semiconductor package are attached to the center portion of the tie bar, thereby reinforcing the support rigidity of the tie bar, and The present invention relates to a lead frame for a semiconductor package capable of preventing positional deformation.

일반적으로 반도체패키지의 리드프레임은 금속재로 구성되어 반도체칩이 부착 탑재되는 탑재판(T)이 구비되고, 이 탑재판(T)의 사각 외부에는 소정간격을 두고 다수의 인너리드(L)가 배열 형성되며, 그리고 상기 탑재판(T)의 네 모퉁이에는 동 탑재판(T)을 지지해 주는 타이바(TB)가 연결되는 구성을 하고 있다.In general, a lead frame of a semiconductor package includes a mounting plate (T) on which a semiconductor chip is attached and mounted with a metal material, and a plurality of inner leads (L) are arranged at a predetermined interval outside the square of the mounting plate (T). It is formed, and the four corners of the mounting plate (T) is configured to connect the tie bar (TB) for supporting the mounting plate (T).

이러한 리드프레임은 탑재판에 반도체칩이 부착되고, 반도체칩과 각 인너리드 사이에 와이어가 연결되며, 인너리드 중 일부를 포함하는 영역과 와이어 및 반도체칩의 외부에는 합성수지 재질의 패키지가 구성되어 완제품 상태의 반도체패키지를 형성하게 된다.The lead frame has a semiconductor chip attached to a mounting plate, a wire is connected between the semiconductor chip and each inner lead, and a package made of a synthetic resin material is formed on the outer part of the inner lead and the wire and the semiconductor chip. The semiconductor package in a state is formed.

이와 같이 종래 반도체패키지를 구성하는 리드프레임(LF)은 제4도에서 보는 바와 같이 리드프레임(LF)의 중앙에 위치하는 사각탑재판(T)의 네 모퉁이에 리드프레임(LF)과 연결되는 타이바(TB)가 구성되고, 그리고 탑재판(T) 외부에는 소정간격을 두고 다수의 인너리드(L)가 배열 형성되는 구성을 하고 있음을 볼 수 있다.As shown in FIG. 4, the lead frame LF constituting the semiconductor package is a tie connected to the lead frame LF at four corners of the square mounting plate T positioned at the center of the lead frame LF. It can be seen that the bar TB is configured, and a plurality of inner leads L are arranged at a predetermined interval outside the mounting plate T.

상기한 리드프레임(LF)에 형성된 인너리드(L)와 타이바(TB) 상에는 사각형태의 띠상의 테이프(TP)가 부착되어 인너리드(L)와 타이바(TB)를 잡아줌으로써의 성형시 이들의 변형을 막아주게 되는데, 이때 테이프(TP)는 탑재판(T)과 근접 배열되는 인너리드(L)의 선단(끝단)에서 댐바(DB) 쪽으로 편중된 위치에 부착되어 인너리드(L)와 타이바(TB)를 지지하는 역할을 수행한다.When forming the inner lead (L) and the tie bar (TB) formed on the lead frame (LF) is attached to the tape (TP) of the rectangular shape by holding the inner lead (L) and tie bar (TB) The tape TP is prevented from being deformed. At this time, the tape TP is attached to a position biased toward the dam bar DB at the end (end) of the inner lead L arranged in close proximity to the mounting plate T and the inner lead L. And support the tie bar (TB).

그러나, 이러한 테이프의 부착 구조는 댐바(DB) 쪽으로 상당히 편중된 위치에서 인너리드(L)와 타이바(TB)를 잡아주는 구성임은 물론 더구나 사각형태의 테이프(TP) 네 모퉁이가 타이바(TB)를 접착하고 있기 때문에, 타이바(TB)의 지지력이 미약하고 또한 테이프(TB)의 접착 위치에서 탑재판(T)까지의 인너리드(L) 및 타이바(TB)의 길이가 비교적 길어 탑재판(T)을 지지하는 견고성이 매우 취약하였다.However, the tape attachment structure is such that the inner lead (L) and the tie bar (TB) are held in a highly biased position toward the dam bar (DB). TB) is bonded, so that the support force of the tie bar TB is weak, and the length of the inner lead L and tie bar TB from the bonding position of the tape TB to the mounting plate T is relatively long. The firmness supporting the mounting plate T was very weak.

따라서, 제5도의 예에서와 같이 탑재판(T)에 반도체칩(C)을 부착 탑재시킨 후 반도체칩(C)과 각 인너리드(L)에 와이어(W)를 연결 본딩시킨 다음 패기지 성형공정에서 몰드금형(MD)을 이용하여 액상의 컴파운드재를 충진 공급하여 패기지(P) 성형시킬 때 충진공급압력과 컴파운드재의 충진 흐름에 따라 타이바(TB)가 쉽게 변형되게 되고, 그에 따라 탑재판(T)의 유동 및 위치변형으로 반도체칩(C)이 상부 또는 하부로 크게 변위되면서 제품의 손상과 불량을 유발시기는 일 원인이 되어 왔었다.Therefore, as shown in the example of FIG. 5, the semiconductor chip C is attached to the mounting plate T, and then the wire W is connected and bonded to the semiconductor chip C and each inner lead L, and then packaged. In the process, when the mold compound (MD) is filled and supplied with a liquid compound material to form a package (P), the tie bar (TB) is easily deformed according to the filling supply pressure and the filling flow of the compound material. As the semiconductor chip C is greatly displaced upward or downward due to the flow and position deformation of the plate T, it has been a cause for causing damage and defects of the product.

본 고안은 상기와 같은 종래의 문제점을 해결하기 위하여 고안한 것으로서, 반도체패키지를 구성하는 리드프레임에 형성된 다수의 인너리드와 타이바의 중앙부분에 팔각형태의 띠상의 테이프를 접착시켜 인너리드 간의 지지견고성을 높임과 동시에 특히 탑재판을 지지하고 있는 타이바의 지지견고성을 제고시켜 패키지성형시 탑재판과 반도체칩의 유동 및 위치변형을 방지토록 하는 것을 목적으로 한다.The present invention has been devised to solve the above-mentioned problems, and the support between the inner leads by adhering an octagonal band-shaped tape to the center portion of the tie bars and the plurality of inner leads formed in the lead frame constituting the semiconductor package The purpose of the present invention is to enhance the robustness and to improve the support robustness of the tie bar supporting the mounting plate, in particular, to prevent the flow and position deformation of the mounting plate and the semiconductor chip during package molding.

제1도는 본 고안의 적용상태 단면구성도.1 is a cross-sectional view of the application state of the present invention.

제2도는 본 고안의 리드프레임 평면구성도.2 is a plan view of the lead frame of the present invention.

제3도는 본 고안의 작용상태도.3 is a working state of the present invention.

제4도는 종래의 리드프레임 평면도.4 is a plan view of a conventional leadframe.

제5도는 종래의 작용상태도5 is a conventional working state diagram

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 반도체패키지 LF : 리드프레임10: semiconductor package LF: lead frame

T : 탑재판 TB : 타이바T: Mounting Plate TB: Tie Bar

TP : 테이프 L : 인너리드TP: Tape L: Inner Lead

이하, 본 고안의 구성을 상세히 설명하면 다음과 같다.Hereinafter, the configuration of the present invention in detail as follows.

반도체패키지(10)의 리드프레임(LF) 내부 중앙에 탑재판(T)이 형성되며, 이 탑재판(T)의 각 사각모퉁이에 타이바(TB)가 연결되고 그리고 탑재판(T)의 외부에는 다수의 인너리드(L)가 배열 형성되며, 상기 인너리드(L) 및 터이바(TB) 위에 이들을 지지하는 테이프(TP)를 일체적으로 부착한 것에 있어서, 상기 테이프(TP)가 팔각형태의 띠상으로 구성되어 인너리드(L) 또는 타이바(TB)의 전체길이 중 중앙부분에 해당하는 위치에 부착됨과 동시에 다수의 인너리드 중 각 모퉁이 부분에 위치한 인너리드와 타이바를 팔각형태의 띠상으로 구성된 테이프(TP)의 한 변으로 접착되도록 하여 타이바(TB)와 인너리드(L)의 지지견고성을 높일 수 있도록 한 것이다.The mounting plate T is formed in the center of the lead frame LF of the semiconductor package 10, and the tie bars TB are connected to each square corner of the mounting plate T, and the outside of the mounting plate T is provided. A plurality of inner leads (L) are formed therein, and the tape (TP) is octagonal in that the tape (TP) supporting them is integrally formed on the inner lead (L) and the tub (TB). It consists of a band shape of which is attached to the position corresponding to the center of the entire length of the inner lead (L) or tie bar (TB), and at the same time, the inner lead and tie bar located at each corner of the plurality of inner leads are formed in the shape of an octagonal band. It is to be bonded to one side of the configured tape (TP) to increase the support strength of the tie bar (TB) and the inner lead (L).

이와 같이 구성된 본 고안을 도면에 도시된 일 실시예에 의거 상세히 설명한다.The present invention configured as described above will be described in detail based on the embodiment shown in the drawings.

제1도는 본 고안의 단면구성도이다. 리드프레임(LF)의 중앙에는 탑재판(T)이 구비되며, 이 탑재판(T)의 상면에는 반도체칩(C)이 탑재되고, 사각의 탑재판(T) 외부에는 다수의 인너리드(L)가 배열 형성되며, 탑재판(T)의 사각 모퉁이에는 타이바(TB)가 연결되어 탑재판(T)을 지지해 주는 역할 하게 된다. 그리고 인너리드(L)의 일부를 포함하는 패키지성형영역(PA)에는 패기지(P)가 형성된다.1 is a cross-sectional view of the present invention. A mounting plate T is provided at the center of the lead frame LF, and a semiconductor chip C is mounted on the upper surface of the mounting plate T, and a plurality of inner leads L are disposed outside the rectangular mounting plate T. ) Is formed in an array, the tie bar (TB) is connected to the square corner of the mounting plate (T) serves to support the mounting plate (T). In addition, a package P is formed in the package forming area PA including a part of the inner lead L. FIG.

본 고안을 구성하는 리드프레임(LF)은 제2도에서 보는 바와 같이 중앙에 위치한 탑재판(T)의 네 모퉁이에 타이바(TB)가 길게 연결되어 있고, 타이바(TB)를 제외한 탑재판(T)의 외부에는 소정간격을 두고 다수의 인너리드(L)들이 배열 형성되어있으며, 그리고 각 인너리드(L)와 타이바(TB)의 상면 중앙부분으로 팔각형태의 띠상의 테이프(TP)가 부착되는 구성을 하고 있다.As shown in FIG. 2, the lead frame LF of the present invention has a tie bar (TB) connected to four corners of the mounting plate (T) located at the center thereof, and the mounting plate except for the tie bar (TB). A plurality of inner leads (L) are arranged outside the (T) at predetermined intervals, and the octagonal tape (TP) is formed in the center of the upper surface of each inner lead (L) and tie bar (TB). Is attached.

상기 팔각형태의 테이프(TP)는 타이바(TB) 및 각 인너리드(L)의 전체 길이중 중앙부분에 해당하는 1/3 ∼ 1/2 영역에 부착된다.The octagonal tape TP is attached to a region of 1/3 to 1/2 corresponding to the center portion of the entire length of the tie bar TB and each inner lead L.

그리고, 다수의 인너리드 중 각 모퉁이 부분에 위치한 인너리드(L)와 타이바(TB)를 팔각형태의 띠상으로 구성된 테이프(TP)의 한 변(에지부분이 아님)으로 접착토록 함으로써 타이바(TB)이 지지견고성을 가일층 높일 수 있게 되는 것이다.In addition, the inner bars (L) and tie bars (TB) located at each corner of the plurality of inner leads are bonded to one side (not the edge part) of the tape TP composed of octagonal bands. TB) will be able to further increase support robustness.

따라서, 팔각형태로 구성된 테이프(TP)가 최대한 탑재판(T)과 가까이 위치하도록 부착되기 때문에 타이바(TB)를 보다 견고히 기지할 수 있는 것이며, 동시에 각 인너리드(L)도 견고히 지지될 수가 있는 것이다.Therefore, the octagonal tape TP is attached as close to the mounting plate T as possible, so that the tie bar TB can be more firmly mounted, and at the same time, each inner lead L can be firmly supported. It is.

이러한 리드프레임(LF)은 제3도에서 보는 바와 같이 패키지 성형공정에서 몰드금형(MD)을 이용하여 패키지(P)를 성형시킬 때 액상의 컴파운드재(CP)가 충진공급 압력으로 공급되는 과정에서 타이바(TB)와 인너리드(L)는 중앙부분에 접착된 테이프 (TP)에 의해 견고히 지지되고 있는 관계로 탑재판(T)과 반도체칩(C)의 유동없이 정위치된 상태에서 패키지(P) 성형이 완료될 수 있는 것이다.In the lead frame LF, as shown in FIG. 3, in the process of supplying the liquid compound material CP at the filling supply pressure when forming the package P using the mold mold MD in the package forming process. Since the tie bar TB and the inner lead L are firmly supported by the tape TP attached to the center part, the tie bar TB and the inner lead L are held in a fixed state without the flow of the mounting plate T and the semiconductor chip C. P) Molding can be completed.

따라서, 반도체패키지(10)의 패키지성형시 패키지(P)의 성형작업성이 용이해지고, 나아가 반도체패키지의 제품신뢰성을 높일 수 있는 것이다.Therefore, the molding workability of the package P at the time of package molding of the semiconductor package 10 becomes easy, and also the product reliability of the semiconductor package can be improved.

이상에서와 같이 본 고안은 반도체패키지의 리드프레임에 형성된 다수의 인너리드 중 각 모퉁이 부분에 위치한 인너리드와 타이바를 팔각형태의 띠상으로 구성된 테이프(TP)의 한 변으로 접착시켜 줌으로써 타이바의 기지견고성을 높여 패키지성형시 탑재판과 반도체칩의 변형을 방지하고, 나아가 패기지 성형성을 높일 수 있는 효과를 제공하게 된다.As described above, the present invention bonds the base of the tie bar by bonding the inner lead and the tie bar at each corner of the plurality of inner leads formed in the lead frame of the semiconductor package to one side of the tape (TP) composed of octagonal bands. By increasing the rigidity, it is possible to prevent deformation of the mounting plate and the semiconductor chip during package molding, and further provide an effect of improving the package formability.

Claims (1)

반도체패키지(10)의 리드프레임(LF) 내부 중앙으로 탑재판(T)이 형성되고, 상기 탑재판(T)의 각 모퉁이에 타이바(TB)가 연결되며, 상기 탑재판(T)의 외부에 다수의 인너리드(L)가 배열 형성되고, 그리고 상기 다수의 인너리드(L) 및 타이바(TB)의 상면에 테이프(TF)를 일체적으로 부착한 것에 있어서, 상기 테이프(TP)가 팔각형태의 띠상으로 구성되어 인너리드(L) 또는 타이바(TB)의 전체길이 중 중앙부분에 해당하는 위치에 부착됨과 동시에 다수의 인너리드 중 각 모퉁이 부분에 위치한 인너리드와 타이바를 팔각형태의 띠상으로 구성된 테이프(TP)의 한 변으로 접착되도록 하는 것을 특징으로 하는 반도체패키지용 리드프레임.A mounting plate T is formed in the center of the lead frame LF of the semiconductor package 10, and tie bars TB are connected to corners of the mounting plate T, and the outside of the mounting plate T is formed. A plurality of inner leads (L) are formed in the array, and the tape (TP) is integrally attached to the upper surfaces of the plurality of inner leads (L) and tie bars (TB). It consists of an octagonal band shape and is attached to the position corresponding to the center of the entire length of the inner lead (L) or tie bar (TB), and at the same time, the inner lead and tie bar located at each corner of the plurality of inner leads are octagonal. A lead frame for a semiconductor package, characterized in that to be bonded to one side of the tape (TP) consisting of a band shape.
KR2019970010650U 1997-05-13 1997-05-13 Lead frame of semiconductor package type KR200160933Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019970010650U KR200160933Y1 (en) 1997-05-13 1997-05-13 Lead frame of semiconductor package type

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019970010650U KR200160933Y1 (en) 1997-05-13 1997-05-13 Lead frame of semiconductor package type

Publications (2)

Publication Number Publication Date
KR19980066267U KR19980066267U (en) 1998-12-05
KR200160933Y1 true KR200160933Y1 (en) 1999-11-15

Family

ID=19500899

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019970010650U KR200160933Y1 (en) 1997-05-13 1997-05-13 Lead frame of semiconductor package type

Country Status (1)

Country Link
KR (1) KR200160933Y1 (en)

Also Published As

Publication number Publication date
KR19980066267U (en) 1998-12-05

Similar Documents

Publication Publication Date Title
US6558980B2 (en) Plastic molded type semiconductor device and fabrication process thereof
US6258630B1 (en) Resin-sealed semiconductor device having island for mounting semiconductor element coupled to heat spreader
KR20030052502A (en) Lead-frame strip and process for manufacturing semiconductor packages using the same
US6686652B1 (en) Locking lead tips and die attach pad for a leadless package apparatus and method
KR200160933Y1 (en) Lead frame of semiconductor package type
US6692989B2 (en) Plastic molded type semiconductor device and fabrication process thereof
US6762490B2 (en) Semiconductor device and method for producing the same
KR100268756B1 (en) A structure of seperat type diepad for leadframe
US20080157297A1 (en) Stress-Resistant Leadframe and Method
KR100191859B1 (en) A leadframe and method for forming a package of semiconductor device mounted on the leadframe
KR200141125Y1 (en) Structure of lead frame
KR940002389B1 (en) Semiconductor leadframe
KR950007768Y1 (en) Thin type flexibie package
KR970004618Y1 (en) Lead on chip semiconductor package
KR200149156Y1 (en) Leadframe
KR200173050Y1 (en) Super thin semiconductor package
JPH04317363A (en) Resin sealed semiconductor device without die pad and its manufacturing method
JPH05243464A (en) Lead frame and plastic molded type semiconductor device using the same
JP2005183492A (en) Semiconductor device
KR100726039B1 (en) Multi-layered lead frame and manufacturing method thereof
KR19990006940A (en) Improved Lead Chip Bonding Structure for Semiconductor Devices and Leadframes Used therein
KR200286323Y1 (en) Semiconductor package
KR20010027844A (en) Leadframe
KR19990008823A (en) Lead frame with curved bends
KR20010046383A (en) Lead on chip type lead frame comprising dummy leads

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 20110817

Year of fee payment: 13

EXPY Expiration of term