KR20010112815A - Method of Fabricating Liquid Crystal Display Device - Google Patents

Abstract

The described CAD system enables a drafter to easily enter dimension entities, which describe the physical dimensions of an object in a CAD drawing or model. The dimension entities define either linear, angular, or radial dimensions, and for each dimension entity, the user defines a reference origin in addition to the normal dimensional information. The value of each defined dimension entity may be a simple constant, a parameter, or an expression of multiple constants and parameters. By virtue of the added reference origin, a very complex network of related dimension entities can be simply defined and easily modified. The recalculation of the dimension entities is performed by a parametric dimensioning engine that transforms groups of entities from the global space of the general CAD drawing or model into a local space. While in local space, the parametric dimensioning recalculates the coordinate data of the entities.

Description

Method of manufacturing liquid crystal display device {Method of Fabricating Liquid Crystal Display Device}

The present invention relates to a method for manufacturing a liquid crystal display device, and more particularly, to a method for manufacturing a liquid crystal display device that can reduce the process by using four masks.

The liquid crystal display device includes a switching element composed of a thin film transistor composed of a gate electrode, a gate insulating layer, an active layer, an ohmic contact layer, a source and a drain electrode, a lower plate on which a pixel electrode is formed, and an upper plate on which a color filter is formed. It consists of the injected liquid crystal.

When manufacturing the lower plate by the conventional method described above, five masks are required to pattern the contact holes and pixel electrodes in the gate electrode, the active layer and the ohmic contact layer, the source and drain electrodes, and the passivation layer. Therefore, research is being actively conducted to form a lower plate by reducing the number of masks and proceeding with only four masks.

1A to 1D are manufacturing process diagrams of a liquid crystal display device using four masks according to the prior art.

Referring to FIG. 1A, a metal thin film is formed by depositing aluminum (Al) or copper (Cu) on a transparent substrate 11 having an array region A1 and a peripheral region P1 by sputtering or the like. Form. The metal thin film is patterned to remain in a predetermined portion on the array region A1 of the transparent substrate 11 by a photolithography method including a wet etching method to form the gate electrode 13 and the gate line 14. In this case, the metal thin film is left on the peripheral region P1 of the transparent substrate 11 to form the gate pad 15 used as an input / output pad.

Referring to FIG. 1B, the gate insulating layer 17, the active layer 19, and the ohmic contact layer 21 may be covered on the transparent substrate 11 to cover the gate electrode 13, the gate line 14, and the gate pad 15. Are formed sequentially by chemical vapor deposition (hereinafter referred to as CVD). The gate insulating layer 17 is formed by depositing an insulating material such as silicon oxide or silicon nitride, and the active layer 19 is formed of amorphous silicon or polycrystalline silicon that is not doped with impurities. In addition, the ohmic contact layer 21 is formed of amorphous silicon or polycrystalline silicon doped with N-type or P-type impurities at a high concentration.

Referring to FIG. 1C, a metal such as molybdenum (Mo), titanium, or tantalum, or a molybdenum alloy such as MoW, MoTa, or MoNb may be covered on the ohmic contact layer 19 on the ohmic contact layer 21. Deposition is by CVD method or sputtering method. The deposited metal or metal alloy is in ohmic contact with the ohmic contact layer 21. Then, the metal or metal alloy and the ohmic contact layer 21 are patterned by photolithography to form the source and drain electrodes 23 and 25, a data line and a data pad (not shown), and the ohmic contact layer 21. Is patterned in the same manner as the source and drain electrodes 23 and 25, the data line, and the data pad.

Referring to FIG. 1D, the passivation layer 27 is formed by depositing an inorganic insulating material such as silicon oxide or silicon nitride so as to cover the source and drain electrodes 23 and 25 on the active layer 19. The passivation layer 27 may be formed of an organic insulator having a low dielectric constant such as an acryl-based organic compound, benzocyclobutene (BCB), or perfluorocyclobutane (PFCB).

The passivation layer 27, the active layer 19, and the gate insulating layer 17 of the transparent substrate 11 are sequentially patterned by photolithography so as to remain only in portions corresponding to the thin film transistor portion, the gate and the data pad portion. In this case, a first contact hole 29 exposing the drain electrode 23 and a second contact hole not shown to expose the data pad (not shown) are formed. In addition, a third contact hole 31 exposing the gate pad 15 is formed. In this case, since the etch selectivity of the drain electrode 23 and the data pad is different from the passivation layer 27, the active layer 19, and the gate insulating layer 17, the first contact hole 29 and the second contact hole correspond to the drain electrode ( 23) and only the data pad.

Indium tin oxide is in contact with the source electrode 23, the data pad, and the gate pad 15 through the first and third contact holes 29 and 31 and the second contact hole on the passivation layer 25. A transparent conductive material such as oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO) is deposited. Then, the transparent conductive material is patterned to form the pixel electrode 27 in contact with the drain electrode 23 through the first contact hole 29 in the array region A1 and at the peripheral region P1. The protective electrode 35 is formed to contact the data pad and the gate pad 15 through the second contact hole and the third contact hole 31.

However, in the method of manufacturing the liquid crystal display device, since the gate line is exposed by patterning the gate insulating layer in the process of forming the third contact hole, the gate line is damaged and disconnected by the pixel electrode etchant when the pixel electrode is formed. there was.

Accordingly, an object of the present invention is to provide a method of manufacturing a liquid crystal display device capable of preventing the damage caused by the patterning by preventing the exposure of the gate line.

1A to 1D are manufacturing process diagrams of a liquid crystal display device according to the prior art.

2A to 2F are manufacturing process diagrams of the liquid crystal display device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

41: transparent substrate 43: gate electrode

44: gate line 45, 69: first and second pad

47: gate insulating film 49: active layer

51: ohmic contact layer 53: metal layer

55 and 56 photoresist patterns 57 and 65 contact holes

59, 61 source and drain electrodes 63 passivation layer

67 pixel electrode

In order to achieve the above object, a method of manufacturing a liquid crystal display device according to the present invention comprises the steps of forming a first electrode pattern including a gate electrode and a gate line and a gate pad on a transparent substrate, Sequentially forming a gate insulating layer, an active layer, and an ohmic contact layer to cover an electrode pattern, forming a metal layer on the ohmic contact layer, and having a different thickness on the metal layer and corresponding to the gate pad; Forming a second photoresist pattern including a source and a drain electrode, a data line, and a data pad by forming a photoresist pattern partially exposing the photoresist; and patterning the metal layer using the photoresist pattern. Patterning and forming a passivation layer on the active layer to cover the second electrode pattern. Patterning the passivation layer and the active layer so as to remain only in a portion corresponding to the second electrode pattern, and forming a pixel electrode in contact with the drain electrode and a protection electrode in contact with the gate and data pad. Characterized in that it comprises a.

Other objects and features of the present invention in addition to the above objects will become apparent from the following description of the embodiments with reference to the accompanying drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are manufacturing process diagrams of the liquid crystal display device using the 4 mask process according to the present invention.

Referring to FIG. 2A, aluminum (Al) or copper (Cu) is deposited on the transparent substrate 41 having the array region A2 and the peripheral region P2 by sputtering or coated by electroless plating. A metal thin film is formed. As the transparent substrate 41, glass, quartz or transparent plastic may be used. The metal thin film is patterned to remain in a predetermined portion on the array region A2 of the transparent substrate 41 by a photolithography method including a wet etching method to form the gate electrode 43 and the gate line 44. At this time, the metal thin film is left on the peripheral region P2 of the transparent substrate 41 to form the gate pad 45 used as an input / output pad.

Referring to FIG. 2B, the gate insulating layer 47, the active layer 49, and the ohmic contact layer 51 may cover the gate electrode 43, the gate line 44, and the gate pad 45 on the transparent substrate 41. Are sequentially formed using the CVD method. The gate insulating film 47 is formed of an insulating material such as silicon oxide or silicon nitride, and the active layer 49 is formed of amorphous silicon or polycrystalline silicon that is not doped with impurities. In addition, the ohmic contact layer 51 is formed of amorphous silicon or polycrystalline silicon doped with N-type or P-type impurities at a high concentration. A source / drain metal layer 53 is deposited on the ohmic contact layer 51 by depositing a metal such as molybdenum (Mo), titanium, or tantalum, or a molybdenum alloy such as MoW, MoTa, or MoNb by a CVD method or a sputtering method. To form. The source / drain metal layer 53 is in ohmic contact with the ohmic contact layer 51. A photoresist is applied on the source / drain metal layer 53 to a uniform thickness. By patterning the photoresist, the portion where the source and drain electrodes, the data lines, and the data pads are to be formed in the array region A2 has the first thickness, and the remaining portions have a thickness of about 10 to 50% of the initial thickness. In P2, the metal layer 53 of the portion corresponding to the gate pad 45 forms a photoresist pattern 55 that is exposed. A portion of the photoresist pattern 55 having a thickness of about 10 to 50% of the initial thickness can be formed by using a halftone mask or a diffraction mask during exposure. The photoresist pattern 55 is used as a mask to remove the source / drain metal layer 53 exposed in the peripheral region P2 by a wet etching method so that the ohmic contact layer 51 is exposed.

Then, dry etching is performed to remove the ohmic contact layer 51 and the active layer 49 exposed from the gate pad part. Alternatively, dry etching may be performed to remove the ohmic contact layer 51, the active layer 49, and the gate insulating layer 47 exposed from the gate pad part. The dry etching process also removes portions having a thin thickness of about 10 to 50% from the photoresist pattern 55, so that the photoresist pattern 55 can be provided with source and drain electrodes, data lines, and the like as shown in FIG. Only the part where the data pad is to be formed is present. Then, an ashing process is used to completely remove the photoresist remaining in the region where the photoresist pattern 55 is removed. Subsequently, the exposed source / drain metal layer 53 is wet-etched using the remaining photoresist pattern 56 as a mask to form source / drain electrodes 59 and 61, data lines, and data pads. The exposed ohmic contact layer 51 is dry etched and patterned in the same manner as the source and drain electrodes 59 and 61, the data line, and the data pad as shown in FIG. 2C.

Referring to FIG. 2D, the photoresist pattern 56 remaining on the source and drain electrodes 59 and 61, the data line, and the data pad is removed.

Referring to FIG. 2E, the passivation layer 63 is formed by depositing an inorganic insulating material such as silicon oxide or silicon nitride so as to cover the source and drain electrodes 59 and 61 on the active layer 49. The passivation layer 63 may be formed of an organic insulator having a low dielectric constant such as an acryl-based organic compound, BCB, or PFCB. The passivation layer 63 and the active layer 49 are then patterned using a two-step dry etching method so that only the source and drain electrodes 59 and 61 on the array region A2 and the portions corresponding to the data lines remain. do.

In detail, in the first dry etching process, the passivation layer 63 is patterned using a gas capable of selectively etching an inorganic insulating material or a storage insulating material of the passivation layer 63 and an amorphous silicon material of the active layer 49. In this case, only the passivation layer 63 is etched in the array area A2, and the passivation layer 63 and the gate insulating layer 47 are simultaneously etched in the first contact hole 57 of the gate pad part. Subsequently, the active layer 49 exposed in the second dry etching process is etched. At this time, the amorphous silicon of the active layer 49 and the inorganic insulating material of the gate insulating layer 47 are selectively etched so that the stable gate insulating layer 47 remains in the remaining region except for the first contact hole 57 of the gate pad part.

Referring to FIG. 2F, the indium tin layer covers the passivation layer 63 on the gate insulating layer 47 and contacts the gate pad 57 and the drain electrode 61 through the first and second contact holes 57 and 65. Transparent conductive materials such as indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO) are deposited. The pixel is patterned with a transparent conductive material to contact the drain electrode 61 and the gate pad 45 through the second and first contact holes 65 and 57 in the array region A2 and the peripheral region P2, respectively. The electrode 67 and the protective electrode 69 are formed. In this case, since the gate line 44 is not covered and exposed by the gate insulating layer 47, the gate line 44 is not damaged by an etchant during patterning to form the pixel electrode 67 and the protection electrode 69.

As described above, according to the method of manufacturing the liquid crystal display device according to the present invention, multiple etching is performed using halftone or diffraction mask for multi-layer etching during source / drain electrode patterning, and double etching during passivation layer and active layer patterning. When the active layer is etched, an etchant having good selectivity between the active layer and the gate insulating layer is used so that the gate insulating layer remains on the gate line. Accordingly, the gate line may be prevented from being damaged by the pixel electrode etchant during the pixel electrode patterning.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (9)

Forming a first electrode pattern including a gate electrode, a gate line, and a gate pad on the transparent substrate; Sequentially forming a gate insulating layer, an active layer, and an ohmic contact layer on the transparent substrate to cover the first electrode pattern; Forming a metal layer on the ohmic contact layer and forming a photoresist pattern on the metal layer, the photoresist pattern having a partially different thickness and partially exposing the metal layer corresponding to the gate pad; Patterning the metal layer using the photoresist pattern to form a second electrode pattern including a source and drain electrode, a data line, and a data pad, and patterning the ohmic contact layer; Forming a passivation layer covering the second electrode pattern on the active layer and patterning the passivation layer and the active layer so as to remain only in a portion corresponding to the second electrode pattern; Forming a pixel electrode in contact with the drain electrode and a protection electrode in contact with the gate and data pad. The method of claim 1, The photoresist pattern is After applying the photoresist on the whole surface, it has a first thickness applied in a first region corresponding to a portion where the second electrode pattern is to be formed by using any one of a halftone mask and a diffraction mask during exposure, and in the remaining second regions And a second thickness thinner than the first thickness and formed to expose the metal layer in a third region corresponding to the gate pad. The method of claim 2, Wherein the first photoresist pattern is formed such that the second thickness has a thickness of about 10 to 50% of the first thickness. The method of claim 2, And wet-etching the exposed metal layer after forming the photoresist pattern. The method of claim 4, wherein And etching the exposed metal layer and performing dry etching to remove the exposed ohmic contact layer and the active layer under the exposed metal layer. The method of claim 4, wherein And etching the exposed metal layer and performing dry etching to remove the exposed ohmic contact layer, the active layer and the gate insulating layer below the exposed metal layer. The method according to any one of claims 5 and 6, And removing the photoresist pattern on the second region, which is etched together during the dry etching, completely using an ashing process. The method of claim 1, Patterning the passivation layer and the active layer Patterning the passivation layer through a dry etching process using a gas capable of selectively etching a passivation layer and an active layer material; And patterning the active layer through a dry etching process using an active layer material and a gas capable of selectively etching the gate insulating film material. The method of claim 1, And simultaneously etching the gate insulating layer corresponding to the gate pad when the passivation layer is patterned.