KR20010085475A - Method for manufacturing electronic semiconductor elements - Google Patents

Method for manufacturing electronic semiconductor elements Download PDF

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Publication number
KR20010085475A
KR20010085475A KR1020010008943A KR20010008943A KR20010085475A KR 20010085475 A KR20010085475 A KR 20010085475A KR 1020010008943 A KR1020010008943 A KR 1020010008943A KR 20010008943 A KR20010008943 A KR 20010008943A KR 20010085475 A KR20010085475 A KR 20010085475A
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South Korea
Prior art keywords
substrate
semiconductor
housing body
surface side
electrical connection
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KR1020010008943A
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Korean (ko)
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페터 뮐레크
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귄터 무스함마
비쉐이 세미컨덕터 게엠베하
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Publication of KR20010085475A publication Critical patent/KR20010085475A/en

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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
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Abstract

PURPOSE: A method for fabricating an electronic semiconductor device is provided to inexpensively mass-produce a small electronic semiconductor device, by eliminating the necessity for an elaborate unit for forming a contact part between the upper and lower portions of a printed circuit board. CONSTITUTION: A conductive board(1) is prepared. A semiconductor chip is attached to the first surface(1.1) of the board. An electrical connection part is formed from the semiconductor chip to the first surface of the board. The semiconductor chip and the electrical connection part are sealed with an insulation material to form a housing body(4). The second surface(1.2) opposite to the first surface is separated from the board to form terminal parts(5,5.1,5.2) which are electrically insulated from each other.

Description

전자 반도체 소자의 제조 방법 {METHOD FOR MANUFACTURING ELECTRONIC SEMICONDUCTOR ELEMENTS}Manufacturing Method of Electronic Semiconductor Device {METHOD FOR MANUFACTURING ELECTRONIC SEMICONDUCTOR ELEMENTS}

본 발명은 청구범위 제 1항의 전제부에 따른 표면 장착용 전자 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a surface mounting electronic semiconductor device according to the preamble of claim 1.

이런 종류의 최신 제조 방법은 예를 들어, 독일 공개 공보 DE 195 44 980 A1로부터 공지된다. 상기 제조 방법으로, 발광 소자는 전기 단자가 절연 기판의 하부측에 형성되며, 땜납과 같은 도전 접속 매체에 의해 LED 칩의 n측 및 p측 전극에 접속되는 상기 기판의 상부측에 형성됨으로써 제조된다. LED 칩과 도전 접속 매체는 절연 기판 상에서 반투명성(translucent) 수지에 의해 밀봉된다.State-of-the-art manufacturing methods of this kind are known, for example, from German publication DE 195 44 980 A1. In the above manufacturing method, the light emitting element is manufactured by forming an electrical terminal on the lower side of the insulated substrate and forming on the upper side of the substrate connected to the n-side and p-side electrodes of the LED chip by a conductive connection medium such as solder. . The LED chip and the conductive connection medium are sealed by a translucent resin on the insulating substrate.

그러나, 상기 제조 방법은 발광 소자가 비교적 큰 치수로 제조되며, 구조화된 인쇄회로기판이 요구되며, 인쇄회로기판의 하부측과 상부측 사이에 접촉부를 형성하는 정교한 수단이 제공되야 한다는 단점을 가진다.However, the manufacturing method has the disadvantage that the light emitting device is manufactured with a relatively large dimension, a structured printed circuit board is required, and a sophisticated means for forming a contact portion between the lower side and the upper side of the printed circuit board must be provided.

본 발명의 목적은 청구범위 제 1항의 전제부에 따른 방법으로, 초소형 전자 반도체 소자가 저비용으로 그리고 단순한 방식으로 대량 생산될 수 있도록 설계하는 것이다.It is an object of the present invention to design a microelectronic semiconductor device in mass production at low cost and in a simple manner by the method according to the preamble of claim 1.

본 발명의 목적은 청구범위 제 1항에 기술된 특징부의 방법에 의해 달성될 수 있다.The object of the invention can be achieved by the method of the features described in claim 1.

도 1a-d는 기판 상에 장착되는 발광 반도체 소자가 도시되며, 본 발명에 따른 제 1 제조 방법의 다양한 여러 공정 단계를 설명하는 사시도.1A-D show a light emitting semiconductor device mounted on a substrate, illustrating a perspective view illustrating various various process steps of a first manufacturing method according to the present invention.

도 2는 본 발명의 방법에 따른 몰딩 공정을 통해 제조되는 다수의 발광 반도체 소자의 사시도.2 is a perspective view of a plurality of light emitting semiconductor devices manufactured through a molding process according to the method of the present invention.

도 3은 연속적으로 연결된 여러 개의 몰딩된 발광 반도체 소자의 사시도.3 is a perspective view of several molded light emitting semiconductor devices connected in series.

도 4는 주석 전기 단자를 가지는 본 발명의 방법에 따라 제조된 하나의 발광 반도체 소자의 하부측 사시도.4 is a bottom side perspective view of one light emitting semiconductor device made in accordance with the method of the present invention having tin electrical terminals.

도 5a는 본 발명의 방법에 따라 제조된 외부 치수가 기입된 반도체 소자의 사시도.5A is a perspective view of an externally dimensioned semiconductor device made in accordance with the method of the present invention.

도 5b는 본 발명의 방법에 따라 제조된 내부 치수가 기입된 반도체 소자의 측면도.5B is a side view of an internally dimensioned semiconductor device made in accordance with the method of the present invention.

도 5c-e는 광학 커플링 소자 및 광학 디커플링 소자가 하우징 몸체 내에 집적되며 본 발명의 방법에 따라 제조되는 여러 개의 반도체 소자의 사시도.5C-E are perspective views of several semiconductor devices in which the optical coupling element and the optical decoupling element are integrated within the housing body and are manufactured according to the method of the present invention.

도 6은 길이 방향의 캐리어 스트립 상에 장착된 예시적인 발광 반도체 소자를 도시하며, 본 발명에 따른 제 2 제조 방법의 여러 공정 단계를 설명하는 사시도.6 shows an exemplary light emitting semiconductor device mounted on a carrier strip in the longitudinal direction, illustrating a perspective view of the various process steps of a second manufacturing method according to the invention.

*도면의 주요부분에 대한 부호 설명** Description of symbols on the main parts of the drawings *

1 : 기판 1.1 : 기판의 상부측1: substrate 1.1: upper side of the substrate

1.2 : 기판의 하부측 2 : 반도체 칩1.2: lower side of the substrate 2: semiconductor chip

3.1 : 결합 배선 3.2 : 도전성 접착제3.1: bonded wiring 3.2: conductive adhesive

4 : 하우징 몸체 5 : 발광 반도체 소자의 전기 단자부4 housing body 5 electrical terminal portion of light emitting semiconductor element

5.1 : 전기 단자부의 애노드 5.2 : 전기 단자부의 캐소드5.1: anode of electrical terminal part 5.2: cathode of electrical terminal part

6 : 브리지 7.1, 7.2 : 스프루6: bridge 7.1, 7.2: sprue

8 : 트랜스퍼 개구 9 : 두꺼운 브리지8: transfer opening 9: thick bridge

10 : 발광 반도체 소자 11 : 금속 캐리어 스트립10 light emitting semiconductor element 11: metal carrier strip

12-16 : 제 1-5 워크 스테이션 17 : 테스트 프로브12-16: 1-5 Workstation 17: Test Probe

18 : 구형 렌즈 19 : 원통형 렌즈18: spherical lens 19: cylindrical lens

20 : 광섬유 리셉터클 21 : 광섬유 리셉터클의 개구20: optical fiber receptacle 21: opening of optical fiber receptacle

청구범위 제 1항의 방법에 따라 제조된 전자 반도체 소자는 단순하게 그리고 저가로 제조될 수 있으며 상기 소자의 접촉 표면이 밀봉 물질로 오염되지 않는다는 장점을 가진다. 또한, 상기 설계는 반도체 몸체에서 발생되는 열을 제거할 수 있는 우수한 능력을 제공한다.Electronic semiconductor devices made according to the method of claim 1 can be manufactured simply and inexpensively and have the advantage that the contact surfaces of the devices are not contaminated with sealing material. The design also provides an excellent ability to remove heat generated in the semiconductor body.

본 발명은 디스플레이 패널에서 광 소스(액정 디스플레이용 배경 광)로서 사용되며 광 스위치에서 광 소스로서 사용되는 소형 발광 소자의 제조에 적합하며 다이오드, 트랜지스터 및 집적 회로와 같은 능동 및 수동 전자 소자에도 적합하다.The invention is suitable for the manufacture of small light emitting devices used as light sources (background light for liquid crystal displays) in display panels and as light sources in optical switches, and also for active and passive electronic devices such as diodes, transistors and integrated circuits. .

청구범위 제 1항에 따른 방법의 장점은 종속 청구항에 기재되어 있다.The advantages of the method according to claim 1 are described in the dependent claims.

본 발명은 도면을 참조로 한 실시예를 통해 기술될 것이다.The invention will be described through an embodiment with reference to the drawings.

도 1a 내지 1d는 본 발명에 따른 제 1 제조 방법의 여러 공정 단계를 설명하는 투시도이며, 도전 기판(1)상에 장착된 발광 반도체 소자(10)의 예를 도시한다.1A to 1D are perspective views illustrating various process steps of the first manufacturing method according to the present invention, showing an example of a light emitting semiconductor element 10 mounted on a conductive substrate 1.

도 1a는 제 1 표면측(1.1)으로서 상부측, 제 2 표면측(1.2)으로서 하부측 및 기판(1)의 부정확한 방향 설정을 방지하기 위한 간단한 특징의 차단 코너(1.3)를 가진 도전 기판(1)을 도시한다. 구리 합금 또는 비교 가능한 물질로 구성된 직사각형 금속 캐리어 기판은 예를 들어, 도전 기판(1)으로서 사용된다. 발광 반도체 소자는 기판(1)의 상부측(1.1)에 규칙적인 방식, 예를 들어, 행과 열의 방식으로 정렬된다. 제조되는 반도체 소자의 전기 접속 영역(단자, 전극)(5)은 하부측(1.2)에 나중에 형성된다. 기판(1)의 크기는 현금 카드와 대략 같지만, 장착되는 반도체 소자(10)와 사용되는 제조 장비의 치수에 따라 다르다; 기판의 두께는 대략 125μm이다. 트랜스퍼(transfer) 개구(8)는 이동 및 제조 장비의 배치를 위해 제공된다.FIG. 1A shows a conductive substrate with a blocking corner 1.3 of a simple feature for preventing incorrect orientation of the substrate 1 with the upper side as the first surface side 1.1, the lower side as the second surface side 1.2 and FIG. 1. (1) is shown. Rectangular metal carrier substrates composed of copper alloys or comparable materials are used, for example, as the conductive substrate 1. The light emitting semiconductor elements are arranged in a regular manner, for example in the manner of rows and columns, on the upper side 1.1 of the substrate 1. An electrical connection region (terminal, electrode) 5 of the semiconductor element to be manufactured is formed later on the lower side 1.2. The size of the substrate 1 is about the same as a cash card, but depends on the dimensions of the semiconductor device 10 to be mounted and the manufacturing equipment used; The thickness of the substrate is approximately 125 μm. A transfer opening 8 is provided for the placement of the movement and manufacturing equipment.

제 1 단계에서, 발광 반도체 몸체(2)는 예를 들어, 기판(1)의 제 1 상부측(1.1)에 부착된다. 따라서, 기판(1)은 특히, 도 1b에 도시된 발광 반도체 몸체 또는 반도체 칩(2)용 캐리어로서 사용된다. 기판(1)에 반도체 칩을 부착하기 위해 기판(1)의 상부측(1.1)에 각각의 발광 반도체 칩(2)을 기계적 수단에 의해 장착하는 것이 바람직하다. 동시에, 반도체 칩(2)의 하방의 후면 접촉부는 제 1 연결점에 은과 같은 도전성 접착제(3.2)(도 5b)에 의해 상부측(1.1)에 도전적으로 접속됨으로써 반도체 몸체(2)에서 기판(1)의 제 1 상부측(1.1)까지 제 1의 전기 접속부가 형성된다. 적절한 후면 접촉부가 있으면, 반도체 칩(2) 또한 열적 칩 결합에 의해 상부측(1.1)에 땜납될 수 있거나 다른 방식으로 상부측에 접촉될 수 있다.In the first step, the light emitting semiconductor body 2 is attached, for example, to the first upper side 1.1 of the substrate 1. Thus, the substrate 1 is used in particular as a carrier for the light emitting semiconductor body or semiconductor chip 2 shown in FIG. 1B. In order to attach the semiconductor chip to the substrate 1, it is preferable to mount each light emitting semiconductor chip 2 on the upper side 1.1 of the substrate 1 by mechanical means. At the same time, the rear contact portion below the semiconductor chip 2 is conductively connected to the upper side 1.1 by means of a conductive adhesive 3.2 (FIG. 5B), such as silver, at the first connection point, thereby providing the substrate 1 in the semiconductor body 2. A first electrical connection is formed to the first upper side 1.1 of. If there is a suitable backside contact, the semiconductor chip 2 can also be soldered to the upper side 1.1 by thermal chip bonding or otherwise contacted to the upper side.

다음으로 각각의 발광 반도체 칩(2)의 제 2 접촉부, 즉 상방의 전면 접촉부는 제 1 접속점과 짧은 거리로 금 또는 알루미늄으로 구성된 결합 배선(3.1)에 의해 제 2 단자점에 접속됨으로써 기판(1)의 상부측(1.1)에 결합에 의해 각각의 발광 반도체 몸체(2)로부터 기판(1)의 제 1 상부측(1.1)까지 제 2 전기 접속부가 형성된다.Next, the second contact portion, i.e., the upper front contact portion, of each of the light emitting semiconductor chips 2 is connected to the second terminal point by a coupling wiring 3.1 composed of gold or aluminum at a short distance from the first connection point, thereby providing a substrate 1 The second electrical connection is formed from each light emitting semiconductor body 2 to the first upper side 1.1 of the substrate 1 by coupling to the upper side 1.1 of the ().

결합 후, 기판(1)의 상부측(1.1)에 부착된 각각의 발광 반도체 몸체(2)는 추가의 공정 단계에서 하우징 몸체(4)에 제공된다. 이를 위하여, 결합 배선(3.1, 3.2)을 포함하는 상부측(1.1)에 부착된 각각의 발광 반도체 칩(2)은 몰딩 공정에 의해, 즉 주조, 사출 성형, 또는 도 1c에서 도시된 종래의 다른 제조 수단에 의한 공지된 방식을 통해 절연 물질로 밀봉된다. 몰딩 공정과 함께 몰딩 물질이라고도 하는 절연 물질은 예를 들어, 열가소성 물질이다.After bonding, each light emitting semiconductor body 2 attached to the upper side 1.1 of the substrate 1 is provided to the housing body 4 in a further process step. To this end, each of the light emitting semiconductor chips 2 attached to the upper side 1.1 including the coupling wirings 3.1 and 3.2 is formed by a molding process, that is, casting, injection molding, or other conventional art shown in FIG. 1C. It is sealed with insulating material through a known manner by the manufacturing means. Insulating materials, also called molding materials, together with the molding process are, for example, thermoplastics.

하우징 몸체(4)를 형성하는 제 1의 선택적 방법은 모든 발광 반도체 소자(10)가 동시에 형성될 수 있도록 몰딩될 때 몰딩 다이(die)의 각각의 공동을 사용하는 것이다. 몰딩 물질이 흘러 들어갈 수 있게 하는 몰딩 다이(몰딩 게이트로도 공지됨)에서 동작되는 채널로 인해, 몰딩 공정 동안 행 또는 열로 정렬된 반도체 소자(10)의 하우징 몸체(4) 사이에 브리지(6)가 형성된다.The first alternative method of forming the housing body 4 is to use each cavity of the molding die when molded so that all the light emitting semiconductor elements 10 can be formed simultaneously. Due to the channel operated in the molding die (also known as the molding gate) which allows the molding material to flow in, the bridge 6 between the housing bodies 4 of the semiconductor elements 10 arranged in rows or columns during the molding process Is formed.

일반적으로, 상기 브리지(6)는 몰딩으로부터 제거 후에 즉,브래이킹(breaking), 절단 또는 다른 방법을 통해서 몰딩 다이로부터 제조된 부분을 제거한 후에 즉시 제거된다. 본 발명의 경우에는, 브리지(6)를 곧 바로 제거하지 않고 잠시 후에 제거하여 잠시동안 임의의 반도체 소자(10) 수가 하우징 몸체(4)에 의해 연결된 상태로 남아있도록 하는 것이 바람직하다.In general, the bridge 6 is removed immediately after removal from the molding, i.e. after removing the part produced from the molding die by breaking, cutting or otherwise. In the case of the present invention, it is preferable not to immediately remove the bridge 6 but to remove it after a while so that for a while, any number of semiconductor elements 10 remain connected by the housing body 4.

첫 번째로, 이것은 제조 공정 동안 조작을 상당히 단순화시키며, 그 다음으로 이것은 함께 연결된 반도체 소자(10)가 한 번에 연속 공정 단계에 공급될 수 있게 한다; 이것은 또한 반도체 소자(10)가 예를 들어, 전기 기능을 검사 받을 때, 극성이 변하지 않도록 같은 방향으로 향한다.Firstly, this greatly simplifies the operation during the manufacturing process, which in turn allows the semiconductor elements 10 connected together to be supplied at one time in a continuous process step; It is also directed in the same direction so that the polarity does not change when the semiconductor device 10 is tested for electrical function, for example.

하우징 몸체(4)를 형성하는 제 2 선택적 방법은 제 1 선택 방법에서와 같이 반도체 소자(10)가 그룹으로 함께 연결되도록 몰딩 물질로서 사용된 열가소성 물질로 전체 상부측(1.1)을 몰딩하는 것이며, 따라서 반도체 소자(10)가 즉시 개체로 분리되는 것 보다 제조 공정에서 조정하는 것이 더 쉽다. 반도체 소자(10)가 예를 들어, 소잉(sawing) 공정을 통해 나중에 분리되어 개체가 된다. 이 선택적 방법에서도 역시, 반도체 소자가 연속해서 그룹을 이루는 한 반도체 소자(10)의 전기 기능을 검사하기 쉬워진다.The second optional method of forming the housing body 4 is to mold the entire upper side 1.1 with a thermoplastic material used as the molding material so that the semiconductor elements 10 are connected together in groups as in the first selection method, Therefore, it is easier to adjust in the manufacturing process than the semiconductor device 10 is immediately separated into individuals. The semiconductor element 10 is later separated and becomes an object, for example, through a sawing process. Also in this selective method, it becomes easy to test the electrical function of the semiconductor element 10 as long as the semiconductor element is grouped continuously.

도 1d는 구조, 즉 단자부(5.1, 5.2)가 이미 제공된 기판(1)의 하부측(1.2)을 도시한다. 레이저 수단을 통한 에칭 또는 소잉 공정에 의해, 물질을 제거함으로써 상기 구조가 형성된다. 에칭을 통해 물질을 제거하기 전에, 하부측(1.2)은 우선 감광성 래커(lacquer)로 공지된 방식으로 코팅되야 하며, 다음으로 래커는 포토리소그라피에 의해 마스킹(즉, 원하는 지점에 노광)해야 하며 기판(1)은 더 이상 필요치 않은 물질이 특정 시간 후에 특정 온도에서 화학적 수단에 의해 제거되도록 산(acid) 용기에 담궈져야 한다.FIG. 1D shows the structure, ie the lower side 1.2 of the substrate 1, on which the terminal portions 5.1, 5.2 have already been provided. The structure is formed by removing material by etching or sawing process through laser means. Before the material is removed by etching, the lower side 1.2 must first be coated in a manner known as photosensitive lacquer, and then the lacquer must be masked by photolithography (i.e. exposed to the desired point) and the substrate (1) should be soaked in an acid container so that substances that are no longer needed are removed by chemical means at a certain temperature after a certain time.

기판(1)의 에지측 또는 차단 코너(1.3)와 함께 트랜스퍼 개구(8)는 제조될 구조의 방향을 설정할 수 있게 한다.The transfer opening 8 together with the edge side or blocking corner 1.3 of the substrate 1 makes it possible to orient the structure to be manufactured.

하부측(1.2)에 구조를 형성할 때 시간 순서에 따라 상이한 선택 방법이 존재한다. 제 1 선택 방법은 하우징 몸체(4) 하부의 일부 영역에서 그리고 동시에 예를 들어, 에칭을 통해서 전기 단자부(5, 5.1, 5.2)의 외곽선을 따라 기판(1)을 완전히 분리시키는 것이다. 이 때, 전기 단자부(5, 5.1, 5.2)는 한 단계로 서로 완전히 분리되어 절연되며 반도체 소자(10)는 기판에서 분리된다. 행으로 배치된 반도체 소자(10)는 브리지(6)를 통해서만 함께 연결되며 연속적인 제조 단계에서 이런 형태(도 3에서 도시된 바와 같이)로 공급된다.There are different selection methods depending on the time sequence when forming the structure on the lower side 1.2. The first selection method is to completely separate the substrate 1 along the outline of the electrical terminal portions 5, 5.1, 5.2 in some region under the housing body 4 and at the same time, for example, by etching. At this time, the electrical terminal portions 5, 5.1, 5.2 are completely insulated from each other in one step and the semiconductor element 10 is separated from the substrate. The semiconductor elements 10 arranged in a row are connected together only via the bridge 6 and are supplied in this form (as shown in FIG. 3) in successive manufacturing steps.

제 2의 선택 방법은 예를 들어, 에칭 공정을 통해서 후면 접촉부(5.1, 5.2) 사이의 하우징 몸체(4) 하부의 일부 영역을 간단히 분리하는 것이다. 이 경우에, 결과로 형성된 전기 단자부(단자부들)(5.1, 5.2)는 이후에 주석 도금되어 최종 장착된 반도체 소자(10)는 부분 동작(커팅, 소잉, 스탬핑 또는 이런 종류)에서 개체가 된다. 예를 들어 갈바니 드럼(galvanic drum) 주석 도금에 의해 개체화된 후에, 단자부(5.1, 5.2)는 주석 도금될 수 있다.The second method of selection is to simply separate some areas of the lower part of the housing body 4 between the back contacts 5. 1, 2. 5, for example, by means of an etching process. In this case, the resulting electrical terminal portions (terminal portions) 5.1, 5.2 are subsequently tinned and the finally mounted semiconductor element 10 becomes an object in partial operation (cutting, sawing, stamping or this kind). After being individualized for example by galvanic drum tin plating, the terminal portions 5.1, 5.2 can be tin plated.

제 3의 선택 방법은 후면 단자부(5.1, 5.2) 사이의 하우징 몸체(4)의 하부의 일부 영역을 통해서 에칭되며 하우징 몸체(4)의 후면 외곽선을 따라서 기판(1)을 아주 가볍게 에칭하는 것이다. 이 방식으로, 예를 들어, 브래이킹에 의해 주석 도금한 후에, 최종 장착된 반도체 소자(10)를 이렇게 형성된 브래이킹 점을 따라 개별화하기 위해 하우징 몸체(4)의 후면 외곽선을 따라 형성된 브래이킹 점이 제공된다.A third method of selection is to etch through the partial region of the lower part of the housing body 4 between the rear terminal portions 5.1 and 5.2 and very lightly etch the substrate 1 along the back outline of the housing body 4. In this way, after tinning, for example by breaking, the bar formed along the rear outline of the housing body 4 for individualizing the finally mounted semiconductor element 10 along the thus formed breaking point. A racking point is provided.

기술된 모든 선택 방법에 있어서, 기판을 통한 광 에칭 및 에칭은 기본적으로 주석 도금 후에 발생할 수 있다.For all the described selection methods, the photoetch and etch through the substrate can occur essentially after tin plating.

본 발명에 따른 방법에 의해 구성된 여러개의 발광 반도체 소자(10)는 도 2에서 도시된다. 이 경우에, 단일 공동은 하우징 몸체(4)를 형성하기 위해 사용되었다. 몰딩 물질은, 몰딩으로부터 제거된 후에 다소 두꺼운 브리지(9)가 이미 형성된 유니트에 존재하도록 몰딩 다이(도시되지 않음)의 공급 파이프를 통해서 압축되며, 이 유니트는 여러개의 링크된 반도체 소자(10) 및 브리지(6), 및 하우징 몸체(4) 사이의 전술한 브리지(6)로 구성된다.Several light emitting semiconductor elements 10 constructed by the method according to the invention are shown in FIG. 2. In this case, a single cavity was used to form the housing body 4. The molding material is compressed through a supply pipe of a molding die (not shown) so that a rather thick bridge 9 is present in the unit already formed after it is removed from the molding, the unit being connected to several linked semiconductor elements 10 and Bridge 6 and the aforementioned bridge 6 between the housing body 4.

연속적인 제조 단계에서 형성된 반도체 소자(10)를 쉽게 다루기 위해서는, 여러개의 링크된 반도체 소자(10) 및 브리지(6)로 구성된 제조된 유니트의 각 단부의 좌측에 스프루(sprue : 7.1, 7.2)가 위치하는 것이 바람직하다. 부정확하게 다루어지는 것을 방지하기 위해서는, 한 측면상에 배치된 모든 스프루(7.2)가 처리를 용이하게 하는 작은 리세스(recess)(7.3) 또는 다른 특별한 형태를 가지는 것이 바람직하다.In order to easily handle the semiconductor device 10 formed in successive fabrication steps, sprues are formed on the left side of each end of the fabricated unit consisting of several linked semiconductor devices 10 and bridges 6. Is preferably located. In order to prevent incorrect handling, it is desirable that all sprues 7.2 placed on one side have a small recess 7.3 or other special shape to facilitate processing.

초기에는 제거되지 않은 스프루(7.1, 7.2)에 의해서, 제조된 유니트는 반도체 소자(10)가 접촉되며 그 결과로 손상되는 일이 없이, 몰딩된 후에 예를 들어 다이에서 분리될 수 있다. 또한, 제조된 유니트는 기판(1)으로부터 분리될 때 이 스프루(7.1, 7.2)에 고정되어, 전기 단자(5)(도 3)를 주석 도금하기 위한 갈바니 용기에 담궈질 수 있다.By means of sprues 7.1 and 7.2 that are not initially removed, the fabricated unit can be separated off, for example, from the die after molding, without the semiconductor element 10 being in contact and as a result of being damaged. Furthermore, the manufactured unit can be fixed to these sprues 7.1 and 7.2 when separated from the substrate 1 and soaked in a galvanic container for tin plating the electrical terminal 5 (FIG. 3).

도 3은 본 발명에 따른 방법에 의해 제조되며 전기 단자(5)를 주석 도금하기 위한 갈바니 공정 전에 브리지(6)에 의해 연속해서 연결된 3개의 발광 반도체 소자(10)를 도시한다. 각각의 반도체 소자(10)는 반도체 몸체(2)(도시되지 않음)와 이격 위치하며, 투명한 하우징 몸체(4) 및 애노드(5.1)와 캐소드(5.2)로 구성된 전기 단자(5)를 가진다. 갈바니 공정에서, 브리지(6)에 의해 연결된 반도체 소자(10)가 주석 도금되며, 즉 상기 소자는 구리 합금으로 구성된 단자(5)가 주석 용기에 완전히 담궈질 때까지 액체 주석 용기의 전기 단자가 낮추어진다.FIG. 3 shows three light emitting semiconductor elements 10 manufactured by the method according to the invention and connected in series by a bridge 6 before the galvanic process for tin plating the electrical terminals 5. Each semiconductor element 10 is spaced apart from the semiconductor body 2 (not shown) and has a transparent housing body 4 and an electrical terminal 5 consisting of an anode 5.1 and a cathode 5.2. In the galvanic process, the semiconductor element 10 connected by the bridge 6 is tinned, i.e., the element is lowered by the electrical terminal of the liquid tin container until the terminal 5 made of copper alloy is completely immersed in the tin container. Lose.

주석 용기로부터 연속해서 연결된 반도체 소자(10)를 빼낸 후에, 단자(5)는 산화작용으로부터 보호되도록 주석 층으로 코팅된다. 전기 단자(5)가 주석 도금된 후에, 브리지(6)는 예를 들어, 소잉, 커팅, 스탬핑 또는 브래이킹을 통해 제거되며, 따라서 반도체 소자(10)는 개체로 존재한다.After withdrawing the semiconductor elements 10 connected in series from the tin container, the terminals 5 are coated with a layer of tin to protect them from oxidation. After the electrical terminal 5 is tinned, the bridge 6 is removed, for example by sawing, cutting, stamping or breaking, so that the semiconductor element 10 is present as an object.

갈바니 공정을 통한 전기 단자(5)의 주석 도금은 하부측(1.2)을 형성하기 전 또는 형성한 후, 반도체 소자(10)의 개체화 전 또는 후, 또는 브리지(6)에 의해 연결된 여러 개의 반도체 소자(10)가 기판(1)과 분리된 후에도 발생할 수 있다.The tin plating of the electrical terminal 5 through the galvanic process may be performed before or after forming the lower side 1.2, before or after the individualization of the semiconductor element 10, or several semiconductor elements connected by the bridge 6. It may also occur after the 10 is separated from the substrate 1.

도 4는 본 발명에 따른 방법에 의해 구성된 단자부(5.1 : 애노드, 5.2 : 캐소드)를 가진 개체의 발광 반도체 소자(10)의 하부측을 도시하며, 여기서 이전에 분리된 브리지(6)의 나머지 부분(6.1)이 도시된다. 최종 반도체 소자(10)의 하부측은 더 이상 존재하지 않는 기판(1)의 하부측(1.2)과 동일하다. 반도체 칩(2)(도시되지 않음)이 비교적 대형의 전기 단자(5.2)에 직접 연결되기 때문에, 반도체 칩(2)에서 발생한 열은 별 어려움 없이 제거될 수 있다.4 shows the lower side of the light emitting semiconductor element 10 of an object having a terminal portion (5.1: anode, 5.2: cathode) constructed by the method according to the invention, where the remaining part of the previously separated bridge 6 (6.1) is shown. The bottom side of the final semiconductor device 10 is the same as the bottom side 1.2 of the substrate 1 which no longer exists. Since the semiconductor chip 2 (not shown) is directly connected to the relatively large electric terminal 5.2, the heat generated in the semiconductor chip 2 can be removed without difficulty.

도 5a는 전기 단자(5.1, 5.2), 반도체 칩(2), 결합 배선(3.1), 및 투명한 하우징 몸체(4)를 가지는 소형-SMD 발광 다이오드의 형태로, 본 발명에 따른 방법에 의해 구성된 반도체 소자(10)의 사시도이다. 반도체 소자(10)의 외부 치수는 폭이 약 0.8mm, 길이가 약 1.7mm, 높이가 약 0.6mm이다.5a shows a semiconductor constructed by the method according to the invention in the form of a small-SMD light emitting diode having electrical terminals 5.1, 5.2, a semiconductor chip 2, a coupling wiring 3.1, and a transparent housing body 4. A perspective view of the element 10. The external dimensions of the semiconductor device 10 are about 0.8 mm wide, about 1.7 mm long, and about 0.6 mm high.

도 5b에서, 반도체 소자(10)에 대한 상세한 치수가 도시된다. 이 도면에서, 각각의 전기 단자(5.1, 5.2)의 폭은 0.7mm이고, 각 단자 사이의 거리는 0.3mm이다. 발광 LED 칩의 경우에, 반도체 칩(2)은 약 0.3mm×0.3mm×0.25mm의 치수의 거의 입방형태를 가진다.In FIG. 5B, the detailed dimensions for the semiconductor device 10 are shown. In this figure, the width of each electrical terminal 5.1, 5.2 is 0.7 mm, and the distance between each terminal is 0.3 mm. In the case of a light emitting LED chip, the semiconductor chip 2 has an almost cubic shape with dimensions of about 0.3 mm x 0.3 mm x 0.25 mm.

결합 배선(3.1)이 곡선이 아니고 반도체 칩(2)과 애노드(5.1) 사이에서 거의 직각으로 굽어질 때, 더 작은 치수가 얻어진다. 이것은 약 50μm까지 반도체 소자의 높이를 감소시킨다. 애노드(5.1)가 짧아지고 캐소드(5.2)에 이르는 거리가 감소되면 1.7mm의 반도체 소자(10)의 길이는 적어도 0.5mm까지 짧아질 수 있다. 따라서 짧아진 애노드(5.1)는 캐소드(5.2)와 쉽게 구별될 수 있다.When the interconnection wiring 3.1 is not curved and is bent almost perpendicularly between the semiconductor chip 2 and the anode 5.1, smaller dimensions are obtained. This reduces the height of the semiconductor device by about 50 μm. If the anode 5.1 is shortened and the distance to the cathode 5.2 is reduced, the length of the semiconductor device 10 of 1.7 mm can be shortened to at least 0.5 mm. The shortened anode 5. 1 can thus be easily distinguished from the cathode 5. 2.

도 5c-e는 하우징 몸체(4) 내에 집적된 광학 커플링 및 디커플링 소자를 가진 본 발명에 따른 방법에 의해 구성된 여러 개의 반도체 소자(10)의 사시도이다. 도 5c는 하우징 몸체(4) 내에 집적된 구면 또는 비구면 렌즈(18)를 가진 반도체 소자(10)를 도시한다. 저가로 제조될 수 있으며 반도체 소자(10)의 하우징 몸체(4) 내에 집적된 원통형 렌즈(19)가 도 5d에 도시된다. 도 5e에서는 개구(21)를 가진리셉터클(20)이 도시된다. 개구(21)의 용도는 예를 들어, 개구(21) 내에 광섬유를 삽입함으로써 광섬유를 커플링하는 것이다. 발광 다이오드 분야에서 공지된 바와 같이 다른 렌즈 형태 및 광학 커플링 소자가 어려움 없이 구성될 수 있다.5C-E are perspective views of several semiconductor elements 10 constructed by the method according to the invention with optical coupling and decoupling elements integrated in the housing body 4. FIG. 5C shows the semiconductor device 10 with a spherical or aspherical lens 18 integrated in the housing body 4. The cylindrical lens 19, which can be manufactured at low cost and integrated into the housing body 4 of the semiconductor element 10, is shown in FIG. 5D. In FIG. 5E, the receptacle 20 with the opening 21 is shown. The use of the opening 21 is to couple the optical fiber, for example by inserting the optical fiber into the opening 21. Other lens shapes and optical coupling elements can be configured without difficulty as is known in the light emitting diode art.

도 6은 기판 상에 행으로 장착된 예시적인 발광 반도체 소자(10)를 이용하지만, 이 경우에는 긴 금속 캐리어 스트립(11)의 형태인 본 발명에 다른 제 2 제조 방법의 여러 공정 단계를 도시하는 사시도이다.FIG. 6 uses exemplary light emitting semiconductor elements 10 mounted in rows on a substrate, but in this case illustrates the various process steps of a second manufacturing method according to the invention in the form of an elongated metal carrier strip 11. Perspective view.

본 발명에 따른 제 1 제조 방법에 있어서, 대부분의 경우에 기판(11) 상에 장착되는 모든 반도체 소자(10) 상에서 임의의 시간에 하나의 특정 공정 단계(가령, 배치, 결합, 몰딩)만이 수행된다. 그러나, 특별 설계된 제조 장비에 있어서, 예를 들어, 배선 결합 후에, 반도체 칩(2)이 즉시 부착되는 등의 다양한 공정 단계가 연속해서 수행될 수 있다.In the first manufacturing method according to the invention, in most cases only one particular process step (eg, placement, bonding, molding) is performed at any time on all semiconductor elements 10 mounted on the substrate 11. do. However, in the specially designed manufacturing equipment, for example, various process steps such as the semiconductor chip 2 is immediately attached after the wiring bonding can be performed continuously.

예를 들어, 도 6에 따르면 반도체 칩(2)은 각 경우에 적절하게 설계된 반도체 칩(2)의 후면 접촉부와 도전 부착 방법, 땜납 방법 또는 열적 칩 결합 방법에 의해 제 1 워크 스테이션에서 특정 시간에 캐리어 스트립(11)의 상부측에 결합된다. 이 동작 후에, 반도체 칩(2)의 전면 접촉부는 결합 배선(3.1)에 의해 캐리어 스트립(11) 표면의 제 2 워크 스테이션(13) 상에 연결된 후에, 제 3 워크 스테이션(14)에서 반도체 칩(2)은 브리지(6)가 형성될 때, 투명한 열가소성 물질의 하우징 몸체(4) 내에 결합 배선(3.1)과 함께 밀봉되며; 그 다음으로 캐리어 스트립(11)의 하부측은 제 4 워크 스테이션(15)에서 형성되며, 최종적으로 반도체 소자(10)의 전기 단자(5)는 제 5 워크 스테이션(16)에서 주석 도금된다.For example, according to FIG. 6, the semiconductor chip 2 is provided at a specific time at the first workstation by the back contact of the semiconductor chip 2 and the conductive attachment method, the solder method or the thermal chip bonding method, which are suitably designed in each case. It is coupled to the upper side of the carrier strip 11. After this operation, the front contact of the semiconductor chip 2 is connected on the second workstation 13 on the surface of the carrier strip 11 by the coupling wiring 3.1, and then at the third workstation 14, the semiconductor chip ( 2) is sealed with the coupling wires 3.1 in the housing body 4 of the transparent thermoplastic material when the bridge 6 is formed; The lower side of the carrier strip 11 is then formed at the fourth workstation 15, and finally the electrical terminal 5 of the semiconductor element 10 is tin plated at the fifth workstation 16.

추가의 워크 스테이션에서, 거의 완성된 반도체 소자(10)는 테스트 프로브(17)에 의해 적절한 기능을 수행하는지에 대해 테스팅 되며 브리지(6)가 제거된다. 세정 공정 및 패키징 공정과 같은 여러 공정 단계가 이어질 수 있다.In a further workstation, the almost completed semiconductor device 10 is tested by the test probe 17 for proper functioning and the bridge 6 is removed. Several process steps can be followed, such as a cleaning process and a packaging process.

발광 반도체 소자(소형-SMD 발광 다이오드)의 2 가지 예를 통해 기술된 방법은 또한 다색의 발광 다이오드, 다이오드, 트랜지스터 및 집적 회로와 같은 다른 표면에 장착된 초소형의 전자 반도체 소자의 제조에 적합하다. 여러 경우에, 불투명한 몰딩 물질을 사용하는 것이 바람직하다. 반도체 소자가 다색의 발광 다이오드, 트랜지스터, 특히 집적 회로의 경우에, 2개 이상의 전기 단자를 필요로 하면, 기판(캐리어 보드 또는 캐리어 스트립)의 구조도 따라서 적용되야 한다; 그러나, 경험있는 전문가에게 있어서, 이것은 전혀 문제가 되지 않는다. 처음에 언급된 제조 방법의 장점은 이런 종류의 변형 예에서도 전부 적용될 수 있다.The method described through two examples of light emitting semiconductor devices (small-SMD light emitting diodes) is also suitable for the manufacture of microelectronic semiconductor devices mounted on other surfaces such as multicolored light emitting diodes, diodes, transistors and integrated circuits. In many cases, it is desirable to use opaque molding materials. If a semiconductor device requires two or more electrical terminals in the case of multicolored light emitting diodes, transistors, in particular integrated circuits, the structure of the substrate (carrier board or carrier strip) must also be applied accordingly; However, for experienced professionals, this is not a problem at all. The advantages of the manufacturing method mentioned at the outset can all be applied to this kind of variant.

본 발명은 본 발명의 제조 방법을 통해서 전자 반도체 소자를 소형, 저비용 및 단순한 방식으로 대량 생산할 수 있는 효과를 가진다.The present invention has the effect of mass production of electronic semiconductor devices in a compact, low cost and simple manner through the manufacturing method of the present invention.

Claims (27)

표면 장착용 전자 반도체 소자(10)의 제조 방법에 있어서,In the manufacturing method of the surface mounting electronic semiconductor element 10, a) 도전성 기판(1; 11)을 준비하는 단계;a) preparing a conductive substrate (1; 11); b) 상기 기판(1; 11)의 제 1 표면측(1.1)에 반도체 칩(2)을 부착시키는 단계;b) attaching a semiconductor chip (2) to a first surface side (1.1) of said substrate (1; 11); c) 상기 반도체 칩(2)에서 상기 기판(1; 11)의 상기 제 1 표면측(1.1)까지 전기 접속부(3.1, 3.2)를 형성하는 단계;c) forming electrical connections (3.1, 3.2) on the semiconductor chip (2) from the semiconductor chip (2) to the first surface side (1.1) of the substrate (1; 11); d) 상기 반도체 몸체(2)와 상기 전기 접속부(3.1, 3.2)를 절연 물질로 밀봉하여 하우징 몸체(4)를 형성하는 단계;d) sealing the semiconductor body (2) and the electrical connections (3.1, 3.2) with an insulating material to form a housing body (4); e) 상기 제 1 표면측에 대향되는 제 2 측(1.2)과 상기 기판을 분리함으로써 전기적으로 서로 절연되는 단자부(5, 5.1, 5.2)를 형성하는 단계를 포함하는 것을 특징으로 하는 방법.e) forming a terminal portion (5, 5.1, 5.2) which is electrically insulated from each other by separating the substrate and the second side (1.2) opposite the first surface side. 제 1항에 있어서,The method of claim 1, 제 1 전기 접속부(3.2)는 도전성 접착제에 의해 상기 반도체 몸체(2)의 제 1 접촉부와 상기 제 1 표면측(1.1) 사이에 형성되는 것을 특징으로 하는 방법.The first electrical connection (3.2) is formed by a conductive adhesive between the first contact of the semiconductor body (2) and the first surface side (1.1). 제 1항에 있어서,The method of claim 1, 상기 제 1 전기 접속부(3.2)는 땜납에 의해 상기 반도체 몸체(2)의 제 1 접촉부와 상기 제 1 표면측(1.1) 사이에 형성되는 것을 특징으로 하는 방법.The first electrical connection (3.2) is characterized in that it is formed between the first contact of the semiconductor body (2) and the first surface side (1.1) by soldering. 제 1항에 있어서,The method of claim 1, 상기 제 1 전기 접속부(3.2)는 열적 칩 결합에 의해 상기 반도체 몸체(2)의 제 1 접촉부와 상기 제 1 표면측(1.1) 사이에 형성되는 것을 특징으로 하는 방법.The first electrical connection (3.2) is characterized in that it is formed between the first contact and the first surface side (1.1) of the semiconductor body (2) by thermal chip bonding. 제 1 내지 제 4항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 4, 제 2 전기 접속부(3.1)는 결합 배선에 의해 상기 반도체 몸체(2)의 제 2 접촉부와 상기 제 1 표면측(1.1) 사이에 형성되는 것을 특징으로 하는 방법.A second electrical connection (3.1) is formed between the second contacting part of the semiconductor body (2) and the first surface side (1.1) by means of coupling wiring. 제 1 내지 제 4항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 4, 상기 하우징 몸체(4)는 몰딩 공정에 의해 제조되는 것을 특징으로 하는 방법.The housing body (4) is characterized in that it is produced by a molding process. 제 1 내지 제 4항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 4, 상기 절연 물질은 열가소성 물질인 것을 특징으로 하는 방법.The insulating material is a thermoplastic. 제 1 내지 제 4항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 4, 여러 개의 반도체 몸체(2)가 상기 기판(1; 11) 상에 부착되는 것을 특징으로 하는 방법.A method, characterized in that several semiconductor bodies (2) are attached on the substrate (1; 11). 제 8항에 있어서,The method of claim 8, 상기 반도체 몸체(2)가 상기 기판(1; 11) 상에 규칙적으로 배치되는 것을 특징으로 하는 방법.The semiconductor body (2) is characterized in that it is regularly arranged on the substrate (1; 11). 제 8항에 있어서,The method of claim 8, 상기 반도체 몸체(2)가 상기 기판(1; 11) 상에 행으로 배치되는 것을 특징으로 하는 방법.The semiconductor body (2) is arranged in rows on the substrate (1; 11). 제 8항에 있어서,The method of claim 8, 상기 반도체 몸체(2)가 상기 기판(1; 11) 상에 행 및 열로 배치되는 것을 특징으로 하는 방법.The semiconductor body (2) is arranged in rows and columns on the substrate (1; 11). 제 1 내지 제 4항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 4, 상기 기판(1; 11) 상에 부착된 상기 각각의 반도체 몸체(2)마다 그 하우징 몸체(4)가 제공되는 것을 특징으로 하는 방법.The housing body (4) is provided for each of said semiconductor bodies (2) attached on said substrate (1; 11). 제 1 내지 제 4항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 4, 상기 전체의 반도체 몸체(2)의 하우징 몸체(4)가 동시에 구성되는 것을 특징으로 하는 방법.The housing body (4) of the whole semiconductor body (2) is configured simultaneously. 제 10항에 있어서,The method of claim 10, 행 또는 열로 배열된 상기 모든 반도체 소자(10)의 하우징 몸체(4)는 상기 하우징 몸체(4)가 형성된 후에 브리지(6)에 의해서 연결되는 것을 특징으로 하는 방법.The housing bodies (4) of all the semiconductor elements (10) arranged in rows or columns are connected by a bridge (6) after the housing bodies (4) are formed. 제 14항에 있어서,The method of claim 14, 스프루(7.1, 7.2)는 브리지(6)에 의해 연결된 상기 반도체 소자(10)의 각 단부에 위치하는 것을 특징으로 하는 방법.A sprue (7.1, 7.2) is characterized in that it is located at each end of the semiconductor element (10) connected by a bridge (6). 제 1 내지 제 4항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 4, 상기 단자부(5, 5.1, 5.2)를 형성할 때, 상기 기판(1; 11)은 상기 하우징 몸체(4) 하부의 일부 영역에서 분리되며 상기 하우징 몸체(4)의 윤곽을 따라 분리되는 것을 특징으로 하는 방법.When forming the terminal portions 5, 5.1, and 5.2, the substrates 1 and 11 are separated in a portion of the lower portion of the housing body 4 and are separated along the contour of the housing body 4. How to. 제 1 내지 제 4항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 4, 상기 단자부(5, 5.1, 5.2)를 형성할 때, 상기 기판(1; 11)은 상기 하우징 몸체(4) 하부의 일부 영역에서 분리되며 형성된 브래이킹 점은 상기 하우징 몸체(4)의 윤곽을 따라 형성되는 것을 특징으로 하는 방법.When forming the terminal portions 5, 5.1, and 5.2, the substrates 1 and 11 are separated in some areas below the housing body 4, and the breaking points formed form the contour of the housing body 4. Formed according to the method. 제 17항에 있어서,The method of claim 17, 상기 기판(1; 11)은 상기 반도체 소자(10)를 개체화하기 위해 상기 형성된 브래이킹 점을 따라 브래이킹되는 것을 특징으로 하는 방법.The substrate (1; 11) is cracked along the formed breaking point for individualizing the semiconductor element (10). 제 16항에 있어서,The method of claim 16, 상기 기판(1; 11)은 포토리소그라피에 의해 마스킹되는 것을 특징으로 하는 방법.The substrate (1; 11) is characterized in that it is masked by photolithography. 제 1 내지 제 4항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 4, 상기 기판(1; 11)의 분리 공정은 레이저로 수행되는 것을 특징으로 하는 방법.The method of separating said substrate (1; 11) is carried out with a laser. 제 1 내지 제 4항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 4, 상기 기판(1; 11)의 분리 공정은 커팅, 쉬어링, 스탬핑 또는 소잉에 의해 수행되는 것을 특징으로 하는 방법.The separation process of the substrate (1; 11) is characterized in that it is carried out by cutting, shearing, stamping or sawing. 제 1 내지 제 4항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 4, 금속 캐리어 보드는 기판(1; 11)으로서 사용되는 것을 특징으로 하는 방법.Metal carrier board is used as substrate (1; 11). 제 1 내지 제 4항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 4, 긴 금속 캐리어 스트립은 기판(1; 11)으로서 사용되는 것을 특징으로 하는 방법.A long metal carrier strip is used as substrate (1; 11). 제 1 내지 제 4항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 4, 상기 기판(1; 11)은 구리 합금으로 이루어지는 것을 특징으로 하는 방법.The substrate (1; 11) is characterized in that the copper alloy. 제 24항에 있어서,The method of claim 24, 상기 단자부(5, 5.1, 5.2)는 주석 도금되는 것을 특징으로 하는 방법.And the terminal portion (5, 5.1, 5.2) is tin plated. 발광 반도체 소자(10)를 제조하기 위해 제 1 내지 제 4항 중 어느 한 항에 따른 방법을 사용하는 방법.A method using the method according to any one of claims 1 to 4 for manufacturing a light emitting semiconductor device (10). 제 1 내지 제 4항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 4, 다이오드, 트랜지스터 및 집적 회로와 같은 능동 및 수동 반도체 소자를 제조하는 방법.A method of manufacturing active and passive semiconductor devices such as diodes, transistors and integrated circuits.
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JP3455685B2 (en) * 1998-11-05 2003-10-14 新光電気工業株式会社 Method for manufacturing semiconductor device

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