DE10128271C1 - Diode manufacturing method uses shaker with reception openings for alignment of diode chips before adhering to lower conductor layers provided by base plate - Google Patents

Diode manufacturing method uses shaker with reception openings for alignment of diode chips before adhering to lower conductor layers provided by base plate

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Publication number
DE10128271C1
DE10128271C1 DE2001128271 DE10128271A DE10128271C1 DE 10128271 C1 DE10128271 C1 DE 10128271C1 DE 2001128271 DE2001128271 DE 2001128271 DE 10128271 A DE10128271 A DE 10128271A DE 10128271 C1 DE10128271 C1 DE 10128271C1
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Germany
Prior art keywords
diodes
chips
conductor layer
base plate
producing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE2001128271
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German (de)
Inventor
Ching-Chang Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CROWNPO TECHNOLOGY INC., TAIPEI, TW
Original Assignee
LIZ ELECTRONICS CORP
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Priority to DE2001128271 priority Critical patent/DE10128271C1/en
Application granted granted Critical
Publication of DE10128271C1 publication Critical patent/DE10128271C1/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49562Geometry of the lead-frame for devices being provided for in H01L29/00
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • HELECTRICITY
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • HELECTRICITY
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
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    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312Aligning
    • H01L2224/83136Aligning involving guiding structures, e.g. spacers or supporting members
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/9512Aligning the plurality of semiconductor or solid-state bodies
    • H01L2224/95121Active alignment, i.e. by apparatus steering
    • H01L2224/95122Active alignment, i.e. by apparatus steering by applying vibration
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01068Erbium [Er]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor
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    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

Abstract

The invention relates to a method for producing diodes. It comprises cutting notches (11) in the base plate structure (1) to form hundreds of units, forming a lower conductor layer (2) on each unit of the base plate structure (1), printing resistors (3) and gluing the Chips (5) on the base plate structure (1) and coating the base plate structure (1) with cover materials (7). After processing, the protrusion (54) is exposed at the chip tip and then printed or plated with the upper conductor layer (6). to connect it to the boundary of each unit. The base plate (1) is separated into elongated rectangular blocks (12). In addition, connection points (8) are formed on the side. After the etching, the base plate (1) is automatically broken into individual chips (5). The solder metals are glued to the surface of the connection points (8), whereupon the electrical detection and packaging are carried out.

Description

The invention relates to the field of diode production and in particular a process for the mass production of flat diodes with lower Costs than before.

As is known, the current packing of low-power diodes for surface mounting takes place essentially in the form of a column, that is to say, by packing the column diodes. However, this packaging method has several disadvantages:

  • 1. During the manufacturing process that involves mechanical gripping, Placing, gluing and soldering includes the column packing arrangement Difficult to operate, the yield low and the masses production is slow.
  • 2. In addition, a coefficient of thermal expansion affects the package the column diodes; in other words, there is no adjustment between the packing of the column diodes and the thermal expansion coefficient efficient of the circuit base plate. If the diodes on the scarf circuit boards are soldered, either the components tend slightly to break, or the circuit breaks because of the bad Heat conduction broken. The result is the reliability of the products bad.

A method for producing diodes is known from US 55 50 086, being hundreds or thousands of units on a plate-like ceramic body are formed on the thick film technique generated lower conductor layers, attached diodes and these with Cover materials are coated, the upper electrode surfaces remain free to apply top conductor layers and this Coating the arrangement with an insulating protective putty.  

The US 36 91 628 treats manufactured using thin or thick film technology coplanar connection technology for the assembly of semiconductor diodes. A covering material is first applied there and a diode is inserted there placed. If cover material forms on the diode, US Pat. No. 3,691,628 mentions that to expose the top pad of the diodes Grinding may be necessary.

From US 60 54 371 it is known to use asymmetrical components to process, the use of funnel-shaped, stepped holes for Includes the components, and the components recesses have, which allow the components in the holes of benefit orientate. However, high-precision placement devices are required for this.

From the publication DE 18 05 174 A is a method for applying Individual bodies on a base body by means of a Postponement shaker known. This consists of a document with fan-shaped depressions. There will be a large number on this document of components applied indiscriminately and by shaking into the wells promoted.

The object of the invention is therefore to provide a method that a Automated process allows the chips to go in the same direction are aligned and thus glued to the lower conductive layer can.

According to the invention, the object is achieved by a method according to the main claim, which comprises the following steps:

  • a) providing a plurality of chips ( 5 ), each of these chips ( 5 ) having a projection ( 54 ) on the top, and providing a base plate ( 1 ) with notches ( 11 ) between receiving locations for hundreds of units;
  • b) forming a lower conductor layer ( 2 ) on each unit;
  • c) placing a plurality of chips ( 5 ) on a plane shaker ( 9 ) having a plurality of funnel-shaped, stepped holes ( 91 );
  • d) operating this plan displacement shaker ( 9 ) at a specific frequency in order to achieve a migration of the chips ( 5 ) into the holes ( 91 ) of the shaker ( 9 ), the chips ( 5 ) occupying the holes ( 91 ) in such a way that the top with the projection ( 54 ) is directed downward and the bottom ( 52 ) protrudes from the holes ( 91 );
  • e) gluing the undersides ( 52 ) of the chips ( 5 ) to the lower conductor layer ( 2 ) on the base plate ( 1 );
  • f) coating the base plate ( 1 ), lower conductor layer ( 2 ), the chips ( 5 ) and their projections ( 54 ) with a cover material ( 53 );
  • g) exposing the protrusions ( 54 ) at the tip of the chips ( 5 );
  • h) forming an upper conductor layer ( 6 ) in connection with the protrusion ( 54 ) of each chip tip;
  • i) Finishing by coating with protective cement ( 7 ), designating the poles of the diodes, forming connection points ( 8 ) and separating them into individual diodes.

With the features specified in the subclaims is another Improvement of the method characterized in claim 1 possible.

Further features and advantages of the invention will become clear when reading the following description of preferred embodiments based on the Drawing reference; show it:

Fig. 1 is a flowchart of a method according to the invention;

Fig. 2 is a cross-sectional view of a ceramic base plate with Schnittker ben;

Fig. 3 is a perspective view of a base plate of Figure 2 with cut notches.

Fig. 4 to the lower conductor layer to form a cross-sectional view of units that have been printed with conductive paste or plated;

Fig. 5 is a top view of the units of Fig. 4 printed or plated with conductive paste to form the lower conductor layer;

Fig. 6 is a cross-sectional view of a printed or plated resistance between the conductors on the base plate;

Fig. 7 is a top view of the printed or plated resistor of Fig. 6 between the conductors on the base plate;

Fig. 8 is a cross sectional view of the printed material on the protection resistance;

Fig. 9 is a top view of the printed protective material of Fig. 8 on the resistor;

FIG. 10 is a cross-sectional view of a resistor with a resistance value corrected by means of laser;

FIG. 11 is a top view of the resistance with a laser corrected resistance value from FIG. 10;

FIG. 12 is a cross-sectional view of bonding to the chip with conductive paste;

FIG. 13 shows a top view of the method step from FIG. 12; FIG.

FIG. 14 is a cross-sectional view of the coating of the chip with Schutzkitt;

Figure 15 is a plan view of the coating of the chip with Schutzkitt of Fig. 14.;

FIG. 16 is a cross-sectional view of a step of exposing the electric to;

Figure 17 is a top plan view of the step of exposing the electrodes of Figure 16;

Figure 18 is a cross-sectional view of the printed or plated conductors on the protrusion of the diode tips. At this point, an upper conductor layer is formed which connects the diodes to the boundary of each unit;

Fig. 19 is a plan view of the printed or plated conductor on the jump before the diode tips. At this point, an upper conductor layer is formed which connects the diodes to the boundary of each unit;

FIG. 20 is a cross-sectional view of coating the top diode with an insulating Schutzkitt;

Fig. 21 is a top view of the coating step shown in Fig. 20;

Fig. 22 is a cross-sectional view of the pole labels and the printed words of a diode;

Fig. 23 is a top view of the pole labels and the printed words of the diode of Fig. 22;

Fig. 24 is a perspective view of the entire base plate separated into elongated rectangular blocks;

Fig. 25 is a plan view of the entire base plate separated into elongated rectangular blocks;

FIG. 26 is a cross sectional view of the conductive paste or the adhered on both sides of conductor to form a diode;

Fig. 27 is a plan view of the conductive paste or the adhered on both sides of conductor to form a diode;

FIG. 28 is a perspective view of the fractured in a single-chip base plate;

FIG. 29 is a plan view of the fractured in a single-chip base plate;

FIG. 30 is a cross-sectional view of the angekleb th at the surface of the diode solders;

FIG. 31 is a plan view of metals adhered on the surface of the diode soldering;

Fig. 32 is a view of a vibrator;

Fig. 33 is a view for demonstrating the effect of the vibrator;

Fig. 34 is a view for demonstrating the placement of a resistor under the diode;

FIG. 35 is a view of a single chip; and

Fig. 36 is a view of the die assembly components.

In Fig. 1 is a flow chart of the manufacturing method of the invention first is shown.

Step 1 : Create cut notches 11 in the form of inverted triangles on the ceramic base plate 1 to form hundreds of units. As shown in Figs. 2 and 3, these notches 11 are not only useful for breaking, but can also create more conductive residual areas when cutting.

Step 2 : Form the lower conductor layer 2 by printing or plating the conductive paste on the surface of each unit of the base plate 1 as shown in FIGS. 4 and 5.

Step 3 : Printing or plating the resistors 3 with an appropriate resistance value between the lower conductor layer 2 of each unit of the base plate 1 , as shown in FIGS. 6 and 7.

Step 4 : Coating the surface of the resistors 3 with protective cover materials 4 for protecting the resistors 3 and for use in laser modification in the next step, as shown in FIGS. 8 and 9.

Step 5 : If the resistance value of the printed resistors 3 does not meet expectations, correct the resistance with the laser to cut a gap 31 and decrease the resistance value of the resistors 3 as shown in FIGS. 10 and 11.

Step 6 : Glue an underside 52 of the chip 5 (such as diodes, LEDs, etc.) to the lower conductor layer 2 with the conductive paste (putty), as shown in FIGS . 12 and 13.

Step 7 : Cover with the cover materials 53 on the top to protect the chip 5 , as shown in FIGS. 14 and 15.

Step 8 : Expose the protrusion 54 on the tip of the chip 5 by polishing, by laser or by chemical etching, as shown in FIGS. 16 and 17.

Step 9 : Print or plate the conductors on the protrusion 54 of the tip of the chip 5 and connect to the boundary of each unit to form the upper conductor layer 6 as shown in Figs. 18 and 19.

Step 10 : Coating the surface with the insulating protective putty 7 , as shown in FIGS. 20 and 21.

Step 11 : Mark the poles and characters 71 on the surface of the protective cement 7 with ink or laser engraving, as shown in FIGS. 22 and 23.

Step 12 : Automatic separation of the base plate 1 using the brittleness and the cut notches 11 into elongated rectangular blocks 12 , as shown in FIGS. 24 and 25.

Step 13 : Glue the conductive paste or the conductors to the side of the blocks 12 and tabs to form the connection points 8 , as shown in FIGS . 26 and 27.

Step 14 : Automated separation of the diodes from the blocks 12 into a single chip 13 using the brittleness and the cut notches 11 of the base plate 1 , as shown in FIGS . 28 and 29.

Step 15 : Glue the solder metals 81 to the connection points 8 to protect the surface of the connection points against oxidation and to improve the solderability, as shown in FIGS. 30 and 31.

Step 16 : performing the electrical detection and packaging.

The correct adhesion of the lower conductor layer 2 to the underside 52 of the chips 5 takes place in step 6 in conjunction with a plan displacement shaker 9 shown in FIGS . 32 and 33, which has funnel-shaped, stepped, filled holes 91 . Here, the protrusion 54 of the chip 5 can be placed under the filled holes 91 , while the chip 5 itself is placed over these holes, creating a state in which the chip is reversed. That is, depending on the specific vibration frequency, the protrusion 54 of the tip of the chip 5 falling down moves faster than the bottom 52 of the chip 5 falling down. On the other hand, coat the underside 52 of the chip 5 on the filled holes 91 of the upwards moving Planverschiebungsrüttlers 9, and this is used to stick to the underside 52 of the chip 5 on the right upper part of the lower conductor layer. 2 The chip 5 with the protrusion 54 contains a main unit of the semiconductor and a metal protrusion, which is a kind of base material. In terms of shape, it forms a rectangular main body and a semicircular projection 54 . Based on the different physical properties of the material and the obvious size, the correct kinetic energy can be transferred by the vibrator 9 . Because of the various physical properties, the protrusion 54 of the chip 5 is located below while the chips 5 are moving forward and then entering the melter. At this time, all chips 5 in the melter are oriented in the same direction, so that the process of adhering the bottom of the chips to the lower conductor layer can be automated in this way.

The process according to DE 18 05 174 A is automated positioned and polarity-aligned arrangement of the individual body used a shake. There, however, the individual bodies are concerned just finished components that are transferred before being transferred a support body on a base only detachable in a lattice Pad must be positioned by the vibration and not by the to finally park a vibration on a substrate (base plate) Crisps.

In order to produce small and light products, the sixth step, as shown in FIG. 34, can be replaced by the following steps, in which the conductor 32 prints on the lower conductor layer 2 and on the protective materials 4 and the chip 5 on the conductors 32 is arranged.

If the resistors 3 do not need to be used, steps 3 to 5 , as shown in FIG. 35, can be omitted, with only a single chip 5 being present.

Fig. 36 is a diagram of the configuration of the die assembly. It shows the above-described omission of steps 3 to 5 of step 14 , in which the blocks 12 are cut into the chip matrix containing several units. In the base plate 1 folds 14 can be made beforehand in order to form the connection point on the side strip in step 13 . At the same time, the chip 5 of the units can contain resistors, capacitors or inductors in addition to the diode. Depending on the requirements, different combinations should accordingly be put together, the arrangement assembly unit being arranged with several chips.

It is evident from the above statements that the invention has the following advantages:

  • 1. It is the only process that is currently used for a large part of the Components of flat diodes can be manufactured.
  • 2. Manufacturing productivity is extremely high, with the end machine equipment can reach up to 200,000 diodes per hour can. The products are also extremely inexpensive.
  • 3. The construction of the invention and the manufacturing process are one Breakthrough in the area. With this invention, the competition ability of the industry to be ensured.
  • 4. The product has high reliability because of the chip connection point of the diodes is glued with conductive materials by the conventional use of non-glass for the contact point of the Diodes are different.
  • 5. The chips can be removed directly from the wafer with the machine and be glued to the base plate or all can Chips are placed with the vibrator on top.
  • 6. The invention can provide a combination of the arrangement in which Different chips can be packed at the same time for the chips around diodes, resistors, capacitors or induction spools can act. In this way, the expediency and increase  productivity, whereby more additional values can be generated.
  • 7. A solid chip and a resistor can be used during the same Manufacturing process to be integrated in the package.

Claims (18)

1. A method for producing diodes on a chip, each chip ( 5 ) having an upper side with a projection ( 54 ) as a tip and an underside ( 52 ), the method comprising the following steps:
  • a) providing a plurality of chips ( 5 ), each of these chips ( 5 ) having a projection ( 54 ) on the top, and providing a base plate ( 1 ) with notches ( 11 ) between receiving locations for hundreds of units;
  • b) forming a lower conductor layer ( 2 ) on each unit;
  • c) placing a plurality of chips ( 5 ) on a plane shaker ( 9 ) having a plurality of funnel-shaped, stepped holes ( 91 );
  • d) operating this plan displacement shaker ( 9 ) at a specific frequency in order to achieve a migration of the chips ( 5 ) into the holes ( 91 ) of the shaker ( 9 ), the chips ( 5 ) occupying the holes ( 91 ) in such a way that the top with the projection ( 54 ) is directed downward and the bottom ( 52 ) protrudes from the holes ( 91 );
  • e) gluing the undersides ( 52 ) of the chips ( 5 ) to the lower conductor layer ( 2 ) on the base plate ( 1 );
  • f) coating the base plate ( 1 ), lower conductor layer ( 2 ), the chips ( 5 ) and their projections ( 54 ) with a cover material ( 53 );
  • g) exposing the protrusions ( 54 ) at the tip of the chips ( 5 );
  • h) forming an upper conductor layer ( 6 ) in connection with the protrusion ( 54 ) of each chip tip;
  • i) Finishing by coating with protective cement ( 7 ), designating the poles of the diodes, forming connection points ( 8 ) and separating them into individual diodes.
2. A method for producing diodes according to claim 1, characterized in that each chip ( 5 ) is a light emitting diode.
3. A method for producing diodes according to claim 1 or 2, characterized in that the notches ( 11 ) of the base plate ( 1 ) are inverted triangles.
4. A method for producing diodes according to a preceding claim, characterized in that the lower conductor layer ( 2 ) is formed by printing the conductive paste.
5. A method for producing diodes according to one of claims 1 to 3, characterized in that the lower conductor layer ( 2 ) is formed by plating.
6. A method of producing diodes according to a preceding claim, characterized in that after the formation of the lower conductor layer ( 2 ) resistors ( 3 ) with a suitable resistance value are applied between the lower conductor layer ( 2 ) of each unit, an upper side each resistor ( 3 ) is coated with the insulating protective cement ( 7 ).
7. A method for producing diodes according to claim 6, characterized in that the resistors ( 3 ) are formed by printing.
8. A method for producing diodes according to claim 6, characterized in that the resistors ( 3 ) are formed by plating.
9. A method for producing diodes according to a preceding claim, characterized in that a laser for cutting a gap ( 31 ) is used to correct the resistance value of the resistors ( 3 ), which reduces the resistance values of the resistors ( 3 ).
10. A method for producing diodes according to a preceding claim, characterized in that the step of forming the lower conductor layer ( 2 ) is carried out by printing conductive paste.
11. A method for producing diodes according to a preceding claim, characterized in that the projection ( 54 ) is exposed at each chip tip by polishing, by means of a laser or by chemical etching.
12. A method for producing diodes according to a preceding claim, characterized in that the upper conductor layer ( 6 ) is formed by printing or plating the conductor on the projection ( 54 ) of each chip tip.
13. A method for producing diodes according to a preceding claim, characterized in that the step of designating the poles and the characters on the surface of the protective cement ( 7 ) is carried out with ink or laser engraving.
14. A method for producing diodes according to a preceding claim, characterized in that the step of separating into individual diodes comprises the production of blocks ( 12 ) with a plurality of diodes, conductive paste or conductor being glued to the side of the blocks ( 12 ) be glued to form connection points ( 8 ).
15. A method for producing diodes according to a preceding claim, characterized in that the step of forming connection points ( 8 ) takes place before arranging the chips ( 5 ) and before separating them into individual diodes.
16. A method for producing diodes according to claim 15, characterized characterized in that a chip arrangement further one or more contr levels and / or one or more capacitors and / or one or more contains more induction coils, the overall combination meeting the requirements is chosen accordingly to the chip arrangement.
17. A method for producing diodes according to a preceding claim, characterized in that after the step of separating into individual diodes, solder metals are applied to the surface of the connection points ( 8 ).
18. A method for producing diodes according to the preceding claim, characterized in that after the step of separating into individual diodes and after applying solder metals to the surface of the connection points ( 8 ), electrical detection and packaging takes place.
DE2001128271 2001-06-12 2001-06-12 Diode manufacturing method uses shaker with reception openings for alignment of diode chips before adhering to lower conductor layers provided by base plate Expired - Fee Related DE10128271C1 (en)

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US3691628A (en) * 1969-10-31 1972-09-19 Gen Electric Method of fabricating composite integrated circuits
DE19536216C1 (en) * 1995-09-28 1996-07-11 Siemens Ag Opto-electronic detector component for UV light
US5550086A (en) * 1995-12-27 1996-08-27 Tai; George Ceramic chip form semiconductor diode fabrication method
US6054371A (en) * 1997-09-29 2000-04-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device by detachably mounting substrates to a holder board
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US3691628A (en) * 1969-10-31 1972-09-19 Gen Electric Method of fabricating composite integrated circuits
DE19536216C1 (en) * 1995-09-28 1996-07-11 Siemens Ag Opto-electronic detector component for UV light
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DE102008030815A1 (en) * 2008-06-30 2009-12-31 Osram Opto Semiconductors Gmbh Method for producing a plurality of optoelectronic components
WO2010000224A2 (en) * 2008-06-30 2010-01-07 Osram Opto Semiconductors Gmbh Method for producing a plurality of optoelectronic components
WO2010000224A3 (en) * 2008-06-30 2010-03-04 Osram Opto Semiconductors Gmbh Method for producing a plurality of optoelectronic components
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