KR20010082830A - Method of Fabricating Thin Film Transistor - Google Patents

Method of Fabricating Thin Film Transistor Download PDF

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KR20010082830A
KR20010082830A KR1020000008306A KR20000008306A KR20010082830A KR 20010082830 A KR20010082830 A KR 20010082830A KR 1020000008306 A KR1020000008306 A KR 1020000008306A KR 20000008306 A KR20000008306 A KR 20000008306A KR 20010082830 A KR20010082830 A KR 20010082830A
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active layer
layer
thin film
film transistor
impurity region
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KR1020000008306A
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KR100724741B1 (en
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양준영
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구본준, 론 위라하디락사
엘지.필립스 엘시디 주식회사
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    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16H—GEARING
    • F16H3/00—Toothed gearings for conveying rotary motion with variable gear ratio or for reversing rotary motion
    • F16H3/44—Toothed gearings for conveying rotary motion with variable gear ratio or for reversing rotary motion using gears having orbital motion
    • F16H3/72—Toothed gearings for conveying rotary motion with variable gear ratio or for reversing rotary motion using gears having orbital motion with a secondary drive, e.g. regulating motor, in order to vary speed continuously
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16H—GEARING
    • F16H39/00—Rotary fluid gearing using pumps and motors of the volumetric type, i.e. passing a predetermined volume of fluid per revolution
    • F16H39/01—Pneumatic gearing; Gearing working with subatmospheric pressure
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16H—GEARING
    • F16H57/00—General details of gearing
    • F16H57/02—Gearboxes; Mounting gearing therein
    • F16H2057/02039—Gearboxes for particular applications
    • F16H2057/02043—Gearboxes for particular applications for vehicle transmissions

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE: A method for fabricating a thin film transistor is to simultaneously conduct an ion doping and an activation processes in the same equipment when forming an impurity region which is used as a source region and a drain region. CONSTITUTION: A buffer layer(33) is formed by depositing silicon nitride or silicon oxide on a transparent substrate(31). An active layer(35) is formed by depositing polysilicon or amorphous silicon on the buffer layer. The active layer is patterned by a photolithography to remain only on a predetermined part of the buffer layer. An insulating material layer such as silicon nitride or silicon oxide is deposited on the buffer layer to coat the active layer. A conductive metal layer such as Al or Cu is deposited on the insulating material layer. A gate insulting layer(37) and a gate electrode(39) are formed by patterning the conductive metal layer and the insulating material layer to remain only on the predetermined part of the active layer. A high-concentration impurity region(41) is formed by doping an N-type impurity ion into the exposed active layer.

Description

박막트랜지스터 제조방법{Method of Fabricating Thin Film Transistor}Method of Fabricating Thin Film Transistor

본 발명은 액정표시장치용 박막트랜지스터 제조방법에 관한 것으로서, 특히, 가열된 활성층에 불순물을 이온 도핑하여 소오스 및 드레인영역으로 이용되는 불순물영역을 형성할 수 있는 박막트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor for a liquid crystal display, and more particularly, to a method of manufacturing a thin film transistor capable of forming an impurity region used as a source and a drain region by ion doping impurities in a heated active layer.

도 1a 내지 도 1c는 종래 기술에 따른 박막트랜지스터 제조방법을 도시하는 공정도이다.1A to 1C are process diagrams showing a method of manufacturing a thin film transistor according to the prior art.

도 1a를 참조하면, 투명기판(11) 상에 질화실리콘 또는 산화실리콘 등의 절연물질을 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 증착하여 버퍼층(13)을 형성한다.Referring to FIG. 1A, an insulating material such as silicon nitride or silicon oxide is deposited on the transparent substrate 11 by chemical vapor deposition (hereinafter, referred to as CVD) to form a buffer layer 13.

버퍼층(13) 상에 다결정실리콘을 CVD 방법으로 증착하고 버퍼층(13)의 소정 부분에만 잔류하도록 포토리쏘그래피 방법으로 패터닝하여 활성층(15)을 형성한다.Polysilicon is deposited on the buffer layer 13 by CVD and patterned by photolithography so as to remain only in a predetermined portion of the buffer layer 13 to form the active layer 15.

도 1b를 참조하면, 버퍼층(13) 상에 활성층(15)을 덮도록 질화실리콘 또는 산화실리콘 등의 절연물질을 CVD 방법으로 증착한다. 그리고, 절연물질층 상에 알루미늄(Al) 또는 구리(Cu) 등의 도전성 금속을 스퍼터링 또는 CVD 방법으로 증착한다.Referring to FIG. 1B, an insulating material such as silicon nitride or silicon oxide is deposited on the buffer layer 13 by CVD to cover the active layer 15. A conductive metal such as aluminum (Al) or copper (Cu) is deposited on the insulating material layer by sputtering or CVD.

도전성 금속층 및 절연물질층을 활성층(15) 상의 소정 부분에만 잔류하도록 포토리쏘그래피 방법으로 패터닝하여 게이트절연막(17)과 게이트전극(19)을 형성한다.The gate insulating film 17 and the gate electrode 19 are formed by patterning the conductive metal layer and the insulating material layer by photolithography so as to remain only on predetermined portions on the active layer 15.

도 1c를 참조하면, 게이트전극(19)을 마스크로 사용하여 활성층(15)의 노출된 부분에 인(P) 또는 아세닉(As) 등의 N형 불순물을 고농도로 이온 도핑하여 이온주입영역(21)을 형성한다.Referring to FIG. 1C, by using the gate electrode 19 as a mask, an ion implantation region may be ion-doped with a high concentration of N-type impurities such as phosphorus (P) or asic (As) in the exposed portion of the active layer 15. 21).

도 1d를 참조하면, 상술한 구조에 레이저 빔을 조사하여 이온주입영역(21) 내에 이온 도핑된 불순물을 활성화하여 소오스 및 드레인영역으로 이용되는 고농도의 불순물영역(23)을 형성한다.Referring to FIG. 1D, the above-described structure is irradiated with a laser beam to activate the ion-doped impurities in the ion implantation region 21 to form a high concentration impurity region 23 used as a source and a drain region.

상술한 바와 같이 종래 기술에 따른 박막트랜지스터의 제조방법은 활성층에 불순물을 고농도로 이온 도핑한 후 레이저 빔을 조사하여 도핑된 불순물을 활성화시켜 소오스 및 드레인영역으로 이용되는 불순물영역을 형성한다.As described above, in the method of manufacturing a thin film transistor according to the related art, after ion doping impurities into the active layer at a high concentration, the doped impurities are activated by irradiating a laser beam to form impurity regions used as source and drain regions.

그러나, 불순물영역을 형성하기 위해 이온 도핑한 후 활성화하여야 하므로 공정이 복잡할 뿐만 아니라 별도의 장비가 필요하며, 또한, 활성화시 레이저 빔에 의해 게이트전극이 손상되는 문제점이 있었다.However, since the process must be activated after ion doping to form the impurity region, the process is not only complicated and requires separate equipment, and also has a problem that the gate electrode is damaged by the laser beam during activation.

따라서, 본 발명의 목적은 소오스 및 드레인영역으로 이용되는 불순물영역을 형성할 때 이온 도핑 및 활성화를 동일한 장비에서 동시에 실시할 수 있는 박막트랜지스터의 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a thin film transistor which can simultaneously perform ion doping and activation in the same equipment when forming impurity regions used as source and drain regions.

본 발명의 다른 목적은 게이트전극이 손상되는 것을 방지할 수 있는 박막트랜지스터의 제조방법을 제공함에 있다.Another object of the present invention is to provide a method of manufacturing a thin film transistor which can prevent the gate electrode from being damaged.

도 1a 내지 도 1d는 종래 기술에 따른 박막트랜지스터 제조방법을 도시하는 공정도1A to 1D are process diagrams showing a method of manufacturing a thin film transistor according to the prior art.

도 2a 내지 도 2c는 본 발명에 따른 박막트랜지스터 제조방법을 도시하는 공정도2a to 2c is a process chart showing a thin film transistor manufacturing method according to the present invention.

도 3은 본 발명을 설명하기 위한 개략도Figure 3 is a schematic diagram for explaining the present invention

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

31, 51 : 투명기판 33 : 버퍼층31, 51: transparent substrate 33: buffer layer

35 : 활성층 37 : 게이트절연막35 active layer 37 gate insulating film

39 : 게이트전극 41 : 불순물영역39: gate electrode 41: impurity region

53 : 어레이영역 55 : 가열수단53 array area 55 heating means

57 : 이온도핑수단57: ion doping means

상기 목적들을 달성하기 위한 본 발명에 따른 박막트랜지스터의 제조방법은기판 상의 소정 부분에 활성층을 형성하는 공정과, 상기 활성층 상에 상기 활성층의 양측이 노출되도록 게이트절연막을 개재시켜 게이트전극을 형성하는 공정과, 상기 게이트전극을 마스크로 사용하여 상기 활성층을 가열하면서 불순물을 이온 도핑하여 상기 활성층의 양측에 불순물영역을 형성하는 공정을 구비한다.A method of manufacturing a thin film transistor according to the present invention for achieving the above objects is a step of forming an active layer on a predetermined portion on the substrate, and forming a gate electrode through a gate insulating film so that both sides of the active layer are exposed on the active layer And forming an impurity region on both sides of the active layer by ion doping an impurity while heating the active layer using the gate electrode as a mask.

상기 목적 외에 본 발명의 다른 목적 및 특징들은 첨부한 도면들을 첨부한 도면들을 참조한 실시예에 대한 설명을 통하여 명백하게 드러나게 될 것이다.Other objects and features of the present invention in addition to the above objects will become apparent from the following description of the embodiments with reference to the accompanying drawings.

이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2c는 본 발명에 따른 박막트랜지스터의 제조방법을 도시하는 공정도이다.2A to 2C are process diagrams illustrating a method of manufacturing a thin film transistor according to the present invention.

도 2a를 참조하면, 투명기판(31) 상에 질화실리콘 또는 산화실리콘을 CVD 방법으로 증착하여 버퍼층(33)을 형성한다. 버퍼층(33) 상에 불순물이 도핑되지 않은 다결정실리콘 또는 비정질실리콘을 CVD 방법으로 증착하여 활성층(35)을 형성한다. 그리고, 활성층(35)을 버퍼층(33)의 소정 부분에만 잔류하도록 포토리쏘그래피 방법으로 패터닝한다.Referring to FIG. 2A, silicon nitride or silicon oxide is deposited on the transparent substrate 31 by CVD to form a buffer layer 33. The active layer 35 is formed by depositing polysilicon or amorphous silicon that is not doped with impurities on the buffer layer 33 by a CVD method. The active layer 35 is patterned by a photolithography method so that only the predetermined portion of the buffer layer 33 remains.

도 2b를 참조하면, 버퍼층(33) 상에 활성층(35)을 덮도록 질화실리콘 또는 산화실리콘 등의 절연물질을 CVD 방법으로 증착한다. 그리고, 절연물질층 상에 알루미늄(Al) 또는 구리(Cu) 등의 도전성 금속을 스퍼터링 또는 CVD 방법으로 증착한다.Referring to FIG. 2B, an insulating material such as silicon nitride or silicon oxide is deposited on the buffer layer 33 by CVD to cover the active layer 35. A conductive metal such as aluminum (Al) or copper (Cu) is deposited on the insulating material layer by sputtering or CVD.

도전성 금속층 및 절연물질층을 활성층(35) 상의 소정 부분에만 잔류하도록 포토리쏘그래피 방법으로 패터닝하여 게이트절연막(37)과 게이트전극(39)을 형성한다. 이 때, 활성층(35)의 양측이 노출된다.The gate insulating layer 37 and the gate electrode 39 are formed by patterning the conductive metal layer and the insulating material layer by a photolithography method so as to remain only on a predetermined portion on the active layer 35. At this time, both sides of the active layer 35 are exposed.

도 2c를 참조하면, 게이트전극(39)을 마스크로 사용하여 활성층(35)의 노출된 부분에 인(P) 또는 아세닉(As) 등의 N형 불순물 이온을 이온 도핑하여 소오스 및 드레인영역으로 이용되는 고농도의 불순물영역(41)을 형성한다. 상기에서 불순물영역(41)은, 활성층(35)을 200∼300℃ 정도의 온도로 가열한 후 바로 불순물을 이온 도핑함으로써 된다. 이 때, 활성층(35)이 가열된 상태이므로 도핑되는 이온은 별도의 활성화 공정이 없이도 자기 활성화(self activation)되어 불순물영역(41)이 형성된다. 그러므로, 불순물영역(41)을 형성할 때 공정이 간단해질 뿐만 아니라 게이트전극(39)이 손상되는 것이 방지진다.Referring to FIG. 2C, N-type impurity ions, such as phosphorus (P) or arsenic (As), are ion-doped to an exposed portion of the active layer 35 using the gate electrode 39 as a mask to form a source and a drain region. The high concentration impurity region 41 to be used is formed. The impurity region 41 is obtained by ion doping an impurity immediately after the active layer 35 is heated to a temperature of about 200 to 300 ° C. At this time, since the active layer 35 is in a heated state, the doped ions are self activated without a separate activation process to form the impurity region 41. Therefore, when the impurity region 41 is formed, not only the process is simplified but also the gate electrode 39 is prevented from being damaged.

도 3은 본 발명을 설명하기 위한 개략도이다.3 is a schematic view for explaining the present invention.

도면은 투명기판(51) 상의 어레이영역(53)에 도 2c에 도시된 바와 같이 활성층(35)에 불순물영역(41)을 형성하는 것을 나타낸다. 상기에서 불순물영역(41)을 형성하기 위한 장치는 챔버(도시되지 않음) 내에 소정 거리 이격되게 설치된 이온 도핑수단(57)과 RTA(Rapid Thermal Annealing)하는 가열수단(55)을 갖는다.The drawing shows that the impurity region 41 is formed in the active layer 35 in the array region 53 on the transparent substrate 51 as shown in FIG. 2C. The apparatus for forming the impurity region 41 has an ion doping means 57 and a heating means 55 for rapid thermal annealing (RTA) installed in a chamber (not shown) spaced a predetermined distance apart.

투명기판(51)을 챔버(도시되지 않음) 내에 장착한 후 소정 거리 이격되게 설치된 가열수단(55)과 도핑수단(57)을 동시에 어레이영역(53) 내의 일측으로부터 타측으로 이동하면서 활성층(35)을 가열하고 불순물을 도핑하여 불순물영역(41)을 형성한다. 상기에서 가열수단(55)과 도핑수단(57)을 어레이영역(53) 내의 일측으로부터 타측으로 이동하면서 활성층(35)을 가열하고 불순물을 도핑하므로 활성층(35)은 가열수단(55)에 의해 가열된 상태에서 도핑수단(57)에 의해 불순물이 도핑된다. 그러므로, 활성층(35)에 도핑되는 불순물 이온은 별도의 열처리 공정을 하지 않고도 자기 활성화(self activation)되어 불순물영역(41)이 형성된다.After the transparent substrate 51 is mounted in a chamber (not shown), the heating means 55 and the doping means 57, which are installed at a predetermined distance apart, are moved from one side to the other side in the array region 53 at the same time. Is heated and doped with impurities to form the impurity region 41. Since the heating means 55 and the doping means 57 are moved from one side to the other side in the array region 53, the active layer 35 is heated and doped with impurities, so the active layer 35 is heated by the heating means 55. In this state, impurities are doped by the doping means 57. Therefore, the impurity ions doped in the active layer 35 are self-activated to form the impurity region 41 without a separate heat treatment process.

상술한 바와 같이 본 발명에 따른 박막트랜지스터의 제조방법은 소정 거리 이격되게 설치된 이온 도핑수단 및 가열수단을 갖는 장비를 이용하여 활성층을 RTA 방법으로 가열한 상태에서 불순물 이온을 도핑하므로써 별도의 활성화 공정을 하지 않아도 자기 활성화(self activation)되어 소오스 및 드레인영역으로 이용되는 불순물영역을 형성한다.As described above, the method of manufacturing the thin film transistor according to the present invention uses a device having ion doping means and heating means spaced at a predetermined distance to perform a separate activation process by doping impurity ions in the state in which the active layer is heated by the RTA method. If not, self activation is performed to form impurity regions used as source and drain regions.

따라서, 본 발명은 불순물영역을 형성하기 위한 이온 도핑 및 활성화를 동일한 장비에서 동시에 실시할 수 있으므로 장비가 간편해지고 공정이 단순해지며, 또한, 게이트전극이 손상되는 것을 방지할 수 있다.Therefore, the present invention can simultaneously carry out ion doping and activation to form the impurity region in the same equipment, thereby simplifying the equipment and simplifying the process, and can also prevent the gate electrode from being damaged.

이상 설명한 내용을 통해 당업자라면 본 발명의 기술 사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다. 따라서, 본 발명의 기술적 범위는 명세서의 상세한 설명에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의해 정하여져야 할 것이다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (6)

기판 상의 소정 부분에 활성층을 형성하는 공정과,Forming an active layer on a predetermined portion on the substrate, 상기 활성층 상에 상기 활성층의 양측이 노출되도록 게이트절연막을 개재시켜 게이트전극을 형성하는 공정과,Forming a gate electrode on the active layer by interposing a gate insulating film to expose both sides of the active layer; 상기 게이트전극을 마스크로 사용하여 상기 활성층을 가열하면서 불순물을 이온 도핑하여 상기 활성층의 양측에 불순물영역을 형성하는 공정을 구비하는 박막트랜지스터의 제조방법.Forming an impurity region on both sides of the active layer by ion doping an impurity while heating the active layer using the gate electrode as a mask. 청구항 1에 있어서,The method according to claim 1, 상기 활성층을 가열하는 가열수단과 상기 불순물 이온을 도핑하는 이온도핑수단이 동일한 챔버 내에 소정 간격 이격되게 설치된 장치를 이용하여 상기 불순물 영역을 형성하는 박막트랜지스터의 제조방법.And a heating means for heating the active layer and an ion doping means for doping the impurity ions to form the impurity region by using a device provided at a predetermined interval in the same chamber. 청구항 2에 있어서,The method according to claim 2, 상기 불순물영역을 상기 챔버 내에 어레이영역을 갖는 투명기판을 장착한 후 상기 가열수단과 도핑수단을 상기 어레이영역 내의 일측으로부터 타측으로 동시에 이동하면서 형성하는 박막트랜지스터의 제조방법.And mounting the impurity region in the chamber with a transparent substrate having an array region and simultaneously moving the heating means and the doping means from one side to the other side in the array region. 청구항 2에 있어서,The method according to claim 2, 상기 활성층을 RTA(Rapid Thermal Annealing) 방법으로 가열하는 박막트랜지스터의 제조방법.Method of manufacturing a thin film transistor for heating the active layer by a rapid thermal annealing (RTA) method. 청구항 4에 있어서,The method according to claim 4, 상기 활성층을 200∼300℃의 온도로 가열하는 박막트랜지스터의 제조방법.A method of manufacturing a thin film transistor for heating the active layer to a temperature of 200 ~ 300 ℃. 청구항 3에 있어서,The method according to claim 3, 상기 불순물영역을 상기 이온 도핑된 불순물 이온을 자기 활성화시켜 형성하는 박막트랜지스터의 제조방법.The impurity region is formed by self-activating the ion-doped impurity ions.
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US10811522B2 (en) 2010-11-11 2020-10-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
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