KR100239782B1 - Method of fabricating a thin film transistor - Google Patents

Method of fabricating a thin film transistor Download PDF

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Publication number
KR100239782B1
KR100239782B1 KR1019970045503A KR19970045503A KR100239782B1 KR 100239782 B1 KR100239782 B1 KR 100239782B1 KR 1019970045503 A KR1019970045503 A KR 1019970045503A KR 19970045503 A KR19970045503 A KR 19970045503A KR 100239782 B1 KR100239782 B1 KR 100239782B1
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source
active layer
layer
drain
substrate
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KR1019970045503A
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KR19990024414A (en
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서성모
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구본준
엘지.필립스 엘시디주식회사
론 위라하디락사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure

Abstract

본 발명은 박막트랜지스터의 제조방법에 관한 것으로, 기판에 소오스/드레인전극을 형성하는 공정과, 기판 상에 소오스/드레인전극을 노출시키는 콘택홀이 형성된 완충산화막을 형성하는 공정과, 완충산화막 상에 비정질실리콘을 증착한 후, 콘택홀 및 소오스/드레인전극 사이의 기판을 덮도록 패터닝하여 활성층을 형성하는 공정과, 활성층 상에 게이트산화막 및 게이트전극을 형성하는 공정과, 활성층을 어닐링하여 소오스/드레인영역을 형성하는 공정을 구비한 것이 특징이다.The present invention relates to a method for manufacturing a thin film transistor, comprising: forming a source / drain electrode on a substrate; forming a buffer oxide film having contact holes exposing the source / drain electrodes on the substrate; After depositing amorphous silicon, patterning the substrate between the contact hole and the source / drain electrodes to form an active layer; forming a gate oxide film and a gate electrode on the active layer; and annealing the active layer to source / drain the active layer. It is characterized by including the step of forming a region.

그리고 본 발명에서는 소오스/드레인전극의 경사진 측면을 완충산화막으로 덮고 그 상면에 활성층을 형성함으로써, 레이저 결정화 시, 소오스/드레인전극의 경사진 측면에서 스텝커버리지가 양호한 잇점이 있다. 따라서, 레이저 결정화 시에 소오스/드레인전극의 경사진 측면에 형성된 박막이 제거되지 않아 결정화 특성이 개선된다.In the present invention, the inclined side surface of the source / drain electrode is covered with a buffer oxide film and an active layer is formed on the top surface of the source / drain electrode, so that the step coverage is good in the inclined side of the source / drain electrode during laser crystallization. Therefore, the thin film formed on the inclined side of the source / drain electrode is not removed during laser crystallization, and the crystallization characteristic is improved.

Description

박막트랜지스터의 제조방법Method of manufacturing thin film transistor

본 발명은 액정표시장치(Liquid Crystal Display)의 박막트랜지스터(Thin Film Transistor)의 제조방법에 관한 것으로, 특히, 활성층이 소오스/드레인전극의 경사진 면에서 스텝커버리지(stepcoverage)가 우수하도록 한 박막트랜지스터의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor of a liquid crystal display. In particular, a thin film transistor having an active layer having excellent step coverage in an inclined surface of a source / drain electrode. It relates to a manufacturing method of.

유리기판에 형성되는 실리콘층인 활성층을 저온에서 증착되어야 하므로 다결정 실리콘(polysilicon)으로 형성하기 보다는 저온에서 공정이 가능한 비정질실리콘(amorphous silicon)으로 형성하여 다결정실리콘 박막트랜지스터를 형성하는 기술이 개발되었다.Since the active layer, which is a silicon layer formed on a glass substrate, must be deposited at a low temperature, a technology of forming a polysilicon thin film transistor by forming amorphous silicon (amorphous silicon) that can be processed at low temperature is developed rather than forming polysilicon.

즉, 채널영역이 형성될 활성층으로 저온에서 비정질실리콘을 증착한 후, 전면에 레이저를 조사하여 다결정실리콘으로 결정화함으로써, 캐리어(carrier)의 이동도를 크게한다.That is, after depositing amorphous silicon at low temperature with the active layer to be formed in the channel region, and irradiated with a laser on the front surface to crystallize to polycrystalline silicon, the mobility of the carrier (carrier) is increased.

도1a 내지 도1d는 종래기술에 따른 박막트랜지스터의 제조공정도로, 이하 첨부된 도면을 참조하여 설명하겠다.1A to 1D are manufacturing process diagrams of a thin film transistor according to the prior art, which will be described below with reference to the accompanying drawings.

도1a를 참조하면, 기판(10) 상에 크롬(Cr) 또는 몰리브덴(Mo) 등의 금속을 스퍼터링(sputtering) 등의 방법을 이용하여 금속층(12)을 형성한다.Referring to FIG. 1A, a metal layer 12 is formed on a substrate 10 using a method such as sputtering a metal such as chromium (Cr) or molybdenum (Mo).

이어서, 금속층 상에 PECVD(Plasma Enhanced CVD) 방법으로 저온에서 진행시키어 불손물이 고농도를 도핑된 비정질실리콘층(14)을 형성한다.Subsequently, the amorphous silicon layer 14 doped with a high concentration of impurity is formed on the metal layer by using a plasma enhanced CVD (PECVD) method.

도1b를 참조하면, 사진식각 공정에 의하여 금속층(12) 및 불순물이 고농도로 도핑된 비정질실리콘층(14)을 패터닝하여 소오스/드레인(source/drain)전극(13) 및 오믹콘택층(ohmic contact)(15)을 형성한다.Referring to FIG. 1B, a source / drain electrode 13 and an ohmic contact layer are patterned by patterning the metal layer 12 and the amorphous silicon layer 14 heavily doped with impurities by a photolithography process. (15).

그리고 오믹콘택층(15)은 금속층인 소오스/드레인전극(13)과 이 후에 형성될 실리콘층인 활성층 간의 접속층으로 사용된다.The ohmic contact layer 15 is used as a connection layer between the source / drain electrode 13 which is a metal layer and the active layer which is a silicon layer to be formed later.

도1c를 참조하면, 기판(10) 상에 오믹콘택층(15)을 덮도록 불순물이 도핑되지 않은 비정질실리콘층을 증착한 후, 소오스/드레인전극을 덮고 소오스/드레인전극(12) 사이의 기판(10)과 접촉되도록 포토리쏘그래피(photolithography)방법으로 패터닝(patterning)하여 활성층(17)을 형성한다.Referring to FIG. 1C, after depositing an amorphous silicon layer that is not doped with impurities to cover the ohmic contact layer 15 on the substrate 10, the substrate is disposed between the source / drain electrodes 12 and covering the source / drain electrodes 12. The active layer 17 is formed by patterning the photolithography method so as to be in contact with 10.

이 때, 증착되는 비정질실리콘층은 500∼600Å 정도의 두께로 형성한다.At this time, the deposited amorphous silicon layer is formed to a thickness of about 500 to 600 kPa.

다음에, 패터닝된 비정질실리콘층을 레이저(laser)로 조사하여 국부적으로 용융시키면서 전면을 다결정실리콘층으로 결정화하며, 동시에 오믹콘택층(15)인 불순물이 고농도로 도핑된 비정질실리콘층도 결정화시키어 불순물이 고농도로 도핑된 다결정실리콘층으로 형성한다. 즉, 오믹콘택층(15)과 활성층(17)을 동시에 결정화시킨다.Next, the patterned amorphous silicon layer is irradiated with a laser and locally melted to crystallize the entire surface into a polysilicon layer. At the same time, the amorphous silicon layer doped with a high concentration of impurities as the ohmic contact layer 15 is also crystallized. This highly doped polysilicon layer is formed. That is, the ohmic contact layer 15 and the active layer 17 are simultaneously crystallized.

도1d를 참조하면, 기판(10) 상에 활성층(17)을 덮도록 실리콘산화층과 금속층을 순차적으로 형성한 후, 포토리쏘그래피 방법으로 활성층(17) 상의 소오스/드레인전극(12) 사이에 잔류되도록 패터닝하여 게이트절연막(18)과 게이트전극(19)을 형성한다.Referring to FIG. 1D, a silicon oxide layer and a metal layer are sequentially formed to cover the active layer 17 on the substrate 10, and then remain between the source / drain electrodes 12 on the active layer 17 by photolithography. The gate insulating film 18 and the gate electrode 19 are formed by patterning the gate insulating film 18.

그리고, 게이트전극(19)을 마스크로 사용하여 활성층(17) 상에 PH3이온을 도핑(doping)하거나 PH3가스를 사용하여 플라즈마(plasma)로 처리하여 소오스/드레인영역(17-1)을 형성한다.In addition, the source / drain regions 17-1 are doped by doping PH 3 ions onto the active layer 17 using the gate electrode 19 as a mask or treating the plasma with plasma using a PH 3 gas. Form.

그러나, 상술한 종래의 기술에서는 금속층인 소오스/드레인전극과 실리콘층인 활성층 간의 접촉력이 좋지 않아 스텝커버리지가 불량하다. 따라서, 활성층 형성시 소오스/드레인전극의 경사진 측면에서 박막의 두께가 얇아지며, 그에 따라 레이저 결정화 시에 소오스/드레인전극의 경사진 측면의 박막이 떨어지거나 결정화 특성이 나빠지게 되는 문제점이 있었다.However, in the above-described conventional technique, the contact force between the source / drain electrode, which is a metal layer, and the active layer, which is a silicon layer is poor, resulting in poor step coverage. Therefore, when the active layer is formed, the thickness of the thin film becomes thin on the inclined side of the source / drain electrode, and thus, when the laser crystallizes, the thin film on the inclined side of the source / drain electrode may fall or the crystallization characteristics deteriorate.

또한, 오믹콘택층과 활성층을 한꺼번에 레이저를 조사하여 결정화해야 하는 어려움이 있었다.In addition, there was a difficulty in crystallizing the ohmic contact layer and the active layer by irradiating a laser at once.

본 발명의 목적은 소오스/드레인전극 상에 활성층 형성 시, 소오스/드레인전극의 경사진 면에서 박막이 제거되지 않도록 보호하기 위해 소오스/드레인전극의 경사진 측면이 감싸여지도록 형성된 박막트랜지스터의 제조방법을 제공하려는 것이다.An object of the present invention is a method of manufacturing a thin film transistor formed so that the inclined side of the source / drain electrode is wrapped to protect the thin film from the inclined surface of the source / drain electrode when the active layer is formed on the source / drain electrode Is to provide.

따라서, 상기의 목적을 달성하고자 본 발명의 박막트랜지스터의 제조방법은 기판에 소오스/드레인전극을 형성하는 공정과, 기판 상에 상기 소오스/드레인전극을 노출시키는 콘택홀이 형성된 완충산화막을 형성하는 공정과, 완충산화막 상에 콘택홀 및 상기 소오스/드레인전극 사이의 기판을 덮도록 패터닝된 활성층을 형성하는 공정과, 활성층 상에 게이트산화막 및 게이트전극을 형성하는 공정을 구비한 것을 특징으로 한다.Accordingly, in order to achieve the above object, a method of manufacturing a thin film transistor according to the present invention includes forming a source / drain electrode on a substrate and forming a buffer oxide film having contact holes exposing the source / drain electrode on the substrate. And forming a patterned active layer on the buffer oxide film so as to cover the substrate between the contact hole and the source / drain electrodes, and forming a gate oxide film and a gate electrode on the active layer.

이하, 첨부된 도면을 참조하여 본 발명을 설명하겠다.Hereinafter, the present invention will be described with reference to the accompanying drawings.

도1a 내지 도1d는 종래기술에 따른 박막트랜지스터의 제조공정도이고,1a to 1d is a manufacturing process diagram of a thin film transistor according to the prior art,

도2a 내지 도2d는 본 발명의 제1실시예를 도시한 것으로, 박막트랜지스터 제조공정도이고,2A to 2D show a first embodiment of the present invention, which is a manufacturing process diagram of a thin film transistor.

도3a 내지 3d는 본 발명의 제2실시예를 도시한 것으로, 박막트랜지스터 제조공정도이고,3A to 3D show a second embodiment of the present invention, which is a manufacturing process diagram of a thin film transistor.

도2a 내지 도2d는 본 발명의 제3실시예를 도시한 것으로, 박막트랜지스터 제조공정도이다.2A to 2D show a third embodiment of the present invention, which is a manufacturing process diagram of a thin film transistor.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10, 20, 30, 40 : 기판 12, 22, 32, 42 : 금속층10, 20, 30, 40: substrate 12, 22, 32, 42: metal layer

13, 23, 33, 43 : 소오스/드레인전극 14, 24, 44 : 실리콘층13, 23, 33, 43: source / drain electrodes 14, 24, 44: silicon layer

15, 25, 45 : 오믹콘택층 17, 27, 37, 47 : 완충산화막15, 25, 45: ohmic contact layer 17, 27, 37, 47: buffer oxide film

27-1, 37-1, 47-1 : 소오스/드레인영역27-1, 37-1, 47-1: source / drain regions

18, 28, 38, 48 : 게이트산화막 19, 29, 39, 49 : 게이트전극18, 28, 38, 48: gate oxide film 19, 29, 39, 49: gate electrode

도2a 내지 도2c는 본 발명의 제1실시예를 도시한 것으로, 소오스/드레인전극의 경사진 측면이 완충산화막 및 활성층으로 감싸여지도록 형성된 박막트랜지스터 제조공정도이다.2A to 2C illustrate a first embodiment of the present invention, in which a slanted side surface of a source / drain electrode is formed to be wrapped with a buffer oxide film and an active layer.

도2a를 참조하면, 기판(20) 상에 크롬(Cr) 또는 몰리브덴(Mo) 등의 금속을 이용하여 스퍼터링 등의 방법으로 금속층(22)을 형성한다.Referring to FIG. 2A, the metal layer 22 is formed on the substrate 20 by sputtering or the like using a metal such as chromium (Cr) or molybdenum (Mo).

이어서, 금속층(22) 상에 PECVD 방법으로 진행시키어 불순물이 도핑되지 않은 비정질실리콘층(24)을 형성한다.Subsequently, the metal layer 22 is subjected to PECVD to form an amorphous silicon layer 24 which is not doped with impurities.

다음에, 비정질실리콘층(24)을 레이저로 조사하여 국부적으로 용융시키면서 점차로 전면을 다결정실리콘층으로 결정화한다.Next, the amorphous silicon layer 24 is irradiated with a laser and locally melted to gradually crystallize the entire surface into a polycrystalline silicon layer.

도2b를 참조하면, 포토리쏘그피 방법으로 금속층(22) 및 불순물이 도핑되지 않은 다결정실리콘층(24)을 패터닝하여 소오스/드레인전극(23) 및 오믹콘택층(25)을 형성한다.Referring to FIG. 2B, the source / drain electrode 23 and the ohmic contact layer 25 are formed by patterning the metal layer 22 and the non-doped polysilicon layer 24 by a photolithography method.

도2c를 참조하면, 기판(20) 상에 소오스/드레인전극(23)을 덮도록 완충산화막(26)을 형성한 후, 소오스/드레인전극(23) 상면이 노출되도록 콘택홀(H)을 형성한다. 이 때, 증착되는 완충산화막(26)은 2000∼3000Å 정도의 두께로 형성한다.Referring to FIG. 2C, after forming the buffer oxide film 26 to cover the source / drain electrodes 23 on the substrate 20, the contact hole H is formed to expose the top surface of the source / drain electrodes 23. do. At this time, the deposited buffer oxide film 26 is formed to a thickness of about 2000 to 3000 microns.

다음에, 완충산화막(26) 및 오믹콘택층(25) 상에 저온공정으로 불순물이 도핑되지 않은 비정질실리콘층을 증착한 후, 소오스/드레인전극(23) 사이의 기판(20)과 접촉되고 소오스/드레인전극(23)을 덮도록 포토리쏘그래피 방법으로 패터닝하여 활성층(27)을 형성한다.Next, after depositing an amorphous silicon layer having no impurities doped on the buffer oxide film 26 and the ohmic contact layer 25 by a low temperature process, the substrate 20 between the source / drain electrodes 23 is brought into contact with the source. The active layer 27 is formed by patterning the photoresist layer so as to cover the drain electrode 23.

이어서, 활성층(27)을 레이저로 조사하여 국부적으로 용융시키면서 전면을 다결정실리콘층으로 결정화한다.Subsequently, the active layer 27 is irradiated with a laser and locally melted to crystallize the entire surface into a polycrystalline silicon layer.

이 때, 채널영역이 형성될 활성층을 비정질실리콘으로 증착한 후, 레이저를 조사하여 다결정실리콘으로 결정하는 방법은 다결정실리콘을 증착하여 활성층을 이루는 방법보다 저온에서 형성될 수 있다.At this time, the method of depositing the active layer on which the channel region is to be formed of amorphous silicon and then irradiating a laser to determine polycrystalline silicon may be formed at a lower temperature than the method of depositing polycrystalline silicon to form the active layer.

도2d를 참조하면, 기판(20) 상에 활성층(27)을 덮도록 실리콘산화층과 금속층을 순차적으로 형성한 후, 포토리쏘그래피 방법으로 활성층(27) 상의 소오스/드레인전극(23) 사이에 잔류되도록 패터닝하여 게이트절연막(28)과 게이트전극(29)을 형성한다.Referring to FIG. 2D, a silicon oxide layer and a metal layer are sequentially formed to cover the active layer 27 on the substrate 20, and then remain between the source / drain electrodes 23 on the active layer 27 by photolithography. The gate insulating film 28 and the gate electrode 29 are formed by patterning the gate insulating film 28.

그리고, 게이트전극(29)을 마스크로 사용하여 활성층(27) 상에 PH3이온을 도핑하거나 PH3가스를 사용하여 플라즈마로 처리하여 소오스/드레인영역(27-1)을 형성한다.The source / drain regions 27-1 are formed by doping PH 3 ions on the active layer 27 using the gate electrode 29 as a mask or by plasma treatment using PH 3 gas.

이 때, 이온도핑은 소오스/드레인전극(23) 상에 불순물이 도핑되지 않은 다결정실리콘인 오믹콘택층(25)이 한층만 존재할 때 발생할 수 있는 전류패스길이를 짧게 하여 소자특성을 개선한다.At this time, ion doping improves device characteristics by shortening the current path length that may occur when only one layer of the ohmic contact layer 25, which is polycrystalline silicon without impurities doped on the source / drain electrodes 23, is improved.

상술한 바와 같이, 종래에는 오믹콘택층과 활성층을 한꺼번에 레이저를 조사하여 결정화해야 하는 어려움이 있었지만, 본 발명의 제1실시예에서는 오믹콘택층 및 활성층을 각각 레이저 조사를 함으로써 결정화 공정을 수월하게 할 수 있다.As described above, in the related art, the ohmic contact layer and the active layer have been difficult to crystallize by irradiating a laser at once, but in the first embodiment of the present invention, the ohmic contact layer and the active layer are respectively irradiated with laser to facilitate the crystallization process. Can be.

그리고 소오스/드레인전극(23)의 경사진 양측면을 완충산화막(26)이 감싸고, 또한, 개구된 완충산화막을 소오스/드레인영역(27-1)이 덮고 있는 구조를 갖으므로, 소오스/드레인전극(23)의 경사진 측면으로 부터 박막이 제거될 우려가 없고 또한, 그에따라 전기적 특성이 나빠지는 것을 방지한다.Since the buffer oxide film 26 covers the inclined both sides of the source / drain electrodes 23 and the open buffer oxide film covers the source / drain regions 27-1, the source / drain electrodes ( There is no fear that the thin film can be removed from the inclined side of 23), thereby preventing the electrical properties from deteriorating.

도3a 내지 도3d는 본 발명의 제2실시예를 도시한 것으로, 소오스/드레인전극의 경사진 측면이 완충산화막 및 활성층으로 감싸여지도록 형성된 박막트랜지스터 제조공정도이다.3A to 3D illustrate a second embodiment of the present invention, in which a slanted side surface of a source / drain electrode is formed to be surrounded by a buffer oxide film and an active layer.

도3a를 참조하면, 기판(30) 상에 크롬(Cr) 또는 몰리브덴(Mo) 등의 금속을 스퍼터링 등의 방법을 이용하여 금속층(32)을 형성한다.Referring to FIG. 3A, a metal layer 32 is formed on a substrate 30 by sputtering a metal such as chromium (Cr) or molybdenum (Mo).

도3b를 참조하면, 포토리쏘그래피 방법으로 금속층(32)을 패터닝하여 소오스/드레인전극(33)을 형성한다.Referring to FIG. 3B, the metal layer 32 is patterned by photolithography to form the source / drain electrodes 33.

도3c를 참조하면, 기판(30) 상에 소오스/드레인전극(33)을 덮도록 완충산화막(36)을 형성한 후, 소오스/드레인전극(33) 상면이 노출되도록 콘택홀(H-1)을 형성한다.Referring to FIG. 3C, after the buffer oxide layer 36 is formed on the substrate 30 to cover the source / drain electrodes 33, the contact hole H-1 may be exposed to expose the top surface of the source / drain electrodes 33. To form.

이어서, 완충산화막(36) 및 소오스/드레인전극(33) 상에 다결정실리콘을 증착한 후, 소오스/드레인전극(33) 사이의 기판(30)과 접촉되고 소오스/드레인전극(33)을 덮도록 포토리쏘그래피 방법으로 패터닝하여 활성층(37)을 형성한다.Subsequently, polycrystalline silicon is deposited on the buffer oxide film 36 and the source / drain electrodes 33, and then contacted with the substrate 30 between the source / drain electrodes 33 to cover the source / drain electrodes 33. The active layer 37 is formed by patterning the photolithography method.

도3d를 참조하면, 기판(30) 상에 활성층(37)을 덮도록 실리콘산화층을 형성하고, 실리콘산화층 상에 금속층을 형성한 후, 사진식각공정에 의해 활성층(37) 상의 소오스/드레인전극(33) 사이에 잔류되도록 패터닝하여 게이트절연막(38)과 게이트전극(39)을 형성한다.Referring to FIG. 3D, a silicon oxide layer is formed on the substrate 30 to cover the active layer 37, a metal layer is formed on the silicon oxide layer, and a source / drain electrode on the active layer 37 is formed by a photolithography process. Patterned so as to remain between 33, the gate insulating film 38 and the gate electrode 39 are formed.

다음에, 게이트전극(39)을 마스크로 사용하여 활성층(37) 상에 PH3이온을 도핑하거나 PH3가스를 사용하여 플라즈마로 처리하여 소오스/드레인영역(37-1)을 형성한다. 이 때, 불순물의 열에 의한 재분포가 일어나지 않는 저온에서 실현하는 것이 바람직하다.Next, the source / drain regions 37-1 are formed by doping PH 3 ions onto the active layer 37 using the gate electrode 39 as a mask or by treating the plasma with a PH 3 gas. At this time, it is preferable to realize at low temperature where redistribution by heat of impurities does not occur.

상기의 공정에서, 활성층(37)인 다결정실리콘에 도핑된 각각의 이온은 결정 격자 중에서 충돌을 반복하면서 내부로 나아가서 정지한다. 이 경우 주위에 결정 구조적인 손상영역을 남기는 데, 이 영역은 상호 오버랩(overlap)하여 기판 위의 도핑영역 표면 전면에 걸쳐서 결함층을 형성한다. 따라서, 기판이 받은 손상은 일반적으로 어닐(열처리)에 의해서 회복시킬 수 있다. 이러한 어닐링의 수단으로 소오스/드레인영역(37-1)에 레이저를 조사한다.In the above process, each of the ions doped in the polycrystalline silicon, which is the active layer 37, proceeds inside and stops while repeating collision in the crystal lattice. This leaves a crystalline structural damage region around, which overlaps each other to form a defect layer over the entire surface of the doped region on the substrate. Therefore, damage to the substrate can generally be recovered by annealing (heat treatment). The laser is irradiated to the source / drain region 37-1 by such annealing means.

상기의 본 발명의 제2실시예에서는 제1실시예와 마찬가지로, 소오스/드레인전극(33)의 경사진 측면을 완충산화막(36)이 감싸고, 또한, 개구된 완충산화막(36) 상부를 소오스/드레인영역(37-1)이 덮고 있으므로 소오스/드레인전극(33)이 외부에 노출되지 않아 전기적 특성이 나빠지는 것을 방지한다.In the second embodiment of the present invention, as in the first embodiment, the buffer oxide film 36 surrounds the inclined side surface of the source / drain electrode 33, and the source / drain upper portion of the buffer oxide film 36 is opened. Since the drain region 37-1 is covered, the source / drain electrodes 33 are not exposed to the outside to prevent the electrical characteristics from deteriorating.

도4a 내지 도4b는 본 발명의 제3실시예를 도시한 것으로, LDD를 이용한 박막트랜지스터 제조공정도이다.4A to 4B show a third embodiment of the present invention, which is a manufacturing process diagram of a thin film transistor using LDD.

도4a를 참조하면, 기판(40) 상에 크롬(Cr) 또는 몰리브덴(Mo) 등의 금속을 스퍼터링 등의 방법을 이용하여 금속층(42)을 형성한다.Referring to FIG. 4A, a metal layer 42 is formed on a substrate 40 by sputtering a metal such as chromium (Cr) or molybdenum (Mo).

그리고 금속층(42) 상에 PECVD 방법으로 진행시키어 불순물이 고농도로 도핑된 다결정실리콘층(44)을 형성한다.In addition, the metal layer 42 is subjected to PECVD to form a polysilicon layer 44 doped with impurities at a high concentration.

도4b를 참조하면, 포토리쏘그래피 방법으로 금속층(42) 및 불순물이 고농도로 도핑된 다결정실리콘층(44)을 패터닝하여 소오스/드레인전극(43) 및 오믹콘택층(45)을 형성한다.Referring to FIG. 4B, a source / drain electrode 43 and an ohmic contact layer 45 are formed by patterning the metal layer 42 and the polysilicon layer 44 doped with a high concentration of impurities by a photolithography method.

도4c를 참조하면, 기판(40) 상에 소오스/드레인전극(43)을 덮도록 완충산화막(46)을 형성한 후, 소오스/드레인전극(43) 상면이 노출되도록 콘택홀(H-2)을 형성한다.Referring to FIG. 4C, after the buffer oxide layer 46 is formed on the substrate 40 to cover the source / drain electrodes 43, the contact hole H-2 may be exposed to expose the top surface of the source / drain electrodes 43. To form.

이어서, 완충산화막(46) 및 소오스/드레인전극(43) 상에 불순물이 도핑되지 않은 비정질실리콘층을 증착한 후, 소오스/드레인전극(43) 상이의 기판(40)과 접촉되고 소오스/드레인전극(43)을 덮도록 포토리쏘그래피 방법으로 패터닝하여 활성층(47)을 형성한다.Subsequently, after depositing an amorphous silicon layer that is not doped with impurities on the buffer oxide film 46 and the source / drain electrode 43, the source / drain electrode 43 is in contact with the substrate 40 and the source / drain electrode The active layer 47 is formed by patterning it so as to cover the 43.

다음에, 활성층(47)을 레이저로 조사하여 국부적으로 용융시키면서 전면을 다결정실리콘층으로 결정화한다.Next, the active layer 47 is irradiated with a laser and locally melted to crystallize the entire surface into a polycrystalline silicon layer.

도4d를 참조하면, 기판(40) 상에 활성층(47)을 덮도록 실리콘산화층을 형성하고, 실리콘산화층 상에 금속층을 순차적으로 형성한 후, 포토리쏘그래피 방법에 의해 활성층(47) 상의 소오스/드레인전극(43) 상이에 실리콘산화층 및 금속층이 잔류되도록 패터닝하여 게이트절연막(48)과 게이트전극(49)을 형성한다.Referring to FIG. 4D, a silicon oxide layer is formed on the substrate 40 to cover the active layer 47, and a metal layer is sequentially formed on the silicon oxide layer, and then a source / image on the active layer 47 is formed by a photolithography method. The gate insulating layer 48 and the gate electrode 49 are formed by patterning the silicon oxide layer and the metal layer to remain on the drain electrode 43.

다음에, 활성층(47) 상에 게이트전극(49)을 마스크로 하여 저농도의 PH3이온을 도핑하거나 플라즈마 상태로 처리하여 LDD(Lightly Doped Drain)구조인 소오스/드레인영역(47-1)을 형성한다.Next, the source / drain region 47-1 having the LDD (Lightly Doped Drain) structure is formed by doping low concentration PH 3 ions or treating the plasma in the plasma state using the gate electrode 49 as a mask on the active layer 47. do.

상기에서, 본 발명의 제3실시예에서는 LDD 구조를 이용하여 소오스/드레인영역을 형성하며, 제1 및 제2실시예와 마찬가지로, 소오스/드레인전극(43)의 경사진 양측면을 완충산화막(46)이 감싸고, 또한, 개구된 완충산화막(46)을 LDD 구조을 갖는 소오스/드레인영역(47-1)이 덮고 있으므로 소오스/드레인전극(43)의 경사진 측면으로 부터 박막이 제거될 우려가 없고, 또한 소오스/드레인전극이 외부로 노출되지 않는다.In the third embodiment of the present invention, the source / drain regions are formed by using the LDD structure. Similarly to the first and second embodiments, the inclined sides of the source / drain electrodes 43 are formed on the buffer oxide film 46. ) And the open buffer oxide film 46 are covered by the source / drain region 47-1 having the LDD structure, so that there is no fear that the thin film is removed from the inclined side of the source / drain electrode 43. In addition, the source / drain electrodes are not exposed to the outside.

상술한 바와 같이, 본 발명의 박막트랜지스터 제조방법에서는 소오스/드레인전극의 경사진 측면을 완충산화막으로 덮고 그 상면에 활성층을 형성함으로써, 레이저 결정화 시, 소오스/드레인전극의 경사진 측면에서 스텝커버리지가 양호한 잇점이 있다.As described above, in the method of manufacturing the thin film transistor of the present invention, by covering the inclined side surface of the source / drain electrode with the buffer oxide film and forming the active layer on the top surface, the step coverage is increased in the inclined side surface of the source / drain electrode during laser crystallization. There is a good advantage.

따라서, 레이저 결정화 시에 소오스/드레인전극의 경사진 측면에 형성된 박막이 제거되지 않아 결정화 특성이 개선된다.Therefore, the thin film formed on the inclined side of the source / drain electrode is not removed during laser crystallization, and the crystallization characteristic is improved.

Claims (4)

박막트랜지스터 제조방법에 있어서, 기판에 소오스/드레인전극을 형성하는 공정과, 상기 기판 상에 상기 소오스/드레인전극을 노출시키는 콘택홀이 형성된 완충산화막을 형성하는 공정과, 상기 완충산화막 상에 비정질실리콘을 증착한 후, 상기 콘택홀 및 상기 소오스/드레인전극 사이의 기판을 덮도록 패터닝하여 활성층을 형성하는 공정과, 상기 활성층 상에 게이트산화막 및 게이트전극을 형성하는 공정과, 상기 활성층을 어닐링하여 소오스/드레인영역을 형성하는 공정을 구비한 박막트랜지스터의 제조방법.A thin film transistor manufacturing method, comprising: forming a source / drain electrode on a substrate, forming a buffer oxide film having a contact hole exposing the source / drain electrode on the substrate, and amorphous silicon on the buffer oxide film After the deposition, patterning the substrate between the contact hole and the source / drain electrodes to form an active layer; forming a gate oxide film and a gate electrode on the active layer; and annealing the active layer to form a source. A method of manufacturing a thin film transistor, comprising the step of forming a drain / drain region. 청구항 1에 있어서, 상기 완충산화막을 2000∼3000Å 두께로 형성한 것이 특징인 박막트랜지스터의 제조방법.The method of manufacturing a thin film transistor according to claim 1, wherein the buffer oxide film is formed to have a thickness of 2000 to 3000 GPa. 청구항 1에 있어서, 상기 어닐링 수단으로는 레이저를 조사한 것이 특징인 박막트랜지스터의 제조방법.The method of manufacturing a thin film transistor according to claim 1, wherein the annealing means is irradiated with a laser. 박막트랜지스터 제조방법에 있어서, 기판에 소오스/드레인전극을 형성하는 공정과, 상기 기판 상에 상기 소오스/드레인전극을 노출시키는 콘택홀이 형성된 완충산화막을 형성하는 공정과, 상기 완충산화막 상에 비정질실리콘을 증착한 후, 상기 콘택홀 및 상기 소오스/드레인전극 사이의 기판을 덮도록 패터닝하여 활성층을 형성하는 공정과, 상기 활성층을 어닐링하는 공정과, 상기 활성층 상에 게이트산화막 및 게이트전극을 형성하는 공정과, 상기 활성층을 저농도로 도핑하여 LDD(Lightly Doped Drain)인 소오스/드레인영역을 형성하는 공정을 구비한 박막트랜지스터의 제조방법.A thin film transistor manufacturing method, comprising: forming a source / drain electrode on a substrate, forming a buffer oxide film having a contact hole exposing the source / drain electrode on the substrate, and amorphous silicon on the buffer oxide film After the deposition, patterning the substrate between the contact hole and the source / drain electrodes to form an active layer, annealing the active layer, and forming a gate oxide film and a gate electrode on the active layer. And forming a source / drain region of LDD (Lightly Doped Drain) by lightly doping the active layer.
KR1019970045503A 1997-09-02 1997-09-02 Method of fabricating a thin film transistor KR100239782B1 (en)

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KR100482460B1 (en) * 1998-10-28 2005-09-02 비오이 하이디스 테크놀로지 주식회사 Method for forming polysilicon thin film transistor of liquid crystal display device

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