KR20010065188A - Method of manufacturing a flash memory device - Google Patents

Abstract

PURPOSE: A method for manufacturing a flash memory device is provided to perform spacer etching operation as well as SAS etching operation at the same time after forming stack gate electrode, so preventing destruction of a tunnel oxide layer due to SAS etching. CONSTITUTION: At first, a field oxide layer is formed and a semiconductor substrate which has a stack gate electrode thereon is provided. Then, the first PR(photoresist) pattern exposing a cell formation reservation region is formed by using a photolithography and etching operations using a cell source mask and a source region is formed by an ion injection and thermal process. At third, the first PR pattern is removed, a S/D ion injection operation is performed to form a drain region. Then, a dielectric layer is formed on the overall structure and the second PR pattern which exposes the cell source region is formed by using a SAS(self-align source) mask. At fifth, the spacer etching operation as well as SAS etching operation are performed at the same time to form a spacer dielectric layer(56) on the sidewall of the gate electrode, and a field oxide layer on the source region is removed. At last, a shallow junction region is formed on the semiconductor substrate from which the field oxide layer is removed by using the ion injection operation and processed to form a common source line.

Description

Method of manufacturing a flash memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and in particular, to prevent damage to a tunnel oxide film and to oxidize a gate electrode during a self-aligned source (SAS) etching process of a stack gate structure flash memory device. It relates to a method for manufacturing a semiconductor device that can prevent the improvement of the characteristics of the device.

In flash memory devices, which are electrically erasable and programmable nonvolatile memory devices, charge retention is a major factor affecting device reliability. Charge retention is a characteristic of flash memory devices, in which electrons in the floating gate are lost or gained by an external stimulus, and its main path is known as the source edge side.

Next, a method of manufacturing a conventional flash memory device will be described with reference to FIGS. 1 to 3.

1 is a layout view of a general flash memory device, FIGS. 2A to 2E are cross-sectional views of the X-X 'portion of FIG. 1, and FIGS. 3A to 3E are cross-sectional views of the Y-Y' portion of FIG.

2A and 2E, a tunnel oxide film 22 is formed on a semiconductor substrate on which the field oxide film 11 is formed, and the floating gate 12, the dielectric film 23, and the control gate are formed by a general gate electrode forming process. A stack gate electrode in which the 13 and the top oxide film 24 are stacked is formed. Subsequently, a first photoresist pattern 25 in which a cell source formation region is opened is formed by a photo and etching process using a cell source mask, and a DDD ion implantation process is performed, thereby forming a source S region. Next, a primary heat treatment process is performed to alleviate the damage of the tunnel oxide film 22 by the DDD ion implantation.

Referring to FIGS. 2B and 3B, the first PR pattern 25 is removed and the cell source region is exposed by a photo and etching process using a self-aligned source mask. The second photoresist pattern 26 is formed, and the field oxide film 11 of the exposed source region is removed. Thereafter, a secondary heat treatment process is performed to alleviate damage to the source side tunnel oxide layer 22 and to enhance charge retention characteristics by the SAS.

2C and 3C, by removing the second PR pattern 26 and opening the entire cell region to perform a source / drain ion implantation process, a drain D region is formed and at the same time the field oxide film 11 is formed. The shallow junction region 31 is formed in the semiconductor substrate 21 which is removed and exposed. In addition, the source S region and the shallow junction region 31 are connected to form a common source line.

Referring to FIGS. 2D and 3D, an insulating material is deposited on the entire structure and a spacer etching process is formed to form a spacer insulating layer 27 on both sidewalls of the stack gate.

Thereafter, the source contact 14 and the drain contact 15 are formed by an interlayer insulating film formation and an etching process using a contact mask.

Such a conventional flash memory manufacturing method has the following problems.

The first problem is an attack on the source (S) side tunnel oxide layer 22 and the semiconductor substrate 21 generated during SAS etching. When etching SAS, both of the semiconductor substrate 21 and the field oxide film 11 on the source S side are etched. However, if the recipe having a good etching selectivity is used, the loss of the semiconductor substrate 21 may be minimized, if not completely. There is a number. However, the tunnel oxide film 2 on the side of the source S is left open as it is when it is etched, resulting in loss. In this case, the charge retention is one of the most important characteristics of the flash device.

Second, the problem of oxidation of the polysilicon gate electrode by the subsequent heat treatment process after the SAS etching process. A source / drain heat treatment process is performed to prevent damage to the tunnel oxide layer 22 and charge loss to the source S side during SAS etching. Oxidation of polysilicon is well known in this heat treatment process, and the edge portions of the floating gate and control gate made of polysilicon are oxidized during the heat treatment process.

Due to the oxidation of the polysilicon gate, problems such as reduction in source / drain junction overlap, dielectric film smileing, and the like, reduce coupling ratio and effective channel depth. As a result, the cell erase / program characteristics are deteriorated, the bit line leakage current is increased, and the cell current is increased. In particular, there is a trend to increase the thermal oxidation rate in order to prevent charge loss toward the source (S), which is in a trade-off relationship with the above-described problems of device characteristics.

4 is a graph illustrating a program characteristic of a flash memory cell according to an oxidation target during source / drain annealing.

As shown, it can be seen that the program characteristics decrease as the source / drain annealing target increases.

Accordingly, the present invention prevents damage of the tunnel oxide layer due to SAS etching and oxidation of the gate electrode by heat treatment after SAS etching by simultaneously performing a spacer etching process and a SAS etching process after forming a stacked gate electrode of a flash memory device. It is an object of the present invention to provide a method of manufacturing a flash memory device capable of preventing the damage.

According to an aspect of the present invention, there is provided a method of manufacturing a flash memory device, the method including: forming a field oxide layer and providing a semiconductor substrate having a stacked gate electrode; Forming a first PR pattern in which the cell source formation target region is exposed by a photo and etching process using a cell source mask from the first step, and forming a source region by an ion implantation process and a heat treatment process; Removing the first PR pattern and performing a S / D ion implantation process to form a drain region; Forming an insulating film on the entire structure and forming a second PR pattern exposing the cell source region by a photolithography and an etching process using a self-aligned source mask; Performing a spacer etching process and a SAS etching process simultaneously to form a spacer insulating film on the sidewall of the gate electrode, and to remove the field oxide film of the exposed source region; And forming a shallow junction region on the semiconductor substrate from which the field oxide film has been removed by an ion implantation process, and performing heat treatment, thereby forming a common source line.

1 is a layout diagram of a typical flash memory device.

2A to 2D and 3A to 3D are cross-sectional views of devices sequentially shown to explain a method of manufacturing a conventional flash memory device.

4 is a graph illustrating program characteristics of a flash memory cell according to an oxidation target during source / drain annealing.

5A to 5D and 6A to 6D are cross-sectional views of devices sequentially shown to explain a method of manufacturing a flash memory device according to the present invention.

<Description of the symbols for the main parts of the drawings>

11: field oxide film 12: floating gate

13: control gate 14: source contact

15: drain contact 21, 51: semiconductor substrate

22, 52: tunnel oxide film 23, 53: dielectric film

24, 54: top oxide film 25, 55: first photoresist pattern

26, 56: spacer insulating film 31, 61: shallow junction region

55: first photoresist pattern

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

5A to 5D and 6A to 6D are cross-sectional views of devices sequentially shown to explain a method of manufacturing a flash memory device according to the present invention. FIG. 5 is a cross-sectional view of part XX ′ of FIG. 1. 6 is a sectional view taken along the line YY 'of FIG. 5A and 6A, a tunnel oxide film 52 is formed on a semiconductor substrate 51 on which a field oxide film 11 is formed by an element isolation process, and the floating gate 12 is formed by a general gate electrode forming process. A stacked gate electrode in which the dielectric film 53, the control gate 13, and the top oxide film 54 are stacked is formed. Subsequently, a first photoresist pattern 55 in which a cell source formation region is opened is formed by a photo and etching process using a cell source mask, a DDD ion implantation process is performed, and thus a source S region is formed. . Next, a primary heat treatment process is performed to mitigate damage to the tunnel oxide film 52 by the DDD ion implantation process.

5B and 6B, the first photoresist pattern 55 is removed, and the entire cell region is opened to perform a source / drain ion implantation process, thereby forming a drain D region.

5C and 6C, insulating film 56A is formed over the entire structure. In addition, a second photoresist pattern 57 may be formed on the entire structure in which the insulating layer 56A is formed by photolithography and etching using a SAS mask to open the cell source S region. In this case, the insulating film 56A is formed to a thickness of 1000 to 2000 GPa.

5D and 6D, in the etching process using the second photoresist pattern 57 as a mask, the spacer etching process and the SAS etching process are simultaneously performed. As a result, a spacer insulating film 56 is formed on the sidewalls of the stacked gate electrodes, and the field oxide film 11 in the source S region is removed. At this time, since the tunnel oxide film 52 of the stacked gate electrode is protected by the insulating film 56A, the tunnel oxide film 52 is not affected by the SAS etching process. Thereafter, an ion implantation process is performed on the semiconductor substrate 51 from which the field oxide film 11 is removed to form a shallow junction region 61. Accordingly, the source S and the shallow junction region 61 are connected in a line form to form a common source line. Herein, the ions implanted to form the shallow junction region 61 are implanted into the source S region, and then the second photoresist pattern 57 is removed, and the activation of the ions implanted in the junction region is performed. A secondary heat treatment process is performed. At this time, since the gate electrode is protected by the spacer insulating film 56, oxidation of the gate electrode does not occur.

As described above, according to the present invention, since the spacer insulating film protects the edge portion of the tunnel oxide layer, it is possible to prevent damage to the tunnel oxide layer due to SAS etching, thereby improving the reliability characteristics of the device, and the gate electrode is surrounded by the spacer film. Therefore, oxidation of the gate electrode by the subsequent heat treatment process can be prevented, and various problems such as dielectric film smileing, dielectric film coupling ratio reduction, junction overlap reduction, and effective channel length reduction can be improved.

Claims (3)

Providing a semiconductor substrate having a field oxide film formed thereon and a stacked gate electrode formed thereon; Forming a first PR pattern exposing the cell source formation target region by a photo and etching process using a cell source mask from the first step and forming a source region by an ion implantation process and a heat treatment process; Removing the first PR pattern and performing a S / D ion implantation process to form a drain region; Forming an insulating film on the entire structure and forming a second PR pattern exposing the cell source region by a photolithography and an etching process using a self-aligned source mask; Performing a spacer etching process and a SAS etching process simultaneously to form a spacer insulating film on the sidewall of the gate electrode, and to remove the field oxide film of the exposed source region; And Forming a shallow junction region on the semiconductor substrate from which the field oxide film has been removed by an ion implantation process, and heat treating the same, thereby forming a common source line. The method of claim 1 The insulating film is a method of manufacturing a flash memory device, characterized in that formed in a thickness of 1000 to 2000Å. The method of claim 1, The shallow junction region is formed by implanting impurity ions of the same type as the source region.