KR100452313B1 - Nonvolatile Memory Device and Manufacturing Method - Google Patents

Abstract

The nonvolatile memory device of the present invention is a nonvolatile memory device that forms a source line by matching a stacked gate including a control gate using a SAS etching process to form a first buffer layer on the stacked gate. A second buffer layer is formed on the sidewalls or sidewalls and the upper side of the stacked gate to protect the second conductive layer with the first buffer layer at the time of etching the SAS, and also considering the relative thicknesses of the stacked gate and the field oxide layer. By adjusting the thickness of the buffer layer, the height of the stacked gate sidewalls in which the second buffer layer remains is etched by the thickness of the first buffer layer even if the height of the stacked gate and the thickness of the field oxide layer to be etched on the source line are different. Due to the margin, the gate oxide and the bottom of the gate oxide adjacent to the edge of the source side stacked gate Damage to the semiconductor substrate can be reduced.

Description

Nonvolatile Memory Device and Manufacturing Method Thereof

The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device using a SAS (Self Aligned Source) etching process and a method of manufacturing the same.

The SAS etching process eliminates non-uniformity in the erase threshold voltage of the cell caused by the misalignment of the control gate and the source line, resulting in the overlap of the source between the even and odd rows. In order to form a source line by matching to the control gate to achieve the use of the flash memory due to the advantage that can increase the memory density (density) in addition to the advantage of solving the misalignment problem in the flash memory Doing.

FIG. 1 illustrates a layout of a general nonvolatile memory device using the SAS etching process, and FIG. 2 illustrates an equivalent circuit of FIG. 1, in which four transistors each include an active region 1 and the active region ( 1, a floating gate 2 corresponding to a region in which a partial region (= floating gate etching region) 4 is etched from the control gate 3, and the active region 1 And a contact window 5 formed on the N, and a source line and a drain region, all of which are commonly connected to the source line.

3 is a cross-sectional view of the nonvolatile memory device taken along line a-a 'of FIG. 1, and is sequentially stacked on the gate oxide film 12 and the gate oxide film 12. Impurity ions are implanted into the semiconductor substrate by applying a patterned stacked gate electrode of the first conductive layer 14, the first oxide layer 14, and the second conductive layer 18, and a double diffused implant (DDI) mask. A first impurity diffusion region 22 formed, a second impurity diffusion region 24 formed by ion implanting impurity ions onto the semiconductor substrate by applying a modified drain mask (MDD) mask, and a partial region of the stacked gate electrode And a SAS photoresist pattern 20 formed in the second impurity diffusion region 24 on one side thereof, and using the SAS etching method, the memory density can be increased as described above.

However, in the non-volatile memory device of FIG. 3, the side surface of the stacked gate electrode, that is, the source active region, is exposed when the SAS is etched, thereby damaging the gate oxide layer and the semiconductor substrate below, and the impurity diffusion profile is uneven. Since the reliability is reduced, a method of forming the spacer 21 before the SAS process has been developed as shown in FIG. 4.

The structure and manufacturing method thereof will be described as follows.

First, a gate oxide film 12 is formed on the semiconductor substrate 10, and a first conductive layer 14 to be provided as a floating gate on the gate oxide film 12, and a material for insulating the floating gate from a control gate of a subsequent process. The first oxide layer 16 and the second conductive layer 18 to be provided as the control gate are stacked and photographed and etched to form a stacked gate.

Subsequently, a DDI mask is formed on the surface of the resultant with photoresist and applied thereto to form a first impurity diffusion region 22 by ion implantation of impurity ions into the semiconductor substrate at low concentration, and then the DDI mask is removed. After the oxide film is grown on the surface of the semiconductor substrate, the spacer 21 is formed on the sidewall of the stacked gate.

Subsequently, a SAS etching process is performed by applying a SAS mask to remove the field oxide film of the source region to connect the source lines, and ion implantation is performed to form a second impurity diffusion region 24 to be provided as a source / drain region. After the mask is formed, impurity ions are implanted into the semiconductor substrate 10 by applying the mask.

However, even when the spacer is formed to protect the stacked gate sidewalls as described above, as shown in FIG. 5, the thickness d of the field oxide layer 11 to be etched in the source region is the thickness d ′ of the stacked gate. In the case of relatively thicker spacers, the spacers are formed. However, when the field oxide is etched, all of the spacers are etched to damage the exposed gate oxides in contact with the edges of the stacked gates (FIG. 6B). Even if the etching selectivity of the conductive layer is increased, the upper region of the second conductive layer is exposed, so as to be etched as shown in FIG. 6A, the resistance component of the control gate increases and additionally adversely affects subsequent processes. There is this.

Accordingly, an object of the present invention is to form a first buffer layer on the stacked gate and a second buffer layer on a portion of sidewalls of the stacked gate to solve the problems of the related art. A nonvolatile memory device capable of preventing damage to a side surface, a gate oxide film adjacent to a stacked gate edge, and a semiconductor substrate is provided.

Another object of the present invention is to provide a manufacturing method for efficiently implementing the nonvolatile memory device.

A nonvolatile memory device of the present invention for achieving the above object is a gate oxide film formed on a semiconductor substrate, a multilayer stacked gate formed on the gate oxide film, a first buffer layer formed on one side edge of the stacked gate, and the stacked type And a multi-layer spacer formed on sidewalls of the gate.

According to another aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device, including sequentially forming a gate oxide layer and a stacked gate on a first conductive semiconductor substrate, and forming the source / drain region. Implanting impurity ions of a second conductivity type into the semiconductor substrate as a mask, forming a second buffer layer on the surface of the resultant, and forming a SAS mask using a photoresist on the second buffer layer. And then etching the resultant to expose the surface of the semiconductor substrate using the same, ion implanting impurity ions of a second conductivity type into the exposed semiconductor substrate, and growing an oxide film over the entire surface of the resultant. Forming a spacer by etching back and forming a spacer; It characterized in that it comprises a step of ion implantation.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

In the nonvolatile memory device according to the present invention, first, as shown in FIG. 7, a gate oxide film 52 is formed on a substrate of a first conductivity type semiconductor substrate 50, and a polycrystalline silicon layer is formed on the gate oxide film 52. A first conductive layer 54 is formed of a conductive material, and a first oxide layer 56 is formed on the first conductive layer 54 to insulate the first conductive layer from the second conductive layer. After the second conductive layer 58 is formed of a conductive material such as polycrystalline silicon or polyside on the 56, the first buffer layer 60 is formed of an insulating material on the second conductive layer 58. In the case of the first buffer layer 60, the thickness is adjusted in consideration of the relative thicknesses of the stacked gate and the field oxide layer.

Subsequently, in FIG. 8, after the first photoresist 62 is coated on the first buffer layer 60, an etch mask is formed according to a photographic process, and subsequently, the etch mask is applied to form a stacked gate. The first buffer layer 60, the second conductive layer 58, the first oxide layer 56, the first conductive layer 54, and the gate oxide layer 52 are etched to expose a surface thereof, and then a second layer is formed in the semiconductor substrate. The conductive impurity ions 64 are implanted to form first impurity diffusion regions 66, 67, and 68 to be provided as source / drain regions. In this case, the first photoresist may be removed before forming the first impurity diffusion region.

9 and 10, a second buffer layer 70 is formed by depositing an insulating material on the surface of the resultant to a thickness of about several hundred micrometers and then coating a second photoresist 72 on the second buffer layer 70. And forming a SAS etching mask according to the photolithography process, and applying the same to the resultant to etch the resultant to open the source region, and subsequently to form a second erase type impurity ion (75). Is implanted at a predetermined angle to form the second impurity diffusion region 76. This process may be performed before the etching process after forming the SAS etching mask.

According to the result of FIG. 10, the second buffer layer 73 and the first buffer layer 60 are partially etched, and in the case of the second buffer layer 73, one side wall of the stacked gate and the gate oxide layer on the same vertical line. It partially remains on one side wall to protect the stacked gate and the gate oxide layer, and the other side wall of the stacked gate and one side wall of the first buffer layer 60 on the same vertical line and the upper front surface of the first buffer layer 60. The lower portion of the second photoresist 72 remains.

Subsequently, although not shown, in the logic circuit region other than the cell portion, a conductive material such as polysilicon is deposited and then patterned to form a gate, and an ion implantation mask is formed with a photoresist and applied thereto to implant n-ion impurities into the semiconductor substrate. LDD and p-LDD regions are formed, and impurity ion implantation is subsequently performed to prevent punch-through.

Subsequently, in FIG. 11, a second oxide film 78 is formed to form a spacer on the surface of the resultant product.

Subsequently, the second oxide film is etched back on the entire surface, and as shown in FIG. 12, the first buffer layer 60 is etched to expose the first oxide layer, thereby etching the first buffer layer 60 to be on the same vertical line as one side wall of the stacked gate and one side wall of the stacked gate. 1. A multi-layer spacer is formed of the etched second buffer layer 74 and the etched second oxide layer 80 adjacent to one side of the buffer layer and adjacent to a portion of the other side wall of the stacked gate, and then impurity ions in the semiconductor substrate. 82 is implanted to form a third impurity diffusion region 84.

In addition, the second oxide layer is etched back to the entire surface, and as shown in FIG. 13, the second buffer layer 73 is exposed to be etched to expose the one side wall of the stacked gate, the upper front surface of the first buffer layer, and the one side wall of the stacked gate. A second buffer layer 73 adjacent to one side wall of the first buffer layer on the same vertical line as the first buffer layer and adjacent to a part of the other side wall of the stacked gate, and both side walls of the stacked gate and one side wall of the second buffer layer. After forming a multi-layer spacer with the etched second oxide layer 80, third impurity ions 82 are implanted into the semiconductor substrate to form a third impurity diffusion region 84.

As described above, according to the present invention, the source / drain region is formed by ion implantation of impurity ions after the formation of the stacked gate without an additional photolithography process, so that the overlap region with the stacked gate is constant even after the SAS etching. In addition, the concentration profile of the source region is not affected by the SAS etching, and secondly, the second conductive layer is protected by the first buffer layer during SAS etching, and the thickness of the stacked gate and the field oxide layer is considered in consideration of the relative thickness of the stacked gate and the field oxide layer. When the thickness of the first buffer layer is adjusted, even if the height of the stacked gate is different from the thickness of the field oxide layer to be etched on the source line side, the height of the stacked gate sidewall in which the second buffer layer remains is the thickness of the first buffer layer. Since there is an etch margin, the edges of the source-side stacked gates during SAS etching Damage to the oxide film and the lower semiconductor substrate can be reduced, and damage caused by partial etching or plasma etching of the second conductive layer can be reduced by the first and second buffer layers during the third SAS etching. It is possible to selectively add impurity ion implantation to form impurity regions after SAS etching for devices adopting the source erasing method as the erasing method without the photo process.

1 illustrates a layout of a typical nonvolatile memory cell.

2 shows the equivalent circuit of FIG. 1,

3 is a cross-sectional view of a nonvolatile memory device using a conventional SAS (Self Aligned Source) etching process.

4 is a cross-sectional view of a nonvolatile memory device using a conventional SAS etching process using a spacer.

5 and 6 illustrate causes and defects of defects in manufacturing the nonvolatile memory device of FIG. 4.

7 to 13 illustrate a method of manufacturing a nonvolatile memory device according to the present invention in order.

<Explanation of symbols for the main parts of the drawings>

50: semiconductor substrate 52: gate oxide film

54: first conductive layer 56: first oxide film

58: second conductive layer 60: first buffer layer

62: first photoresist 64,82: impurity ions

66, 67, 68: first impurity diffusion region 70: second buffer layer

72 second photoresist 76 second impurity diffusion region

78: second oxide film 84: third impurity diffusion region

Claims (17)

A gate oxide film formed on the semiconductor substrate, a multilayer stacked gate formed on the gate oxide film, a first buffer layer formed on one side edge of the stacked gate, and a multilayer spacer formed on sidewalls of the stacked gate. Nonvolatile memory device. The nonvolatile memory device of claim 1, wherein the stacked gate is formed by sequentially layering a first conductive layer pattern, an insulating layer pattern, and a second conductive layer pattern on the gate oxide layer. The nonvolatile memory device of claim 1, wherein the multi-layer spacer is left and right asymmetrical. The nonvolatile memory device of claim 1, wherein the multilayer spacer comprises a first spacer and a second spacer from sidewalls of the stacked gate. The multi-layer spacer of claim 1, wherein the multilayer spacer is adjacent to one side wall of the stacked gate and one side wall of the first buffer layer on the same vertical line as one side wall of the stacked gate, and adjacent to a portion of the other side wall of the stacked gate. And a second spacer covering both sidewalls of the stacked gate and the first spacer. 2. The multilayer structure of claim 1, wherein the multilayer spacer is adjacent to one side wall of the stacked gate, an upper front surface of the first buffer layer, and one side wall of the first buffer layer on the same vertical line as one side wall of the stacked gate. And a second spacer adjacent to a portion of the other sidewall of the gate, and a second spacer covering both sidewalls of the stacked gate and one sidewall of the first spacer. The nonvolatile memory device of claim 4, wherein the first spacer is formed of an insulating layer. The nonvolatile memory device of claim 4, wherein the second spacer is formed of an oxide film. Sequentially forming a gate oxide film and a stacked gate on a first conductive semiconductor substrate, and impurity ions of the second conductive type are first applied to the semiconductor substrate using the stacked gate as a mask to form a source / drain region. Implanting the ion, forming a second buffer layer on the surface of the resultant, forming a SAS mask with a photoresist on the second buffer layer, and then etching the resultant to expose the surface of the semiconductor substrate using the same; And ion implanting a second conductivity type impurity ion into the exposed semiconductor substrate, growing an oxide film on the entire surface of the resultant, and etching back to form a spacer; Non-volatile comprising the step of ion implanting impurity ions of the second conductivity type Memory devices how prepared. The method of claim 9, wherein the forming of the stacked gate is performed by sequentially forming a first conductive layer, an insulating layer, and a second conductive layer on the gate oxide layer, and etching the same using a photo and an etching process. Method for manufacturing nonvolatile memory device. The method of claim 10, wherein the first conductive layer and the second conductive layer are made of polycrystalline silicon. The method of claim 10, wherein the second conductive layer is made of polyside. 10. The method of claim 9, wherein the second buffer layer has a thickness of about several hundred microseconds. 10. The nonvolatile memory device of claim 9, wherein the ion implantation of the impurity ions of the second conductivity type into the semiconductor substrate is performed by ion implantation of the impurity ions of the second conductivity type at an arbitrary angle. Manufacturing method. 10. The method of claim 9, wherein the ion implantation of the second conductivity type impurity ions into the semiconductor substrate is performed before the SAS etching. The method of claim 9, wherein the forming of the spacers comprises etching the oxide layer only to expose the second buffer layer under the oxide layer when the spacer is etched after forming the oxide layer. The method of claim 9, wherein the forming of the spacer comprises etching the oxide layer and the second buffer layer during etching back after forming the oxide layer so that the upper surface of the upper surface of the first buffer layer below the second buffer layer and the upper partial surface of the stacked gate are exposed. Non-volatile memory device manufacturing method characterized in that.

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