CN112447737A - Integrated circuit, memory device and forming method thereof - Google Patents

Integrated circuit, memory device and forming method thereof Download PDF

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Publication number
CN112447737A
CN112447737A CN202010787448.8A CN202010787448A CN112447737A CN 112447737 A CN112447737 A CN 112447737A CN 202010787448 A CN202010787448 A CN 202010787448A CN 112447737 A CN112447737 A CN 112447737A
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China
Prior art keywords
source
line
dielectric layer
gate line
etch
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CN202010787448.8A
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Chinese (zh)
Inventor
黄咏胜
刘铭棋
黄志斌
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US16/800,167 external-priority patent/US11239245B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN112447737A publication Critical patent/CN112447737A/en
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    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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Abstract

Various embodiments of the present invention are directed to a method for opening a source line in a memory device. The Erase Gate Line (EGL) and the source line are formed to be elongated in parallel. The source line is located below the EGL and separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stop on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process includes a third etch with the second mask in place, the third etch extending the first opening through the dielectric layer. Vias are formed that extend through the EGL to the silicide layer. Embodiments of the invention also relate to integrated circuits, memory devices, and methods of forming the same.

Description

Integrated circuit, memory device and forming method thereof
Technical Field
Embodiments of the invention relate to integrated circuits, memory devices, and methods of forming the same.
Background
Many modern electronic devices include flash memory. Flash memory is a non-volatile computer storage medium that can be electrically erased and reprogrammed. To store information, flash memory includes an addressable array of memory cells, typically made up of floating gate transistors. Common types of flash memory cells include stacked gate flash memory cells and split gate flash memory cells (e.g., third generation ultra flash (ESF3) memory cells). Split gate flash memory cells have lower power consumption, higher injection efficiency, lower sensitivity to short channel effects, and over-erase immunity compared to stacked gate flash memory cells.
Disclosure of Invention
An embodiment of the present invention provides a memory device including: a substrate; an erase gate line, a control gate line, and a source line elongated in parallel in a first direction, wherein the erase gate line has a break dividing the erase gate line into a pair of erase gate segments in the first direction, wherein the control gate line is adjacent to the erase gate line, and wherein the source line is located under the erase gate line in the substrate; a source dielectric layer between the erase gate line and the source line; main sidewall spacers over the source dielectric layer and the source lines at centers between the erase gate segments; and a contact via extending through the erase gate line and the source dielectric layer at the break and electrically coupled with the source line.
Another embodiment of the present invention provides an Integrated Circuit (IC) including: a substrate; a memory array including a plurality of cells, wherein the plurality of cells includes a source bar cell and a pair of control gate bar cells; an erase gate line and a source line partially defining the source bar cells and elongated in parallel in a first direction, wherein the source line is located below the erase gate line, and wherein the erase gate line has a first break in the first direction; a first control gate line, a second control gate line, and a pair of select gate lines partially defining the control gate bar unit and elongated in parallel in the first direction, wherein the select gate lines are located between and respectively adjacent to the first control gate line and the second control gate line and have a second break in the first direction, and wherein the first control gate line has a pad protruding toward the second control gate line at the second break; and a trench isolation structure located under the first and second control gate lines; wherein the top surface of the substrate has a recess with a U-shaped top layout surrounding the pads at the second break.
Yet another embodiment of the present invention provides a method for forming a memory device, the method comprising: forming an erase gate line and a source line elongated in parallel, wherein the source line is located below the erase gate line in a substrate and separated from the erase gate line by a source dielectric layer; performing a first etch on the erase gate line to form a first opening extending through the erase gate line, wherein the first etch is performed with a first mask in place and stops on the source dielectric layer; performing a second etch of the source dielectric layer through the first opening with the first mask in place to thin the source dielectric layer at the first opening; performing a silicide process to form a silicide layer on the source line at the first opening, wherein the silicide process includes a third etch that extends the first opening through the source dielectric layer and exposes the source line; and forming a contact via extending through the erase gate line to the silicide layer.
Drawings
Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.
Fig. 1A-1C illustrate various views of some embodiments of a memory device including source bar cells, according to aspects of the present invention.
Fig. 2A-2D illustrate enlarged cross-sectional views of various embodiments of the source bar cell at fig. 1A.
Fig. 3A and 3B show enlarged cross-sectional views of various embodiments of the source bar cell at fig. 1B.
Fig. 4 illustrates a more detailed top layout of some embodiments of the source bar cell at fig. 1C.
Fig. 5 illustrates a cross-sectional view of some embodiments of a memory device including source bar cells and Control Gate (CG) bar cells, in accordance with aspects of the invention.
Fig. 6A and 6B show cross-sectional views of some alternative embodiments of the CG bar element at fig. 5.
Fig. 7 illustrates a top layout of some embodiments of the CG bar cell at fig. 5.
Fig. 8 shows a schematic top view of some embodiments of a memory device including a memory array in which the source bar cells and CG bar cells of fig. 5 are arranged, and further including lines and vias interconnecting the cells of the memory array.
FIG. 9 illustrates a top layout of some embodiments of a portion of the memory array of FIG. 8.
Fig. 10-13 and 16-24 show a series of cross-sectional views of some embodiments of methods for forming a memory device including source bar cells and CG bar cells, in accordance with aspects of the present invention.
Fig. 14A and 14B show cross-sectional views of some alternative embodiments of the source bar cell at fig. 13.
Fig. 15A and 15B illustrate cross-sectional views of various embodiments of the source bar cell at fig. 13 in a direction orthogonal to the cross-sectional view of fig. 13.
Fig. 25 illustrates a block diagram of some embodiments of the methods of fig. 10-13 and 16-24.
Fig. 26-32 show a series of cross-sectional views of some alternative embodiments of the method of fig. 10-13 and 16-24, wherein the active regions and the trench isolation structures have different layouts.
Detailed Description
The present invention provides many different embodiments or examples for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, for ease of description, pitch relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. Pitch relationship terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the pitch relationship descriptors used herein interpreted accordingly as such.
The memory device may, for example, include a plurality of device lines. The plurality of device lines include a Select Gate (SG) line, a Control Gate (CG) line, an Erase Gate (EG) line, and a source line extending in parallel. The CG line is located between the EG line and the SG line, and the source line is located below the EG line in the substrate. The plurality of device lines define a plurality of memory cells and a plurality of stripe cells spaced along a length of the device lines. The stripe unit electrically couples the device line with a metal line having a lower resistance than the device line repeatedly along the device line to reduce the resistance, and thus reduce a voltage drop along the device line. At the bar cells for the source line (e.g., source bar cells), the EG line has a break to allow access to the source line. At a bar unit for a CG line (e.g., a CG bar unit), the CG line has a pad protruding laterally. Further, the SG wire has a break to prevent the risk of contact vias electrically shorting the CG wire and SG wire together, and/or to prevent the SG wire from electrically shorting to an adjacent SG wire.
In some embodiments, a first etch is performed on the EG lines and the SG lines with the first mask in place while the source bar cells and the CG bar cells are formed. The first etch stops on the source dielectric layer and the substrate portions below the EG line and SG line, respectively. In addition, the first etching simultaneously forms first and second openings extending through the EG and SG lines, respectively, at the source and CG bar cells. Thereafter, with the second mask in place, a second etch is performed on the source dielectric layer, rather than on the substrate portion. The second etch removes portions of the source dielectric layer in the first openings to expose the source lines at the source bar cells. A photoresist protective oxide (RPO) layer is deposited lining the first opening, and a third etch is performed on the RPO layer with a third mask in place to extend the first opening through the RPO layer to the source line. With the RPO layer in place, a silicide layer is formed on the source lines, and contact vias are formed on the silicide layer. The challenge is that the formation of the second mask may result in photoresist scum on the source lines even after the second mask is removed. The dross may prevent the silicide layer from forming properly on the source line and thus may result in a high resistance connection between the contact via and the source line. High resistance connections may cause device failure and/or deviate operating parameters (e.g., power consumption) from specification, and thus mass production yields may be low.
Various embodiments of the present invention are directed to enhanced etching methods for opening source lines in memory devices as well as the memory devices themselves. It should be understood that the second mask may be omitted and a second etch may be performed with the first mask in place to thin the source dielectric layer without exposing the source lines. Further, the third etch may extend (e.g., increase in duration) to extend the first opening through the source dielectric layer and expose the source line. Thus, the enhanced etching method may use at least one photomask less. Using less than one photomask can save a significant amount of cost due to the high cost of forming the photomask and the high cost of using the photolithographic processing tool. In addition, since the second mask can be omitted, the risk of contaminating the source line in the first opening is reduced. This enlarges the process window for forming the silicide layer and the contact vias (e.g., making the process more flexible).
Referring to fig. 1A-1C, various views 100A-100C of some embodiments of a memory device including source bar cells 102 are provided. Fig. 1A corresponds to a cross-sectional view 100A of the source bar cell 102 in a first direction (e.g., Y-direction), while fig. 1B corresponds to a cross-sectional view 100B of the source bar cell 102 in a second direction (e.g., X-direction) orthogonal to the first direction. Fig. 1C corresponds to a top layout of source bar cells 102. For example, fig. 1A and 1B may be taken along line a in fig. 1C and line B in fig. 1C, respectively. The memory device may be, for example, part of an Integrated Circuit (IC) chip or some other suitable semiconductor structure. Further, the memory device may be, for example, a third generation super flash (ESF3) memory device or some other suitable split gate flash memory device.
The source bar cell 102 is located above an active region 104a of the substrate 104 and is defined in part by a source line 106, an EG line 108, and a CG line 110 extending in parallel. For example, the various lines may be elongated in parallel along columns of the memory array. The active region 104a of the substrate 104 is a top region of the substrate 104 surrounded and bounded by the trench isolation structure 112. The trench isolation structure 112 may be or include, for example, silicon oxide and/or some other suitable dielectric. Furthermore, the trench isolation structure 112 may be or include, for example, a Shallow Trench Isolation (STI) structure or some other suitable trench isolation structure. The substrate 104 may be, for example, a bulk monocrystalline silicon substrate, a silicon-on-insulator (SOI) substrate, or some other suitable semiconductor substrate.
The source line 106 and the EG line 108 are located between the CG line 110, and the EG line 108 is located above the source line 106 while being spaced apart from the source line 106 by a source dielectric layer 114. Further, CG lines 110 are respectively located above floating gates 116 and separated from EG lines 108 and breaks 118 in source dielectric layer 114 by main sidewall spacers 120. The break 118 separates (or breaks) the EG line 108 into individual EG segments along the length of the EG line 108. Silicide layers 122 are located on the EG line 108 and the source line 106, respectively, and contact vias 124 extend to the silicide layers 122, respectively. The silicide layer 122 provides a low resistance electrical coupling from the contact via 124 to the EG line 108 and source line 106, respectively.
As will be seen below, the source bar cell 102 may be formed using, for example, an enhanced method of opening the source line 106 (e.g., for forming a break 118 in the EG line 108 and the source dielectric layer 114). Instead of using a photolithography/etching process dedicated to cleaning the source dielectric layer 114 at the break 118, the enhancement method thins the source dielectric layer 114 while cleaning the EG line 108 at the break 118 and etches through the source dielectric layer 114 when patterning a photoresist protection dielectric (RPD) layer (not shown) used during formation of the source silicide layer 122 a. Thus, the enhancement method can use one less photomask. Using less than one photomask can save a significant amount of cost due to the high cost of forming the photomask and the high cost of using the photolithographic processing tool. In addition, because one less photomask may be used, the risk of photoresist scum on the source line 106 may be reduced. The reduced risk of scum may expand the process window for forming the source silicide layer 122a and the source contact via 124a on the source silicide layer 122a (e.g., making the process more flexible). Thus, the reduced risk of scum may reduce the likelihood of the source contact via 124a failing to electrically couple to the source silicide layer 122a properly. Too much scum on the source silicide layer 122a may prevent the source silicide layer 122a from forming completely on the source lines 106, such that the source silicide layer 122a may be smaller and/or non-existent. Therefore, the source contact via 124a may not be fully bonded on the source silicide layer 122a, and the resistance from the source contact via 124a to the source line 106 may be high. Such high resistance may in turn cause the operating parameters of the memory device to go out of specification and/or result in low yield.
By opening the source line 106 according to an enhancement method, main sidewall spacers 120 are located over the thinned portion of the source dielectric layer 114 in fig. 1A. Thus, the height H of the main sidewall spacers 120sGreater than the original height of fig. 1A. In some embodiments, the height H of the primary sidewall spacers 120sAbout 400-800 angstroms, about 400-600 angstroms, about 600-800 angstroms, or some other suitable value. Further, by opening the source line 106 according to the enhancement method, the width W of the source silicide layer 122asMay be larger than the original width in fig. 1B. Further, the ratio of the width Ws to the interval S between EG segments of the EG line 108 may be greater than what it would be in fig. 1B. In this way, the likelihood of the source contact via 124a being properly bonded to the source silicide layer 122a is increased. This enlarges the process window for forming the source contact via 124a and reduces the likelihood that the source contact via 124a will not be properly electrically coupled to the source contact via 124 a.
In some embodiments, the width W of the source silicide layer 122asAbout 800-1100 angstroms, about 800-950 angstroms, about 950-1100 angstroms, or some other suitable value. If the width W issToo small (e.g., less than about 800 angstroms or some other suitable value), the likelihood of the source contact via 124a properly engaging the source silicide layer 122a may be low. As such, the process window for forming the source contact via 124a may be smaller, and the likelihood of high resistance or absence of electrical coupling between the source contact via 124a and the source line 106 may be higher. If the width W issToo large (e.g., greater than about 1100 or some other suitable value), the memory device is exposed in the process window of the source contact via 124aScaling down may be hindered with little gain.
In some embodiments, the width WsA ratio to spacing S greater than about 0.4: 1.0, about 0.5: 1.0, about 0.6: 1.0 or some other suitable ratio. In some embodiments, the width WsThe ratio to the spacing S is about 0.4: 1.0 to about 0.6: 1.0, about 0.6: 1.0 to 0.8: 1.0 or some other suitable ratio. If the ratio is too low (e.g., less than about 0.4: 1.0 or some other suitable ratio), the source silicide layer 122a may be smaller and the likelihood of the source contact via 124a being properly bonded on the source silicide layer 122a may be lower.
With continued reference to fig. 1A-1C, the source line 106 may be or include, for example, a doped portion of the substrate 104 and/or some other suitable semiconductor region. The EG line 108, CG line 110, and floating gate 116 may be or include, for example, doped polysilicon and/or some other suitable conductive material. The silicide layer 122 may be or include, for example, a metal silicide and/or some other suitable silicide. The contact vias 124 may be or include, for example, a metal and/or some other suitable conductive material. The source dielectric layer 114 may be or include, for example, silicon oxide and/or some other suitable dielectric.
CG lines 110 are separated from floating gates 116 by respective CG dielectric layers 126, and floating gates 116 are separated from substrate 104 by respective floating gate dielectric layers 128. Further, the CG lines 110 are separated from the main side wall spacers 120 by respective CG sidewall spacers 130, and the floating gates 116 are separated from the main side wall spacers 120 by respective EG tunnel dielectric layers 132. In some embodiments, the EG tunnel dielectric layer 132 and the source dielectric layer 114 are defined by a common layer. The CG dielectric layer 126 and CG sidewall spacers 130 may be or include, for example, silicon oxide, silicon nitride, some other suitable dielectric, or any combination of the preceding. In some embodiments, as shown, the CG dielectric layer 126 and CG sidewall spacers 130 are oxide-nitride-oxide (ONO) films. The floating gate dielectric layer 128 and the EG tunnel dielectric layer 132 may be or include, for example, silicon oxide and/or some other suitable dielectric.
An interconnect dielectric layer 134 covers the source bar cells 102 and fills the break 118 in the EG line 108 and the source dielectric layer 114. Furthermore, an interconnect dielectric layer 134 surrounds the contact via 124. The interconnect dielectric layer 134 may be or include, for example, silicon oxide and/or some other suitable dielectric.
Although fig. 1A-1C are described together with respect to the same memory device, each of fig. 1A-1C is individually independent of the other of fig. 1A-1C. For example, the memory device may have the cross-sectional view 100A of fig. 1A, but may not have the cross-sectional view 100B of fig. 1B and/or the top layout 100C of fig. 1C. As another example, the memory device may have the cross-sectional view 100B of fig. 1B, but may not have the cross-sectional view 100A of fig. 1A and/or the top layout 100C of fig. 1C.
Referring to fig. 2A, an enlarged cross-sectional view 200A of some embodiments of the source bar cell 102 of fig. 1A is provided, wherein the source bar cell 102 is further defined in part by an SG line 202. The SG lines 202 are elongated in parallel with the CG lines 110 (not visible in the sectional view 200A), and the CG lines 110 are located between the SG lines 202 and are respectively adjacent to the SG lines 202. Furthermore, SG line 202 partially overlies trench isolation structure 112 and is separated from substrate 104 by a respective SG dielectric layer 204. The SG line 202 may be or include, for example, doped polysilicon and/or some other suitable conductive material. SG dielectric layer 204 may be or include, for example, silicon oxide and/or some other suitable dielectric.
CG sidewall spacers 130 and SG sidewall spacers 206 separate CG line 110 from SG line 202, respectively. CG sidewall spacer 130 is located on the sidewall of CG line 110, while SG sidewall spacer 206 is located on the sidewall of SG line 202 facing CG line 110. Further, primary side wall spacers 120 are located on the side walls of the SG line 202 facing away from the CG line 110. SG sidewall spacers 206 may be or include, for example, silicon oxide and/or some other suitable dielectric. In some embodiments, CG sidewall spacers 130 are or comprise ONO film, SG sidewall spacers 206 are or comprise silicon oxide, and main sidewall spacers 120 are or comprise silicon nitride. However, other materials are suitable for one or any combination of the above-described spacers.
Silicide layer 122 is situated on SG line 202 to provide a low resistance electrical coupling from SG line 202 to an SG contact via (not shown). Furthermore, a Contact Etch Stop Layer (CESL)208 is located on the main sidewall spacers 120 and the source silicide layer 122a, and a source contact via 124a extends from the source line lead 210a through the CESL208 to the source silicide layer 122 a. The source line lead 210a is located in the interconnect dielectric layer 134 and may be or include, for example, a metal and/or some other suitable conductive material. CESL208 may be or include, for example, silicon oxide, silicon nitride, some other suitable dielectric, or any combination of the preceding.
Referring to fig. 2B, a cross-sectional view 200B of some alternative embodiments of the source bar cell 102 of fig. 2A is provided, where the lowest point of the main sidewall spacers 120 between CG lines 110 is at the same level as the floating gate 116 and/or floating gate dielectric layer 128.
Referring to fig. 2C, a cross-sectional view 200C of some alternative embodiments of the source bar cell 102 of fig. 2A is provided, wherein SG line 202 is located at a side of trench isolation structure 112. In other words, the SG line 202 does not cover the trench isolation structure 112.
Referring to fig. 2D, a cross-sectional view 200D of some alternative embodiments of the source bar cell 102 of fig. 2C is provided, wherein a common dielectric structure 212 surrounds the source bar cell 102 and separates the constituent parts of the source bar cell 102. Wherein the common dielectric structure 212 surrounds and separates the floating gate 116, the CG line 110, the silicide layer 122, the CESL208, the sidewall spacers 214, and the gate dielectric layer 216. In addition, the common dielectric structure 212 defines an integral part of the source bar cell 102. Wherein the common dielectric structure 212 defines the trench isolation structure 112 and the floating gate dielectric layer 128. The common dielectric structure 212 may be or include, for example, silicon oxide and/or some other suitable dielectric. The sidewall spacers 214 and/or the gate dielectric layer 216 may be or include, for example, silicon nitride and/or some other suitable dielectric.
Although not labeled to simplify fig. 2D, it is to be understood that the common dielectric structure 212 and the sidewall spacers 214 may, for example, collectively define the CG sidewall spacers 130 of fig. 2C. For example, the common dielectric structure 212 and the sidewall spacers 214 may collectively define an ONO film corresponding to the CG sidewall spacers 130 of fig. 2C. Further, the common dielectric structure 212 and the gate dielectric layer 216 may, for example, collectively define the CG dielectric layer 126 of fig. 2C. For example, the common dielectric structure 212 and the gate dielectric layer 216 may collectively define an ONO film corresponding to the CG dielectric layer 126 of fig. 2C.
Referring to fig. 3A, an enlarged cross-sectional view 300A of some embodiments of the source bar cell 102 of fig. 1B is provided, wherein the contact vias 124 respectively extend from the leads 210 to the silicide layers 122, respectively. Furthermore, CESL208 is located on the main sidewall spacers 120, and the source contact via 124a extends through the CESL 208. The leads 210 are located in the interconnect dielectric layer 134 and may be or include, for example, a metal and/or some other suitable conductive material.
Referring to fig. 3B, a cross-sectional view 300B of some alternative embodiments of the source bar cell 102 of fig. 3A is provided, wherein the common dielectric structure 212 surrounds and separates the constituent parts of the source bar cell 102. Wherein a common dielectric structure 212 surrounds and separates the EG line 108, the silicide layer 122, the main sidewall spacers 120, and the CESL 208. In addition, the common dielectric structure 212 defines an integral part of the source bar cell 102. Wherein the common dielectric structure 212 defines the source dielectric layer 114.
Referring to fig. 4, an enlarged top layout 400 of some embodiments of the source bar cell 102 of fig. 1C is provided, where the SG line 202 is laterally elongated parallel to the CG line 110 and the EG line 108. Further, the SG line 202, the CG line 110, and the EG line 108 overlap the trench isolation structure 112 and the active region 104a, and the trench isolation structure 112 surrounds and divides the active region 104 a. Any of the cross-sectional views 100A, 200A-200D of fig. 1A and 2A-2D may be taken along line a, and/or any of the cross-sectional views 100B, 300A, 300B of fig. 1B, 3A, and 3B may be taken along line B, for example.
Referring to fig. 5, a cross-sectional view 500 of some embodiments of a memory device including source bar cells 102 and CG bar cells 502 is provided. The memory device may be, for example, part of an IC chip or some other suitable semiconductor structure. Further, the memory device may be, for example, an ESF3 memory device or some other suitable split gate flash memory device.
The source bar cells 102 and CG bar cells 502 are located over the trench isolation structures 112 and the active area 104a of the substrate 104. Furthermore, the source bar cell 102 and the CG bar cell 502 are defined in part by the source line 106, EG line 108, CG line 110, and SG line 202 elongated in parallel (not visible in the cross-sectional view 500 of fig. 5). The source bar cell 102 is as shown and described in fig. 2A, but may alternatively be as shown and described in any one or combination of fig. 1A-1C, 2B-2D, 3A, 3B, and 4, or any other suitable source bar cell, for example.
The source lines 106 are respectively contiguous with the CG lines 110 on a first side of the CG lines 110, and the EG lines 108 are respectively located above the source lines 106 while remaining spaced apart from the source lines 106 by a source dielectric layer 114. Note that the source dielectric layer 114 of the source bar cell 102 is partially removed, while the source dielectric layer 114 of the CG bar cell 502 is intact. Further, the SG lines 202 are respectively adjacent to the CG lines 110 on the second sides of the CG lines 110, and the CG lines 110 are respectively located above the floating gates 116. The EG line (not visible) of the source bar cell 102 and the source dielectric layer 114 of the source bar cell 102 have a first break 118 at the source bar cell 102, and the SG line (not visible) of the CG bar cell 502 has a second break 504 at the CG bar cell 502.
As seen below, the source bar cells 102 may be formed by an enhanced method for opening the source lines 106, for example. During the enhancement method, the first lithography/etch process clears the EG line of the source bar cell at the first break 102 while clearing the SG line of the CG bar cell 502 at the second break 504. Furthermore, instead of using a second lithography/etch process dedicated to clearing the source dielectric layer 114 at the first discontinuity 118, the enhancement method thins the source dielectric layer 114 of the source bar cell 102 during the first lithography/etch process and etches through the remaining portion of the source dielectric layer while patterning the RPD layer (not shown) used during formation of the silicide layer 122 at the first discontinuity 118. In this way, the first lithography/etching process is extended.
Because the first photolithography/etching process is extended and performed on the SG line 202 of the CG stripe unit 502, the first photolithography/etching process extends into the substrate 104 and the trench isolation structure 112 at the CG stripe unit 502. This in turn forms a recess 506 having a depth D, as measured from the top surface of the substrate 104. In some embodiments, the depth D is greater than about 50 angstroms or greater than about 100 angstroms and/or less than about 200 angstroms, less than about 250 angstroms, or less than about 300 angstroms. However, other suitable values are acceptable. If the depth D is too large (e.g., greater than about 300 angstroms or some other suitable value), metal may be trapped in the recess 506. Such trapped metal may cause contamination of the process tool, undesirable electrical shorts, or other suitable challenges. If the depth D is too small (e.g., less than about 50 angstroms or some other suitable value), the source dielectric layer 114 of the source bar cells 102 may not be thin enough and the patterning of the RPD layer may not be able to etch through the remaining portion of the source dielectric layer. As such, the contact via 124 of the source bar cell 102 may not be electrically coupled to the source line 106 of the source bar cell 102.
With continued reference to fig. 5, CG line 110 is separated from trench isolation structure 112 and floating gate 116, respectively, by a respective CG dielectric layer 126. In addition, the floating gates 116 are separated from the substrate 104 by respective floating gate dielectric layers 128, and the SG lines 202 are separated from the substrate 104 by respective SG dielectric layers 204. The CG line 110 is separated from the EG line 108 and the SG line 202 by respective CG sidewall spacers 130. The CG line 110 is further separated from the EG line 108 by a respective EG tunnel dielectric layer 132, and from the SG line 202 by a respective SG sidewall spacer 206. CG sidewall spacers 130 are located on the sidewalls of CG line 110, EG tunnel dielectric layer 132 is located on the sidewalls of floating gate 116 and EG line 108, and SG sidewall spacers 206 are located on the sidewalls of SG line 202.
CESL208 lines the outer sidewalls of source bar cells 102 and CG bar cells 502, and main sidewall spacers 120 separate CESL208 from the outer sidewalls, respectively. The silicide layer 122 is located on the SG line 202, the EG line 108, and the source line 106 of the source stripe cell 102, respectively. The source line leads 210a and the source contact vias 124a are located above the silicide layers 122 of the source bar cells 102, and the source contact vias 124a extend from the source line leads 210a to the silicide layers 122 of the source bar cells 102. An interconnect dielectric layer 134 covers the source bar elements 102 and CG bar elements 502. Further, an interconnect dielectric layer 134 fills the first and second breaks 118, 504 and surrounds the source line lead 210a and the source contact via 124 a.
Referring to fig. 6A and 6B, various cross-sectional views 600A, 600B of some alternative embodiments of GC bar unit 502 of fig. 5 are provided, in which recess 506 is substantially defined by substrate 104 and trench isolation structure 112 is located substantially below CG line 110. In fig. 6A, the trench isolation structure 112 is adjacent to the second discontinuity 504 and the recess 506. In fig. 6B, the trench isolation structure 112 is adjacent to the EG line 108.
Referring to fig. 7, a top layout 700 of some embodiments of GC bar unit 502 of fig. 5 is provided. For example, GC strip cells 502 of FIG. 5 may be cut along line C, but other suitable locations are possible. In an alternative embodiment, the GC bar cell 502 in either of fig. 6A and 6B may be truncated along line C, for example, by modifying the top layout of the trench isolation structure 112 and the top layout of the active region 104 a. The CG line 110, the EG line 108, and the SG line 202 are laterally elongated in parallel and overlap the trench isolation structure 112 and the active region 104 a. Further, one of the CG lines 110 has a pad 110p at the break 504, a groove 506 surrounds the pad 110p, and a contact via 124 extends from the pad 110p to electrically couple the pad 110p to a metal line (not shown). In some embodiments, the groove 506 is U or C shaped. In alternative embodiments, the groove 506 has some other suitable shape.
Referring to fig. 8, a schematic top view 800 of some embodiments of a memory device including a memory array is provided in which the source bar cells 102 of fig. 5 and the GC bar cells 502 of fig. 5 are arranged. The memory array includes a plurality of cells in a plurality of rows and a plurality of columns. Marking rows as R, respectivelyxTo Rx+7And the columns are respectively marked as CmTo Cm+2、CnTo Cn+2、CoTo Co+2And CpTo Cp+2. The row and column labeled subscripts identify the corresponding row and column numbers. Further, x is an integer variable representing a row number, and m, n, o, and p are integer variables representing a column number.
The plurality of cells includes a plurality of source bar cells 102, a plurality of CG bar cells 502, and a plurality of memory cells 802 repeated along each row. In some embodiments, the plurality of cells further includes SG strip cells and/or other types of strip cells not shown. The source bar cell 102 electrically couples a source line (not shown) and an EG line (not shown) to a corresponding source bar line 804 and a corresponding EG bar line 806. As such, the source bar cells 102 may also be referred to as source/erase gate (SEG) bar cells, for example. CG bar element 502 electrically couples CG lines (not shown) to corresponding CG bar lines 808. The CG line, the EG line, and the source line extend along the row and partially define a plurality of cells. Memory cell 802 stores individual bits of data and may be, for example, an ESF3 memory cell, a split gate flash memory cell, or some other suitable memory cell. The source bar cell 102 may, for example, be the same as any one or combination of fig. 1A-1C, 2A-2D, 3A, 3B, 4, and 5, and/or the GC bar cell 502 may, for example, be the same as any one or combination of fig. 5, 6A, 6B, and 7.
The interconnect structure interconnects the plurality of cells and includes a plurality of leads 210 and a plurality of vias 810. Note that leads 210 and vias 810 are labeled only in the legend below the memory array. Leads 210 are grouped into multiple lead levels and vias 810 are grouped into multiple via levels. When the memory device is viewed in cross-section, the levels correspond to heights above the memory array. The plurality of lead levels includes a first lead level M1, a second lead level M2, a third lead level M3, and a fourth lead level M4. The level of wiring is schematically illustrated by the thickness of the wiring 210, and the height above the memory array increases with the thickness of the wiring. The plurality of via levels includes a contact via level CO (e.g., a zero via level), a first via level V1, a second via level V2, and a third via level V3. The via level is schematically shown by shape and/or color. For example, black circles correspond to contact vias 124 in the contact via level CO, while white squares correspond to vias in the second via level V2.
Vias in the contact via level CO extend from the cell to the leads in the first lead level M1, and vias in the first via level V1 extend from wires in the first lead level M1 to leads in the second lead level M2. Further, vias in the second via level V2 extend from wires in the second wire level M2 to wires in the third wire level M3, and vias in the third via level V3 extend from wires in the third wire level M3 to wires in the fourth wire level M4. Note that vias at different levels directly overlap, with intermediate leads not shown.
The plurality of leads 210 includes a plurality of bit lines 812, a plurality of source shunt leads 814, and a plurality of EG shunt leads 816 in the first steering line level Ml. Bit line 812 follows the column in which memory cell 802 is located (e.g., column C)m、Cm+2、Cn+2、CoEtc.) and are electrically coupled to the memory cells in the respective column by vias in the contact via level CO. Source and EG shunt lines 814, 816 run along the column in which source bar cell 102 is located (e.g., column C)m+1And Co+1) Extend, and are electrically coupled to source lines (not shown) and EG (not shown) at source bar cells 102, respectively, by contact vias in contact via level CO.
In addition, the plurality of leads 210 includes a source line 804, an EG line 806, and a CG line 808. The source and EG lines 804, 806 are located in the fourth lead level M4 and are electrically coupled to the source and EG shunt lines 814, 816, respectively, through vias in the first, second and third via levels V1, V2 and V3. The CG line 808 is located in the third wiring level M3 and is electrically coupled to CG lines (not shown) in respective rows at the CG bar cell 502 by contact via levels CO and contact vias in the first and second via level V1, V2.
Although fig. 8 shows the various lines and various shunt lines at certain lead levels, in alternative embodiments, some or all of the lines and/or some or all of the shunt lines may be at different lead levels. For example, in an alternative embodiment, CG line 808 may be located in the second lead level M2. As another example, in an alternative embodiment, the EG line 806 may be located in the fourth lead level M4 and the source line 804 may be located in the fifth lead level (not shown), or vice versa.
Referring to FIG. 9, the memory array of FIG. 8 is providedTop layout 900 of some embodiments of a portion of a column. The top layout 900 may be, for example, taken within box E in fig. 8, but other suitable locations are possible. The plurality of EG lines 108, the plurality of CG lines 110, and the plurality of SG lines 202 are laterally elongated in parallel and partially define a plurality of cells in a plurality of rows and columns. Marking rows as R, respectivelyyTo Ry+3And the columns are respectively marked as CqTo Cq+7. The row and column labeled subscripts identify the corresponding row and column numbers. Further, y is an integer variable representing a row number, and q is an integer variable representing a column number.
The plurality of cells includes a plurality of source bar cells 102, a plurality of CG bar cells 502, and a plurality of memory cells 802. The plurality of cells overlap the active region 104a and the trench isolation structure 112 surrounding and dividing the active region 104 a. Further, the plurality of cells are electrically coupled to respective leads (not shown; see, e.g., FIG. 8) through respective contact vias 124. The source bar cell 102 may be, for example, the same as any one or combination of fig. 1A-1C, 2A-2D, 3A, 3B, 4, and 5. For example, any of fig. 1A and 2A-2D may be taken along line a, and/or any of fig. 1B, 3A, and 3B may be taken along line B, for example. Furthermore, the source bar cell 102 of fig. 5 may be taken, for example, along line a. The CG bar element 502 may be, for example, as in any one or combination of fig. 5, 6A, 6B, and 7, and/or any one of fig. 6A and 6B may be, for example, taken along line C. Further, the CG bar element 502 of fig. 5 may be taken, for example, along line C.
Referring to fig. 10-13 and 16-24, a series of cross-sectional views 1000, 1600, 2400 of some embodiments of methods for forming a memory device including source bar cells and CG bar cells in accordance with aspects of the present invention are provided. The method is used to form the memory device of fig. 5, but may alternatively be used to form the memory device in any one or combination of fig. 1A-1C, 2A-2D, 3A, 3B, 4, 6A, 6B, and 7-9, or to form some other suitable memory device, for example.
As shown in the cross-sectional view 1000 of fig. 10, the source bar cells 102 and CG bar cells 502 are partially formed on the trench isolation structures 112 and the active area 104a of the substrate 104. The trench isolation structure 112 surrounds and divides the active region 104 a. The source bar cell 102 and the CG bar cell 502 are defined in part by the parallel elongated source line 106, EG line 108, CG line 110 and SG line 202 (not visible in cross-sectional view 1000). In some embodiments, the source bar cell 102 has the top layout of fig. 4, minus the contact via 124 and the break 118, such that the EG line 108 of the source bar cell 102 is continuous. In some embodiments, the CG strip cell 502 has the top layout in fig. 7, minus the contact vias 124 and breaks 504, such that the SG line 202 of the CG strip cell 502 is continuous. However, other suitable top layouts are suitable for source bar cells 102 and/or CG bar cells 502.
The SG lines 202 are respectively adjacent to the CG lines 110 on a first side of the CG lines 110, and the CG lines 110 are respectively located above the floating gates 116. Further, the source lines 106 adjoin the CG lines 110, respectively, on a second side of the CG lines 110, and the EG lines 108 overlie the source lines 106, respectively, while remaining spaced apart from the source lines 106 by a source dielectric layer 114. The source dielectric layer 114 has a spherical or elliptical cross-sectional profile, but other profiles are possible. In some embodiments, the individual height H of the source dielectric layer 114dAbout 300-500 angstroms, about 300-400 angstroms, about 400-500 angstroms, or some other suitable value. In some embodiments, the individual width Wd of the source dielectric layer 114 is about 500-800 angstroms, about 500-650 angstroms, about 650-800 angstroms, or some other suitable value.
CG line 110 is separated from trench isolation structure 112 and floating gate 116 by respective CG dielectric layers 126, and floating gate 116 is separated from substrate 104 by respective floating gate dielectric layers 128. Further, SG lines 202 are separated from substrate 104 by respective SG dielectric layers 204. The CG line 110 is separated from the EG line 108 and the SG line 202 by respective CG sidewall spacers 130. The CG line 110 is further separated from the EG line 108 by a respective EG tunnel dielectric layer 132, and from the SG line 202 by a respective SG sidewall spacer 206.
The CG hard masks 1002 cover the CG lines 110, respectively, and the SG hard masks 1004 cover the SG lines 202, respectively. In addition, the EG hard masks 1006 cover the EG lines 108, respectively. The EG hard mask 1006 and/or the SG hard mask 1004 may be or include, for example, silicon nitride and/or some other suitable dielectric. The CG hard mask 1002 may be or include, for example, silicon oxide, silicon nitride, some other suitable dielectric, or any combination of the preceding. In some embodiments, as shown, the CG hard mask 1002 is or includes a nitride-oxide-nitride (NON) film.
As shown in the cross-sectional view 1100 of fig. 11, a first mask 1102 is formed to partially cover the source bar cells 102 and the CG bar cells 502. In some embodiments, the first mask 1102 is or includes photoresist and/or some other suitable mask material. Further, in some embodiments, the first mask 1102 is formed by photolithography and/or some other suitable process for forming the first mask 1102.
Also shown by the cross-sectional view 1100 of fig. 11, a sacrificial layer 1104 is formed to fill the gaps between CG bar elements 502 (see, e.g., fig. 10). The sacrificial layer 1104 may be, for example, may be or include a bottom anti-reflective coating (BARC) and/or some other suitable sacrificial material. In some embodiments, the sacrificial layer 1104 is formed of a material that is flowable and self-leveling under the force of gravity, so the top surface of the sacrificial layer 1104 is flat or substantially flat. The process of forming the sacrificial layer 1104 may include, for example, depositing the sacrificial layer 1104 by spin coating, followed by etching back the sacrificial layer 1104 until the top surface of the sacrificial layer 1104 is approximately flush with the top surface of the CG hard mask 1002. However, other suitable processes may be employed to form sacrificial layer 1104.
As shown in the cross-sectional view 1200 of fig. 12, a first etch is performed on the source and CG bar cells 102, 502 with a first mask 1102 in place. The first etch may, for example, comprise or be performed by an anisotropic etch, a dry etch, some other suitable type of etch, or any combination of the preceding.
The first etch stops on the source dielectric layer 114 of the source bar cells 102 and further stops on the portion of the substrate 104 between the CG bar cells 502. Furthermore, in some embodiments, the first etch stops on portions of the trench isolation structures 112 between the second stripe of cells 502. In some embodiments, source dielectric layer 114 and trench isolation structure 112 are or comprise silicon oxide and/or are or comprise the same material. In some embodiments, the etchant employed for the first etch has a high selectivity (e.g., a high etch rate) for the material of the EG and SG lines 108, 202 relative to the material of the source dielectric layer 114 and/or the material of the substrate 104.
The first etching forms: 1) a first opening 1202 through the EG line 108 (see, e.g., fig. 11) of the source bar cell 102; 2) a second opening 1204 through the SG line 202 (see, e.g., fig. 11) of the CG strip unit 502. Further, the first etch completely or substantially removes the sacrificial layer 1104 (see, e.g., fig. 11) and partially removes some of the dielectric layer in the first opening 1202 and the second opening 1204. For example, SG sidewall spacers 206 of CG stripe cells 502 are thinned or partially removed.
The sacrificial layer 1104 protects the substrate 104 between the CG strip units 502 so that the substrate 104 is not exposed to the etchant for the entire duration of the first etch. If the substrate 104 is exposed to an etchant, deep grooves may be formed that would trap the metal. Such trapped metal is difficult to remove and may therefore lead to process tool contamination, undesirable electrical shorts, or other suitable challenges.
As shown in cross-sectional view 1300 of fig. 13, the second etch is performed with the first mask 1102 in place. A second etch is performed on the exposed portions of the substrate 104 between the source dielectric layer 114 of the source bar cells 102 and the CG bar cells 502. In some embodiments, a second etch is also performed on the exposed portions of the trench isolation structures 112 between the CG stripe cells 502. In some embodiments, the second etch uses an etchant that is different from the etchant used for the first etch and/or has a high selectivity (e.g., a high etch rate) to the material of the source dielectric layer 114 and/or the material of the substrate 104 relative to the surrounding structures. As with the first etch, the second etch may, for example, comprise or be performed by an anisotropic etch, a dry etch, some other suitable type of etch, or any combination of the foregoing.
In some embodiments, the first etch and the second etch are performed in-situ. In other words, the first etch and the second etch are performed within a common process chamber such that the substrate 104 is located within the common process chamber continuously from the beginning of the first etch to the end of the second etch. In an alternative embodiment, the first and second embodiments are performed in different process chambers.
The second etch thins the exposed portions of the CG hard mask 1002. In some embodiments where the CG hard mask 1002 is or includes a NON film, the second etch stops on the oxide layer of the NON film before reaching the bottom nitride layer of the NON film. The second etch thins the source dielectric layer 114 of the source bar cells 102. Thus, the height H of the source dielectric layer 114 of the source bar cell 102dLess than the height before thinning. In addition, the second etch planarizes the source dielectric layer 114 of the source bar cells 102 such that the top surface of the source dielectric layer is flatter than before the second etch. For example, the difference between the highest point on the top surface and the lowest point on the top surface may be less than the difference before the second etching. The second etch extends into the substrate 104 and the trench isolation structures 112 to form recesses 506 between the CG stripe cells 502. The recess 506 has a depth D, measured from the top surface of the substrate 104, and may, for example, have the top layout in fig. 7. For example, the grooves 506 may have a C-shaped or U-shaped top layout. However, other suitable top layouts are also possible.
In some embodiments, height HdAbout 300-500 angstroms, about 300-400 angstroms, about 400-500 angstroms or some other suitable values before the second etch, and/or about 100-200 angstroms, about 100-150 angstroms, about 150-200 angstroms or some other suitable values after the etch. If the height H after the second etchingdToo small (e.g., less than about 100 angstroms or some other suitable value), the depth D may be too large. This may result in metal being trapped, as described below. If the height H after the second etchingdToo large (e.g., greater than about 200 angstroms or some other suitable value), the subsequently described RPD etch may not extend the first opening 1202 through the source dielectric layer of the source bar cell 102114. This may in turn reduce the process window for forming silicide and/or contact vias on the source dielectric layer 114 of the source bar cells 102.
In some embodiments, the depth D is greater than about 50 angstroms or greater than about 100 angstroms and/or less than about 200 angstroms, less than about 250 angstroms, or less than about 300 angstroms. However, other suitable values are possible. If the depth D is too large (e.g., greater than about 300 angstroms or some other suitable value), metal may be trapped in the recess 506. Such trapped metal may cause contamination of the process tool, undesirable electrical shorts, or other suitable challenges. If the depth D is too small (e.g., less than about 50 angstroms or some other suitable value), the source dielectric layer 114 of the source bar cell 102 may not be thin enough at the first opening 1202 and the height HdMay be too large (see above).
Referring to fig. 14A and 14B, cross-sectional views 1400A, 1400B of some alternative embodiments of the source bar cell 102 of fig. 13 are provided. In fig. 14A, the active region 104A of the substrate 104 and the trench isolation structure 112 have different layouts such that the SG line 202 is located substantially at the side of the trench isolation structure 112. In fig. 14B, a common dielectric structure 212 surrounds and separates the constituent parts of the source bar cells 102. Wherein the common dielectric structure 212 surrounds and separates the floating gate 116, the CG line 110, the sidewall spacer 214, the gate dielectric layer 216 and the hard mask 1402. In addition, the common dielectric structure 212 defines an integral part of the source bar cell 102. Wherein the common dielectric structure 212 defines the source dielectric layer 114 and the trench isolation structure 112. Hard mask 1402 may be or include, for example, silicon nitride and/or some other suitable dielectric.
Referring to fig. 15A and 15B, cross-sectional views 1500A, 1500B of some embodiments of the source bar cell 102 of fig. 13 are provided in a direction orthogonal to the direction of the cross-sectional view 1300 of fig. 13. For example, fig. 15A and 15B may be in the X direction, and fig. 13 may be in the Y direction. In fig. 15A, the EG line 108 is recessed relative to the EG hard mask 1006 and the source dielectric layer 114 is indented where it is not covered by the EG hard mask 1006 and the first mask 1102. In fig. 15B, the corners are more rounded and the straightness of the surface is lower.
In some embodiments, the source bar cell 102 of fig. 15A and 15B is taken along line B in any one or combination of fig. 1C, 4, and 9, and the source bar cell 102 of fig. 13 is taken along line B in any one or combination of fig. 1C, 4, and 9. Further, in some embodiments, the cross-sectional views 1500A, 1500B of fig. 15A and 15B optionally correspond to fig. 14A and/or 14B instead of fig. 13.
Referring back to fig. 10-13 and 16-24 and the series of cross-sectional views 1000, 1600, 2400 shown thereby, the first mask 1102 (see, e.g., fig. 13) is removed at the cross-sectional view 1600 of fig. 16. The removal may be performed, for example, by plasma ashing and/or other suitable removal processes.
As also shown in cross-section 1600 of fig. 16, the source and CG bar elements 102, 502 are thinned and their top surfaces flattened to about level. This includes thinning the SG hard mask 1004, CG hard mask 1002, and EG hard mask 1006 and planarizing the top surface of the hard mask. In some embodiments, the process for performing thinning and flattening comprises: 1) depositing a sacrificial layer covering the source and CG bar elements 102, 502; 2) etching back the sacrificial layer in parallel with the source and CG stripe cells 102, 502; and 3) removing the sacrificial layer. However, other processes are also possible. The sacrificial layer has a planar or substantially planar top surface and may, for example, be or include BARC and/or some other suitable sacrificial material. In some embodiments, the sacrificial layer is formed from a flowable material that is self-leveling under the force of gravity, so that the top surface of the sacrificial layer is flat or substantially flat. The process for forming the sacrificial layer may, for example, comprise depositing the sacrificial layer by spin coating. However, other processes are also possible.
As shown in the cross-sectional view 1700 of fig. 17, the main sidewall spacers 120 are formed on the outer sidewalls of the source and CG strip cells 102, 502 and line the sidewalls of the source and CG strip cells 102, 502 at the first and second openings 1202, 1204. In some embodiments, the process for forming the main sidewall spacers 120 includes: 1) depositing a spacer layer covering the source and CG bar elements 102, 502 and lining sidewalls of the source and CG bar elements; and 2) performing an etch back on the spacer layer to remove the horizontal segments but not the vertical segments. However, other processes are also possible.
Because the source dielectric layer 114 of the source bar cell 102 is thinned only at the first opening 1202, the main sidewall spacers 120 in the first opening 1202 overlie the source dielectric layer. In some embodiments, the main sidewall spacers 120 in the first opening 1202 have a bottom surface that rises above the highest point of the substrate 104. Furthermore, in some embodiments, the main sidewall spacers 120 in the first opening 1202 have bottom surfaces that are raised above the bottom surface of the floating gate 116 and/or are respectively recessed relative to the top surface of the floating gate 116. Since the main side wall spacers 120 in the first opening 1202 are located above the source dielectric layer 114 of the source bar cell 102, the height H of the main side wall spacerss1Less than if the first opening 1202 extended through the source dielectric layer prior to formation.
Because the grooves 506 extend into the substrate 104 and the trench isolation structures 112 between the CG strip cells 502, the main side wall spacers 120 between the CG strip cells 502 also extend into the substrate 104 and the trench isolation structures 112. Because the main side wall spacers 120 between the CG stripe cells 502 extend into the substrate 104 and the trench isolation structures 112, the height H of the main side wall spacerss2Greater than if the groove 506 were not present. As described above, the groove 506 occurs because the second etch uses the first mask 1102 (see, e.g., fig. 13).
As shown in cross-section 1800 of fig. 18, a photoresist protective dielectric (RPD) layer 1802 is deposited covering the source and CG bar cells 102, 502 and further lining the sidewalls of the main sidewall spacers 120. The RPD layer 1802 may be or include silicon oxide, for example, and thus may also be an RPO layer, for example. Alternatively, RPD layer 1802 may be or include some other suitable dielectric, for example.
As shown in the cross-sectional view 1900 of fig. 19, a second mask 1902 is formed on the RDP layer 1802. The second mask 1902 is formed with an opening located over the source line 106 of the source bar cell 102. Although not visible, the second mask 1902 may, for example, further comprise additional openings. The openings of the second mask 1902 may, for example, define a silicide pattern for a subsequently formed silicide. In some embodiments, the second mask 1902 is or includes a photoresist and/or some other suitable mask material. Furthermore, in some embodiments, the second mask 1902 is formed by photolithography and/or some other suitable process for forming the second mask 1902.
As also shown in the cross-sectional view 1900 of fig. 19, with the second mask 1902 in place, a third etch is performed on the RPD layer 1802 and the source dielectric layer 114 of the source bar cell 102. The third etch extends the first opening 1202 through the source dielectric layer 114 of the source bar cell 102 to expose the source line 106 of the source bar cell 102. The third etch may, for example, comprise or be performed by an anisotropic etch, a dry etch, some other suitable type of etch, or any combination of the preceding. In some embodiments, the RPD layer 1802 and the source dielectric layer 114 of the source bar cell 102 are or include the same dielectric material such that the third etch uses a single etchant.
As described above, the second etch (see, e.g., fig. 13) thins the source dielectric layer 114 of the source bar cell 102 in the first opening 1202, and then the third etch etches through the source dielectric layer to extend the first opening 1202 to the source line 106 of the source bar cell 102. The second etch uses a first mask 1102 (see, e.g., fig. 13) of the first etch (see, e.g., fig. 12), and the third etch uses a second mask 1902 (see, e.g., fig. 19). This two-step process for exposing the source line 106 of the source bar cell 102 is in contrast to a single-step process in which the source line is exposed by a single lithography/etch process using a third mask, which is different from the first and second masks 1102, 1902.
Because the present invention uses a two-step process rather than a single-step process, the method can use one less photomask than it otherwise would. Using less than one photomask can save a significant amount of cost due to the high cost of forming the photomask and the high cost of using the photolithographic processing tool. In addition, because one less photomask may be used, the risk of photoresist errors on the source lines 106 of the source bar cells 102 is reduced. This expands the process window for forming silicide and/or contact vias on the source lines 106 of the source stripe cells 102 (e.g., making the process more flexible). Too much scum on the source lines 106 of the source bar cells 102 may prevent the silicide layer from forming completely on the source lines, so that the silicide layer may be smaller. A smaller silicide layer may reduce the likelihood of the contact via fully bonding on the silicide layer, and may therefore result in a high resistance from the contact via to the source line. Such high resistance may in turn cause the operating parameters of the memory device to go out of specification and/or result in low yield.
As described above, the second etch thins the source dielectric layer 114 of the source bar cells 102 such that the height Hd(see, e.g., fig. 13) is about 100-200 angstroms, about 100-150 angstroms, about 150-200 angstroms, or some other suitable value after etching. If the height H isdToo large (e.g., greater than about 200 angstroms or some other suitable value), the third etch may not extend the first opening 1202 through the source dielectric layer 114 of the source bar cell 102 without damaging structures (not shown) on the substrate 104. For example, a third etch may also be used to expose source/drain regions (not shown) on the substrate 104. The source/drain regions may not be covered by the source/drain dielectric layer, but only by the RDP layer 1802. Thus, extending the third etch through the source dielectric layer 114 of the source bar cell 102 may increase the exposure of the source/drain regions to the etchant during the third etch. This increased exposure, in turn, may damage the source/drain regions. If the height H isdToo large, damage may be high and thus operating parameters may deviate from specification.
As shown in the cross-sectional view 2000 of fig. 20, the second mask 1902 is removed (see, e.g., fig. 19), and a source silicide layer 122a is formed on the source lines 106 of the source bar cells 102. The removal may be performed, for example, by plasma ashing and/or other suitable removal processes. The source silicide layer 122a is formed by the following process: a silicide is formed on silicon semiconductor regions not covered by RPD layer 1802 but not on silicon semiconductor regions covered by RPD layer 1802. The process may be, for example, a salicide process or some other suitable process for forming a silicide.
As shown in the cross-sectional view 2100 of fig. 21, the RPD layer 1802 (see, e.g., fig. 20) is removed. The removal may be performed, for example, by an etching process or some other suitable etching process.
Also shown by the cross-sectional view 2100 of fig. 21, the CG hard mask 1002, SG hard mask 1004, and EG hard mask 1006 are removed. In some embodiments, the process for performing removal includes: 1) depositing a sacrificial layer covering the source and CG bar elements 102, 502; 2) etching back the sacrificial layer in parallel with the source and CG stripe cells 102, 502; and 3) removing the sacrificial layer. However, other processes are also possible. The sacrificial layer may be or comprise BARC and/or some other suitable sacrificial material, for example. In some embodiments, the sacrificial layer is formed from a flowable material that is self-leveling under the force of gravity, so that the top surface of the sacrificial layer is flat or substantially flat. The process for forming the sacrificial layer may, for example, include depositing the sacrificial layer by spin coating or other suitable process.
As shown in the cross-sectional view 2200 of fig. 22, the CESL208 and the first interconnect dielectric layer 134a are deposited to cover the source and CG stripe cells 102, 502 and to further fill the first and second openings 1202, 1204 (see, e.g., fig. 21). The first interconnect dielectric layer 134a may be or include, for example, silicon oxide and/or some other suitable dielectric.
Planarization is performed on the CESL208 and the first interconnect dielectric layer 134a, as shown in cross-sectional view 2300 of fig. 23. Planarization continues until the top surfaces of the CESL208 and the first interconnect dielectric layer 134a are substantially flush with the top surfaces of the SG line 202, the CG line 110, and the EG line 108, respectively. Planarization is performed, for example, by chemical mechanical polishing or some other suitable planarization process.
Also shown by cross-sectional view 2300 of fig. 23, CG/EG silicide layer 122b is formed on CG line 110 and EG line 108. For example, the CG/EG silicide layer 122b may be formed by a salicide process or some other suitable process.
As shown in the cross-sectional view 2400 of fig. 24, a second interconnect dielectric layer 134b is formed over the source and CG stripe cells 102, 502 and the first interconnect dielectric layer 134 a. The second interconnect dielectric layer 134b may be or include, for example, silicon oxide and/or some other suitable dielectric.
Also shown by the cross-sectional view 2400 of fig. 24, a lead 210a and a contact via 124a are formed in the first interconnect dielectric layer 134a and the second interconnect dielectric layer 134 b. Contact via 124a extends from lead 210a through first and second interconnect dielectric layers 134a and 134b and CESL208 to source silicide layer 122 a. The CESL208 may, for example, serve as an etch stop layer when forming the contact via 124 a.
Although fig. 10-13 and 16-24 are described with reference to various embodiments of a method, it will be understood that the structures shown in fig. 10-13 and 16-24 are not limited to this method, but may be independent of this method alone. While fig. 10-13 and 16-24 are described as a series of acts, it will be appreciated that the order of the acts may be varied in other embodiments. Although fig. 10-13 and 16-24 are shown and described as a particular set of acts, some acts shown and/or described may be omitted in other embodiments. Moreover, acts not shown and/or described may be included in other embodiments.
Referring to fig. 25, a block diagram 2500 of some embodiments of the methods of fig. 10-13 and 16-24 is provided.
At 2502, source bar cells are partially formed, wherein the source bar cells are defined by a source line and an EG line located above the source line. See, for example, fig. 10.
At 2504, a pair of CG strip cells is partially formed, wherein the CG strip cells are defined by CG lines and SG lines, respectively, and wherein the SG lines are located between and adjacent to the CG lines, respectively. See, for example, fig. 10.
At 2506, a first etch is performed on the EG and SG lines with the first mask in place, wherein the first etch forms a first opening through the EG line at the source bar cell and a second opening through the SG line at the CG bar cell, and wherein the first etch stops on the source dielectric layer below the EG line. See, for example, fig. 12.
At 2508, with the first mask in place, a second etch is performed on the source dielectric layer to thin the source dielectric layer at the first opening. See, for example, fig. 13.
At 2510, primary side wall spacers are formed on the sidewalls of the source and CG bar cells. See, for example, fig. 17.
At 2512, an RPD layer is deposited, covering the source bar cells and CG bar cells. See, for example, fig. 18.
At 2514, a third etch is performed on the RPD layer with the second mask in place to pattern the RPD layer with a silicide pattern and extend the first opening through the source dielectric layer to the source line. See, for example, fig. 19. Thus, the source line is opened by a two-step process consisting of the second and third etches. The two-step process is in contrast to a single-step process for opening the source line, which uses a single lithography/etch process with a different mask than the first and second masks.
At 2516, a silicide layer is formed in the first opening and on the source line according to a silicide pattern.
At 2518, leads and contact vias are formed on the silicide layer. See, for example, fig. 24.
Since the method uses a two-step process instead of a single-step process to open the source lines, the method can use one less photomask than originally. This can reduce costs. In addition, since one less photomask can be used, the risk of photoresist errors on the source lines can be reduced. This may enlarge the process window for forming the silicide layer and/or the contact via on the source line.
While the block diagram 2500 of fig. 25 is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Moreover, not all illustrated acts may be required to implement one or more aspects or embodiments described herein, and one or more acts described herein may be performed in one or more separate acts and/or phases.
Referring to fig. 26-32, a series of cross-sectional views 2600-. Furthermore, the hard mask is completely removed prior to depositing the RPD layer.
As shown in the cross-sectional view 2600 of fig. 26, the source bar cells 102 and the CG bar cells 502 are partially formed on the trench isolation structures 112 and the active area 104a of the substrate 104. The trench isolation structure 112 and the active region 104a are as described with respect to fig. 10, except that the trench isolation structure 112 and the active region 104a have a different layout than fig. 10.
The acts shown and described with respect to fig. 11 and 12 are performed as illustrated by cross-sectional view 2700 of fig. 27. A first mask 1102 is formed to partially cover the source bar cells 102 and the CG bar cells 502, and a sacrificial layer (not shown; see, e.g., 1104 in fig. 11) is formed to fill gaps between the CG bar cells 502 (see, e.g., fig. 26). Further, with the first mask 1102 in place, a first etch is performed on the source and CG bar cells 102, 502 to form a first opening 1202 and a second opening 1204.
As shown in cross-sectional view 2800 of fig. 28, a second etch is performed on the source dielectric layer 114 of the source bar cells 102 and the exposed portions of the substrate 104 between the CG bar cells 502. The second etch is as described with respect to fig. 13.
As shown in cross-sectional view 2900 of fig. 29, the acts shown and described with respect to fig. 17 and 21 are performed. The CG hard mask 1002, SG hard mask 1004, and EG hard mask 1006 are removed. In addition, primary side wall spacers 120 are formed on the outer side walls of the source and CG bar cells 102, 502 and line the sidewalls of the source and CG bar cells 102, 502 in the first and second openings 1202, 1204.
As shown in the cross-sectional view 3000 of fig. 30, an RPD layer 1802 is formed to cover the source and CG stripe cells 102, 502 and further to line the sidewalls of the main sidewall spacers 120. The RPD layer 1802 is formed as described with respect to fig. 18.
As shown in cross-sectional view 3100 of fig. 31, the acts shown and described with respect to fig. 19 are performed. A second mask 1902 is formed on the RDP layer 1802. Further, a third etch is performed on the RPD layer 1802 and extends into the source dielectric layer 114 of the source bar cell 102 to expose the source line 106 of the source bar cell 102 at the first opening 1202.
As shown in cross-sectional view 3200 of fig. 32, the acts shown and described with respect to fig. 20 and 22-24 are performed. The second mask 1902 is removed, and a source silicide layer 122a is formed on the source lines 106 of the source bar cells 102. CESL208 and the first interconnect dielectric layer 134a are deposited to cover the source and CG bar cells 102, 502 and to further fill the first and second openings 1202, 1204 (see, e.g., fig. 13). Planarization is performed on the CESL208 and the first interconnect dielectric layer 134a, and a CG/EG silicide layer 122b is formed on the CG line 110 and the EG line 108. A second interconnect dielectric layer 134b is formed over the source and CG bar cells 102, 502 and the first interconnect dielectric layer 134 a. The lead 210a and the contact via 124a are formed.
While fig. 26-32 are described with reference to various embodiments of a method, it should be understood that the structures shown in fig. 26-32 are not limited to this method, but may be independent of this method alone. While fig. 26-32 are depicted as a series of acts, it will be appreciated that the order of the acts may be varied in other embodiments. While fig. 26-32 are shown and described as a particular set of acts, some acts shown and/or described may be omitted in other embodiments. Moreover, acts not shown and/or described may be included in other embodiments.
In some embodiments, the present invention provides a memory device comprising: a substrate; an erase gate line, a control gate line and a source line elongated in parallel in a first direction, wherein the erase gate line has a break dividing the erase gate line into a pair of erase gate segments in the first direction, wherein the control gate line is adjacent to the erase gate line, and wherein the source line is located under the erase gate line in the substrate; a source dielectric layer between the erase gate line and the source line; main sidewall spacers over the source line and the source dielectric layer in the center between the erase gate segments; and a contact via extending through the erase gate line and the source dielectric layer at the break and electrically coupled with the source line. In some embodiments, the contact vias are spaced apart from the main sidewall spacers and the source dielectric layer. In some embodiments, the main sidewall spacers have a bottom surface that is at least partially raised above the topmost point of the substrate. In some embodiments, the main sidewall spacers and the source dielectric layer define a common sidewall facing the contact via. In some embodiments, the memory device further includes an Etch Stop Layer (ESL) having a U-shaped profile centered between the erase gate segments, wherein the U-shaped profile laterally contacts the main sidewall spacers. In some embodiments, the memory device further comprises: a floating gate located under the control gate line; and a control gate sidewall spacer overlying the floating gate and separating the control gate line from the main sidewall spacer. In some embodiments, the memory device further includes a silicide layer located between and directly contacting the contact via and the source line. In some embodiments, the silicide layer has a width of about 800-1100 angstroms.
In some embodiments, the present invention provides an Integrated Circuit (IC) comprising: a substrate; a memory array including a plurality of cells, wherein the plurality of cells includes a source bar cell and a pair of control gate bar cells; an erase gate line and a source line partially defining the source bar unit and elongated in parallel in a first direction, wherein the source line is positioned under the erase gate line, and wherein the erase gate line has a first break in the first direction; a first control gate line, a second control gate line, and a pair of select gate lines partially defining a control gate bar unit and elongated in parallel in a first direction, wherein the select gate lines are located between and adjacent to the first control gate line and the second control gate line, respectively, and have second breaks in the first direction, and wherein the first control gate line has a pad protruding toward the second control gate line at the second breaks; and a trench isolation structure located under the first and second control gate lines; wherein the top surface of the substrate has a recess with a U-shaped top layout surrounding the pads at the second break. In some embodiments, the recess extends into the top surface of the substrate to a depth of about 100 and 300 angstroms. In some embodiments, the contact vias extend to the source line, the first control gate line, and the second control gate line at the source bar unit and the control gate bar unit, respectively. In some embodiments, the first discontinuity divides the erase gate line into a pair of erase gate segments along the first direction, wherein the IC further comprises: a source dielectric layer between the erase gate line and the source line; and main sidewall spacers vertically separated from the substrate by a source dielectric layer located adjacent the first break and at a location spaced apart from and between the erase gate segments. In some embodiments, the location is equidistant from the erase gate segment.
In some embodiments, the invention provides a method for forming a memory device, the method comprising: forming an erase gate line and a source line elongated in parallel, wherein the source line is located below the erase gate line in the substrate and separated from the erase gate line by a source dielectric layer; performing a first etch on the erase gate line to form a first opening extending through the erase gate line, wherein the first etch is performed with the first mask in place and stops on the source dielectric layer; performing a second etch of the source dielectric layer through the first opening with the first mask in place to thin the source dielectric layer at the first opening; performing a silicide process to form a silicide layer on the source line at the first opening, wherein the silicide process includes a third etch that extends the first opening through the source dielectric layer and exposes the source line; and forming a contact via extending through the erase gate line to the silicide layer. In some embodiments, the silicide process includes an RPO etch, wherein the RPO etch removes the source dielectric layer at the first opening. In some embodiments, the portion of the source dielectric layer at the first opening has an oval profile before the second etch, wherein a top surface of the portion has a W-shaped profile after the second etch. In some embodiments, the method further includes forming a pair of control gate lines and a pair of select gate lines overlying the substrate and elongated parallel to the erase gate lines, wherein the select gate lines are between and respectively adjacent to the control gate lines, wherein one of the control gate lines has a pad protruding toward the other control gate line, and wherein the first etch forms a second opening at the pad extending through the select gate line. In some embodiments, the control gate line is formed partially over the trench isolation structure and extends to the top surface of the substrate, wherein the second etch forms a recess in the top surface of the substrate through the second opening, and wherein the recess surrounds the pad. In some embodiments, the method further comprises: forming a pair of control gate lines overlying the substrate and elongated in parallel with erase gate lines, wherein the erase gate lines are between and adjacent to the control gate lines; and forming main side wall spacers between the control gate lines on sidewalls of the first opening, wherein the main side wall spacers are located over the source dielectric layer at centers between the discrete segments of the erase gate lines separated by the first opening. In some embodiments, the silicide process comprises: depositing an RPD layer covering the erase gate line and lining the first opening; performing a third etch of the RPD layer and the source dielectric layer with the second mask in place to extend the first opening through the RPD layer and the source dielectric layer; forming a silicide layer on the source line and with the RPD layer in place; and removing the RPD layer.
The present disclosure outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A memory device, comprising:
a substrate;
an erase gate line, a control gate line, and a source line elongated in parallel in a first direction, wherein the erase gate line has a break dividing the erase gate line into a pair of erase gate segments in the first direction, wherein the control gate line is adjacent to the erase gate line, and wherein the source line is located under the erase gate line in the substrate;
a source dielectric layer between the erase gate line and the source line;
main sidewall spacers over the source dielectric layer and the source lines at centers between the erase gate segments; and
a contact via extending through the erase gate line and the source dielectric layer at the break and electrically coupled with the source line.
2. The memory device of claim 1, wherein the contact via is spaced apart from the main sidewall spacers and the source dielectric layer.
3. The memory device of claim 1, wherein the main side wall spacers have a bottom surface that is at least partially raised above an uppermost point of the substrate.
4. The memory device of claim 1, wherein the main sidewall spacers and the source dielectric layer define a common sidewall facing the contact via.
5. The memory device of claim 1, further comprising:
an Etch Stop Layer (ESL) having a U-shaped profile in the center between the erase gate segments, wherein the U-shaped profile laterally contacts the main sidewall spacers.
6. The memory device of claim 1, further comprising:
a floating gate located under the line; and
control gate sidewall spacers overlying the floating gate and separating the control gate line from the main sidewall spacers.
7. The memory device of claim 1, further comprising:
a silicide layer between and directly contacting the contact via and the source line.
8. The memory device of claim 7, wherein the silicide layer has a width of 800-1100 angstroms.
9. An Integrated Circuit (IC), comprising:
a substrate;
a memory array including a plurality of cells, wherein the plurality of cells includes a source bar cell and a pair of control gate bar cells;
an erase gate line and a source line partially defining the source bar cells and elongated in parallel in a first direction, wherein the source line is located below the erase gate line, and wherein the erase gate line has a first break in the first direction;
a first control gate line, a second control gate line, and a pair of select gate lines partially defining the control gate bar unit and elongated in parallel in the first direction, wherein the select gate lines are located between and respectively adjacent to the first control gate line and the second control gate line and have a second break in the first direction, and wherein the first control gate line has a pad protruding toward the second control gate line at the second break; and
a trench isolation structure located under the first and second control gate lines;
wherein the top surface of the substrate has a recess with a U-shaped top layout surrounding the pads at the second break.
10. A method for forming a memory device, the method comprising:
forming an erase gate line and a source line elongated in parallel, wherein the source line is located below the erase gate line in a substrate and separated from the erase gate line by a source dielectric layer;
performing a first etch on the erase gate line to form a first opening extending through the erase gate line, wherein the first etch is performed with a first mask in place and stops on the source dielectric layer;
performing a second etch of the source dielectric layer through the first opening with the first mask in place to thin the source dielectric layer at the first opening;
performing a silicide process to form a silicide layer on the source line at the first opening, wherein the silicide process includes a third etch that extends the first opening through the source dielectric layer and exposes the source line; and
forming a contact via extending through the erase gate line to the silicide layer.
CN202010787448.8A 2019-08-30 2020-08-07 Integrated circuit, memory device and forming method thereof Pending CN112447737A (en)

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US16/800,167 US11239245B2 (en) 2019-08-30 2020-02-25 Etch method for opening a source line in flash memory

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