KR20010059977A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR20010059977A KR20010059977A KR1019990067973A KR19990067973A KR20010059977A KR 20010059977 A KR20010059977 A KR 20010059977A KR 1019990067973 A KR1019990067973 A KR 1019990067973A KR 19990067973 A KR19990067973 A KR 19990067973A KR 20010059977 A KR20010059977 A KR 20010059977A
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- insulating film
- gate electrode
- forming
- contact plug
- insulating layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 28
- 125000006850 spacer group Chemical group 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 230000002093 peripheral effect Effects 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 238000007517 polishing process Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 description 30
- 239000010410 layer Substances 0.000 description 23
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 고집적 반도체소자의 게이트전극과 콘택플러그를 동시에 형성하는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a gate electrode and a contact plug of a highly integrated semiconductor device are simultaneously formed.
최근의 반도체장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 반도체장치의 제조공정 중에서 식각 또는 이온주입 공정 등의마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다.The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.
상기 감광막 패턴의 분해능(R) 은 축소노광장치의 광원의 파장(λ) 및 공정 변수(k)에 비례하고, 노광 장치의 렌즈 구경(numerical aperture : NA, 개구수)에 반비례한다.The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the numerical aperture NA of the exposure apparatus.
[ R = k*λ/NA, R = 해상도, λ = 광원의 파장, NA = 개구수][R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = numerical aperture]
여기서, 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를 들어 파장이 436 및 365nm인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 각각 약 0.5, 0.3㎛ 정도가 한계이고, 0.3㎛이하의 미세 패턴을 형성하기 위해 파장이 작은 원자외선(deep ultra violet : DUV), 예를 들어 파장이 248㎚인 KrF 레이저나 193㎚인 ArF 레이저를 광원으로 사용하는 노광장치를 이용하거나, 공정상의 방법으로는 노광마스크(photo mask)를 위상 반전 마스크(phase shift mask)를 사용하는 방법과, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘.(contrast enhancement layer, 이하 CEL이라 함)방법이나 두 층의 감광막 사이에 SOG 등의 중간층을 개재시킨 삼층레지스트(tri layer resist, TLR) 방법 또는 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션 방법 등이 개발되어 분해능 한계치를 낮추고 있다.Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.5 and 0.3 µm, respectively. Exposure is limited using a deep ultra violet (DUV) light, for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm as a light source to form a fine pattern of 0.3 μm or less. As an apparatus or process method, a photo mask is used as a phase shift mask, and a separate thin film is formed on the wafer to improve image contrast. L. (contrast enhancement layer, CEL) method, tri-layer resist (TLR) method in which an intermediate layer such as SOG is interposed between two layers of photoresist, or selectively on top of the photoresist. Silicate methods for injecting cones have been developed to lower the resolution limit.
또한, 상하의 도전배선을 연결하는 콘택홀은 소자가 고집적화되어감에 따라 자체의 크기와 주변배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스펙트비(aspect ratio)가 증가하기 때문에 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택을 형성하기 위하여 제조 공정에서의 마스크들간의 정확하고 엄격한 정렬이 요구되어 공정여유도가 감소되는 문제점이 있다.In addition, the contact holes connecting the upper and lower conductive wirings have a multi-layered structure due to the high integration of devices, and the gap between the size of the contact holes and the peripheral wirings is reduced and the aspect ratio, which is the ratio of the diameter and depth of the contact holes, is increased. In the highly integrated semiconductor device having the conductive wiring of, a precise and strict alignment between the masks in the manufacturing process is required to form a contact, thereby reducing the process margin.
상기와 같이 소자의 고집적화에 따른 문제점을 해결하기 위하여 도전배선을 서로 연결시키고, 공정여유도를 증가시키기 위하여 비트라인과 저장전극 콘택을 형성하는 경우 콘택플러그를 사용하게 된다. 상기 콘택플러그는 게이트전극을 형성한 다음 비트라인 콘택과 저장전극 콘택으로 예정되는 부분을 노출시키는 콘택홀이 구비된 층간절연막을 형성한 후, 전면에 다결정실리콘층을 형성한 다음, 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함)공정으로 제거하여 비트라인 콘택과 저장전극 콘택으로 예정되는 부분과 접속되는 콘택플러그를 형성한다.In order to solve the problems caused by the high integration of the device as described above, the contact plugs are used when the conductive lines are connected to each other and the bit line and the storage electrode contacts are formed to increase the process margin. The contact plug forms a gate electrode and then forms an interlayer insulating film having a contact hole exposing a portion intended as a bit line contact and a storage electrode contact, and then forms a polysilicon layer on the front surface, followed by chemical mechanical polishing ( chemical mechanical polishing (hereinafter referred to as " CMP ") process to form a contact plug that is connected to a portion intended as a bit line contact and a storage electrode contact.
그러나, 상기와 같이 종래기술에 따른 반도체소자의 제조방법은, 소오스/드레인접합영역에 접속되는 비트라인 또는 저장전극의 콘택플러그를 형성하는 경우 게이트전극 측벽의 절연막 스페이서에 의해 콘택이 형성될 공간을 충분히 확보하는 것이 어렵고, 자기정렬콘택(self aligned contact, SAC)공정에 의한 콘택식각으로 접합영역이 손상되어 소자의 전기적 특성 및 공정수율을 저하시키는 문제점이 있다.However, in the semiconductor device manufacturing method according to the related art as described above, when forming a contact plug of a bit line or a storage electrode connected to a source / drain junction region, a space for forming a contact is formed by an insulating layer spacer on the sidewall of the gate electrode. It is difficult to secure enough, and there is a problem in that the junction region is damaged by contact etching by a self aligned contact (SAC) process, thereby lowering the electrical characteristics and process yield of the device.
본 발명은 상기한 종래기술의 문제점들을 해결하기 위하여, 게이트전극 형상의 희생절연막 패턴을 형성하고, 희생절연막 패턴의 측벽에 절연막 스페이서를 형성한 다음, 상기 희생절연막 패턴을 제거하여 절연막 스페이서만 남기고, 전체표면 상부에 도전층을 형성한 다음 CMP공정을 실시하여 게이트전극 및 콘택플러그를 동시에 형성한 후 마스크공정을 실시하여 필요없는 부분에 형성된 콘택플러그를 제거함으로써 미스얼라인 또는 과도식각으로 발생하는 반도체기판의 손상을 최소화하고, 소자간에 단락되는 현상을 방지하는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.According to the present invention, in order to solve the problems of the prior art, a sacrificial insulating film pattern having a gate electrode shape is formed, an insulating film spacer is formed on sidewalls of the sacrificial insulating film pattern, and the sacrificial insulating film pattern is removed to leave only the insulating film spacer, A semiconductor is formed by misalignment or transient etching by forming a conductive layer on the entire surface and then performing a CMP process to simultaneously form a gate electrode and a contact plug, and then performing a mask process to remove contact plugs formed on unnecessary portions. It is an object of the present invention to provide a method for manufacturing a semiconductor device which minimizes damage to a substrate and prevents a short circuit between the devices.
도 1 내지 도 7 은 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도.1 to 7 are cross-sectional views showing a method of manufacturing a semiconductor device according to the present invention.
<도면의 주요부분에 대한 부호 설명><Description of Signs of Major Parts of Drawings>
11 : 반도체기판 13 : 소자분리절연막11: semiconductor substrate 13: device isolation insulating film
15 : 게이트절연막 패턴 17 : 희생절연막 패턴15: gate insulating film pattern 17: sacrificial insulating film pattern
19 : LDD영역 21 : 절연막 스페이서19: LDD region 21: insulating film spacer
23 : 고농도불순물영역 25 : 홈23: high concentration impurity area 25: home
27 : 다결정실리콘층 28 : 콘택플러그27 polysilicon layer 28 contact plug
29 : 게이트전극 31 : 감광막 패턴29 gate electrode 31 photosensitive film pattern
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 제조방법은,In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,
셀영역과 주변회로영역이 구비되는 반도체기판에 소자분리절연막을 형성하고, 상기 반도체기판 상부에 게이트전극 형상을 갖는 게이트절연막 패턴과 희생절연막패턴의 적층구조를 형성하는 공정과,Forming a device isolation insulating film on a semiconductor substrate having a cell region and a peripheral circuit region, and forming a stacked structure of a gate insulating pattern and a sacrificial insulating pattern having a gate electrode shape on the semiconductor substrate;
상기 적층구조 양측 반도체기판에 저농도불순물을 이온주입하여 LDD영역을 형성하는 공정과,Forming an LDD region by ion implanting low-concentration impurities into the semiconductor substrates on both sides of the stacked structure;
상기 적층구조의 양측에 절연막 스페이서를 형성하는 공정과,Forming insulating film spacers on both sides of the laminated structure;
상기 주변회로영역의 절연막 스페이서 양측에 고농도불순물영역을 형성하는 공정과,Forming a high concentration impurity region on both sides of the insulating film spacer of the peripheral circuit region;
상기 희생절연막 패턴을 제거하여 상기 절연막 스페이서로 둘러싸인 홈을 형성하는 공정과,Removing the sacrificial insulating film pattern to form a groove surrounded by the insulating film spacer;
전체표면 상부에 도전층을 형성하는 공정과,Forming a conductive layer over the entire surface,
상기 도전층 및 절연막 스페이서를 화학적 기계적 연마공정으로 제거하여 게이트전극과 콘택플러그를 형성하되, 상기 게이트전극과 콘택플러그는 상기 절연막 스페이서에 의해 절연되도록 형성하는 공정과,Forming a gate electrode and a contact plug by removing the conductive layer and the insulating film spacer by a chemical mechanical polishing process, wherein the gate electrode and the contact plug are insulated by the insulating film spacer;
전체표면 상부에 상기 셀영역 상에서 소자분리절연막 상에 형성된 콘택플러그와 주변회로영역에서 게이트전극을 제외한 부분에 형성된 콘택플러그를 제거하는 공정을 포함하는 것을 특징으로 한다.And removing contact plugs formed on the device isolation insulating layer on the cell region over the entire surface and contact plugs formed on portions other than the gate electrode in the peripheral circuit region.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 7 은 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도이다.1 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
먼저, 셀영역(Ⅰ)과 주변회로영역(Ⅱ)이 구비되는 반도체기판(11)에서 소자분리영역으로 예정되는 부분에 소자분리절연막(13)을 형성한다.First, an element isolation insulating film 13 is formed on a portion of the semiconductor substrate 11 including the cell region I and the peripheral circuit region II, which is intended to be an element isolation region.
다음, 전체표면 상부에 게이트절연막(도시안됨)과 희생절연막(도시안됨)을 형성하고, 게이트전극마스크를 식각마스크로 상기 희생절연막과 게이트절연막을 식각하여 게이트전극 형상의 희생절연막 패턴(17)과 게이트절연막 패턴(15)의 적층구조를 형성한다. 이때, 상기 희생절연막은 후속공정에서 습식식각공정으로 제거되기 쉬운 PSG막으로 형성한다. (도 1 참조)Next, a gate insulating layer (not shown) and a sacrificial insulating layer (not shown) are formed on the entire surface, and the sacrificial insulating layer and the gate insulating layer are etched using a gate electrode mask as an etch mask, and the sacrificial insulating pattern 17 having a gate electrode shape is formed. A stack structure of the gate insulating film pattern 15 is formed. In this case, the sacrificial insulating film is formed of a PSG film which is easily removed by a wet etching process in a subsequent process. (See Figure 1)
그 다음, 상기 적층구조의 양측 반도체기판(11)에 저농도의 불순물을 이온주입하여 LDD영역(19)을 형성한다.Next, the LDD region 19 is formed by ion implanting impurities of low concentration into both semiconductor substrates 11 of the stacked structure.
다음, 상기 적층구조의 측벽에 절연막 스페이서(21)를 형성한다. 이때, 상기 절연막 스페이서(21)은 상기 희생절연막 패턴(17)과 식각선택비차이를 갖는 질화막으로 형성한다. (도 2 참조)Next, an insulating film spacer 21 is formed on the sidewall of the stacked structure. In this case, the insulating layer spacer 21 is formed of a nitride layer having an etching selectivity difference from the sacrificial insulating layer pattern 17. (See Figure 2)
그 다음, 상기 주변회로영역(Ⅱ) 상에 형성되는 적층구조의 양측반도체기판(11)에 고농도의 불순물을 이온주입하여 고농도 불순물영역(23)을 형성한다. (도 3 참조)Next, a high concentration impurity region 23 is formed by ion implantation of high concentration of impurities into both semiconductor substrates 11 of the stacked structure formed on the peripheral circuit region II. (See Figure 3)
다음, 상기 희생절연막 패턴(17)을 제거하여 상기 절연막 스페이서(21)로 둘러싸인 홈(25)을 형성한다. 상기 홈(25)은 게이트전극이 형성될 영역으로 그 저부에는 게이트절연막 패턴(15)이 형성되어 있다. (도 4 참조)Next, the sacrificial insulating film pattern 17 is removed to form the groove 25 surrounded by the insulating film spacer 21. The groove 25 is a region where a gate electrode is to be formed, and a gate insulating film pattern 15 is formed at a bottom thereof. (See Figure 4)
그 다음, 전체표면 상부에 다결정실리콘층(27)을 형성하되, 상기 홈(25)이 완전히 매립되도록 형성한다. (도 5 참조)Next, a polysilicon layer 27 is formed on the entire surface, and the groove 25 is formed to be completely buried. (See Figure 5)
다음, 상기 다결정실리콘층(27)과 절연막 스페이서(21)를 CMP공정으로 제거하여 게이트전극(29)과 콘택플러그(28)를 형성하되, 상기 게이트전극(29)과 콘택플러그(28)는 상기 절연막 스페이서(21)에 의해 절연되도록 형성한다. (도 6 참조)Next, the polysilicon layer 27 and the insulating layer spacer 21 are removed by a CMP process to form a gate electrode 29 and a contact plug 28, wherein the gate electrode 29 and the contact plug 28 are formed as described above. It is formed so as to be insulated by the insulating film spacer 21. (See Figure 6)
그 다음, 전체표면 상부에 상기 셀영역(Ⅰ)에서 소자분리절연막(13) 상에 형성된 콘택플러그와 주변회로영역(Ⅱ)에서 게이트전극 이외의 부분을 노출시키는 감광막 패턴(31)을 형성한다. (도 7 참조)Next, a contact plug formed on the device isolation insulating film 13 in the cell region I and a photoresist pattern 31 exposing portions other than the gate electrode in the peripheral circuit region II are formed on the entire surface. (See Figure 7)
그 후, 도시되어 있지는 않지만 상기 감광막 패턴(31)에 노출되는 콘택플러그, 즉 필요하지 않은 콘택플러그들을 제거하여 게이트전극(29)과 비트라인 및 저장전극과 접속될 콘택플러그(28)들만 남긴다.Thereafter, although not shown, contact plugs exposed to the photoresist pattern 31, that is, unnecessary contact plugs, are removed, leaving only the contact plugs 28 to be connected to the gate electrode 29, the bit line, and the storage electrode.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 고집적 반도체소자의 제조공정에서 게이트전극과 콘택플러그가 형성될 부분을 미리 형성하되, 그 사이에 절연막 스페이서를 형성하여 서로 분리시켜 놓은 다음, 다결정실리콘층을 형성하고 CMP공정으로 상기 다결정실리콘층을 식각하여 게이트전극과 콘택플러그를 형성하되, 상기 절연막 스페이서에 의해 서로 절연되도록 형성한 후마스크공정으로 필요없는 부분에 형성된 콘택플러그를 제거함으로써 단순한 공정으로 접합영역에 손상을 주지않고 게이트전극 및 콘택플러그를 형성하여 소자의 전기적 특성 및 공정수율을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, in the manufacturing process of a highly integrated semiconductor device, a portion in which a gate electrode and a contact plug are to be formed is formed in advance, and insulating film spacers are formed therebetween to separate them from each other. Forming a polysilicon layer and etching the polysilicon layer by a CMP process to form a gate electrode and a contact plug, and formed to be insulated from each other by the insulating film spacer, and then removing the contact plug formed in the unnecessary portion by a mask process By forming a gate electrode and a contact plug without damaging the junction region by a simple process, there is an advantage to improve the electrical characteristics and the process yield of the device, and thereby high integration of the semiconductor device.
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| KR19980077340A (en) * | 1997-04-18 | 1998-11-16 | 김영환 | Method for forming storage electrode of semiconductor device |
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