KR20010058955A - A method for forming a metal line of a semiconductor device - Google Patents
A method for forming a metal line of a semiconductor device Download PDFInfo
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- KR20010058955A KR20010058955A KR1019990066331A KR19990066331A KR20010058955A KR 20010058955 A KR20010058955 A KR 20010058955A KR 1019990066331 A KR1019990066331 A KR 1019990066331A KR 19990066331 A KR19990066331 A KR 19990066331A KR 20010058955 A KR20010058955 A KR 20010058955A
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- film
- forming
- metal wiring
- nitride film
- interlayer insulating
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 70
- 239000002184 metal Substances 0.000 title claims abstract description 70
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title abstract description 25
- 150000004767 nitrides Chemical class 0.000 claims abstract description 39
- 239000011229 interlayer Substances 0.000 claims abstract description 22
- 239000010936 titanium Substances 0.000 claims abstract description 17
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 125000006850 spacer group Chemical group 0.000 claims abstract description 8
- 230000001681 protective effect Effects 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 9
- 125000004435 hydrogen atom Chemical group [H]* 0.000 claims description 9
- 230000007547 defect Effects 0.000 abstract description 12
- YZCKVEUIGOORGS-IGMARMGPSA-N Protium Chemical compound [1H] YZCKVEUIGOORGS-IGMARMGPSA-N 0.000 abstract 2
- 239000010408 film Substances 0.000 description 55
- 239000010410 layer Substances 0.000 description 26
- 239000000463 material Substances 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 7
- 238000002161 passivation Methods 0.000 description 5
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- -1 hydrogen ions Chemical class 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 특히 수소이온을 이용하여 반도체소자의 제조공정시 유발되는 격자 결함을 보상해 주는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a technique for compensating for lattice defects caused in the manufacturing process of semiconductor devices using hydrogen ions.
일반적으로 반도체 메모리 소자는 하나의 트랜지스터와 하나의 캐패시터를 하나의 단위로 하여 구성되며, 이들을 다수개 연결하여 소자의 기능 및 용량을 증가시킨다.In general, a semiconductor memory device includes one transistor and one capacitor as one unit, and a plurality of the semiconductor memory devices are connected to each other to increase the function and capacity of the device.
그리고, 상기 메모리 소자를 구동시키기 위하여 금속배선을 형성한다.Then, metal wirings are formed to drive the memory device.
그 다음, 상기 메모리 소자의 결함을 보상하기 위하여 상기 결함을 수소와 반응시킴으로써 누설전류를 감소시킨다.The leakage current is then reduced by reacting the defect with hydrogen to compensate for the defect of the memory element.
도 1 은 종래기술에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.1 is a cross-sectional view showing a metal wiring formation method of a semiconductor device according to the prior art.
먼저, 반도체기판(11)에 소자분리막, 워드라인, 비트라인 및 캐패시터가 구비되는 하부절연층(13)을 형성한다.First, a lower insulating layer 13 having a device isolation film, a word line, a bit line, and a capacitor is formed on the semiconductor substrate 11.
그리고, 상기 반도체기판(11)을 노출시키는 금속배선 콘택홀(15)을 형성한다.A metal wiring contact hole 15 exposing the semiconductor substrate 11 is formed.
이때, 상기 금속배선 콘택홀(15)은 금속배선 콘택마스크(도시안됨)를 이용한 사진식각공정으로 상기 하부절연층(13)을 식각하여 형성한다.In this case, the metal wiring contact hole 15 is formed by etching the lower insulating layer 13 by a photolithography process using a metal wiring contact mask (not shown).
그 다음, 상기 콘택홀(15)을 통하여 상기 반도체기판(11)에 접속되는 제1금속배선(17)을 형성한다.Next, a first metal wiring 17 connected to the semiconductor substrate 11 through the contact hole 15 is formed.
이때, 상기 제1금속배선(17)은 상기 금속배선 콘택홀(15)을 매립하는 제1금속배선 물질층을 전체표면상부에 형성하고 이를 제1금속배선 마스크를 이용한 사진식각공정으로 패터닝하여 형성한다.In this case, the first metal wiring 17 is formed by forming a first metal wiring material layer filling the metal wiring contact hole 15 on the entire surface and patterning it by a photolithography process using a first metal wiring mask. do.
그 다음, 상기 제1금속배선(17) 포함한 전체표면상부에 층간절연막(19)을 형성하고 이를 평탄화시킨다.Next, an interlayer insulating film 19 is formed on the entire surface including the first metal wiring 17 and flattened.
그리고, 상기 제1금속배선(17)을 노출시키는 비아콘택홀(21)을 형성한다.A via contact hole 21 exposing the first metal wiring 17 is formed.
이때, 상기 비아콘택홀(21)은 비아콘택마스크(도시안됨)를 이용한 사진식각공정으로 상기 층간절연막(19)을 식각하여 형성한다.In this case, the via contact hole 21 is formed by etching the interlayer insulating layer 19 by a photolithography process using a via contact mask (not shown).
그 다음, 전체표면상부에 티타늄막 ( Ti layer )(23)을 형성한다.Then, a Ti layer 23 is formed on the entire surface.
그리고, 상기 비아콘택홀(21)을 매립하며 상기 제1금속배선(17)에 접속되는 제2금속배선(25)을 형성한다.Then, the via contact hole 21 is buried to form a second metal wiring 25 connected to the first metal wiring 17.
이때, 상기 제2금속배선(25)는 상기 제1금속배선(17)에 접속되는 제2금속배선 물질층을 전체표면상부에 형성하고 이를 제2금속배선 마스크를 이용한 사진식각공정으로 패터닝하여 형성한다.In this case, the second metal wiring 25 is formed by forming a second metal wiring material layer connected to the first metal wiring 17 on the entire surface and patterning it by a photolithography process using a second metal wiring mask. do.
그 다음, 전체표면상부에 보호막(27)을 형성한다.Next, a protective film 27 is formed over the entire surface.
이때, 상기 보호막(27)은 다량의 수소기를 배출하는 제1보호막과 그 상부에 형성되어 상기 수소기의 유출을 방지하는 실리콘질화막의 적층구조로 형성된다.In this case, the passivation layer 27 is formed in a stacked structure of a first passivation layer for discharging a large amount of hydrogen groups and a silicon nitride film formed thereon to prevent the outflow of the hydrogen groups.
여기서, 상기 제1보호막은 반도체소자의 제조공정중, 특히 식각공정 및 이온주입공정시 유발되는 격자결함과 수소기를 반응시켜 결함을 보상할 수 있도록 하기 위하여 형성한 박막으로서, 격자결함을 감소시켜 접합누설전류를 감소시키고 그에따른 반도체소자의 리프레쉬 특성을 향상시키는 역할을 한다.Here, the first protective film is a thin film formed so as to compensate for defects by reacting a lattice defect caused by a hydrogen group with a lattice defect caused during an etching process and an ion implantation process of the semiconductor device. It serves to reduce the leakage current and thereby improve the refresh characteristics of the semiconductor device.
후속 열처리공정으로 상기 제1보호막에서 유발되는 수소기를 확산시켜 격자 결함을 보상한다. (도 1)A subsequent heat treatment process diffuses the hydrogen groups induced in the first protective film to compensate for the lattice defects. (Figure 1)
상기한 종래기술은, 제2금속배선(17) 하부에 형성되는 티타늄막(23)과 상기 수소기가 반응하여 격자 결함을 발생시킴으로써 반도체기판에 상존하는 격자결함으로 인하여 반도체소자의 리프레쉬 특성이 저하되는 문제점이 있다.According to the related art, a refreshing characteristic of a semiconductor device is deteriorated due to lattice defects remaining on a semiconductor substrate by generating a lattice defect by reacting the titanium film 23 formed under the second metal wiring 17 with the hydrogen group. There is a problem.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 제2금속배선의 하부에 티타늄막을 형성하기 전에 층간절연막 표면에 질화막을 형성하고 그 상부에 티타늄막을 형성함으로써 후속공정으로 유발되는 수소기와 티타늄막의 반응으로 인한 격자결함의 유발을 방지하여 누설전류를 증가를 방지하고 그에 따른 리프레쉬 특성을 향상시킬 수 있는 반도체소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the above problems of the prior art, by forming a nitride film on the surface of the interlayer insulating film before forming the titanium film on the lower portion of the second metal wiring and the titanium film on the upper portion of the hydrogen and titanium film caused by a subsequent process It is an object of the present invention to provide a method for forming metal wirings in a semiconductor device which can prevent the occurrence of lattice defects due to a reaction, thereby preventing an increase in leakage current and thereby improving refresh characteristics.
도 1 은 종래기술의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.1 is a cross-sectional view showing a metal wiring forming method of a semiconductor device according to an embodiment of the prior art.
도 2a 내지 도 2e 는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.2A to 2E are cross-sectional views illustrating a method for forming metal wirings in a semiconductor device according to an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11,31 : 반도체기판 13,33 : 하부절연층11,31: semiconductor substrate 13,33: lower insulating layer
15,35 : 금속배선 콘택홀 17,37 : 제1금속배선15,35: metal wiring contact hole 17,37: first metal wiring
19,39 : 층간절연막 21,60 : 비아콘택홀19,39: interlayer insulating film 21,60: via contact hole
23,45 : 티타늄막 25 : 제2금속배선23,45: titanium film 25: second metal wiring
27 : 보호막 41 : 제1질화막27: protective film 41: first nitride film
43 : 제2질화막 47 : 제2금속배선 물질층43: second nitride film 47: second metal wiring material layer
49 : 감광막패턴 51 : 제3질화막49: photosensitive film pattern 51: third nitride film
53 : 제1보호막 55 : 제2보호막53: first protective film 55: second protective film
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 금속배선 형성방법은,In order to achieve the above object, a metal wiring forming method of a semiconductor device according to the present invention,
반도체기판에 접속되는 제1금속배선을 형성하는 공정과,Forming a first metal wiring connected to the semiconductor substrate;
상기 제1금속배선을 포함한 전체표면상부에 층간절연막을 형성하는 공정과,Forming an interlayer insulating film over the entire surface including the first metal wiring;
상기 층간절연막 상부에 제1질화막을 형성하는 공정과,Forming a first nitride film on the interlayer insulating film;
상기 제1질화막과 층간절연막을 식각하여 상기 제1금속배선을 노출시키는 비아콘택홀을 형성하는 공정과,Etching the first nitride film and the interlayer insulating film to form a via contact hole exposing the first metal wiring;
상기 비아콘택홀을 포함한 전체표면상부에 제2질화막을 형성하는 공정과,Forming a second nitride film on the entire surface including the via contact hole;
상기 제2질화막을 이방성식각하여 상기 비아콘택홀 측벽에 제2질화막 스페이서를 형성함으로써 상기 층간절연막의 노출면에 제1,2질화막을 형성하는 공정과,Anisotropically etching the second nitride film to form second nitride film spacers on the sidewalls of the via contact holes to form first and second nitride films on the exposed surface of the interlayer insulating film;
전체표면상부에 티타늄막을 형성하는 공정과,Forming a titanium film on the entire surface;
상기 비아콘택홀을 매립하는 제2금속배선을 형성하여 상기 제2금속배선과 층간절연막의 계면에 질화막과 티타늄막의 적층구조를 형성하는 공정과,Forming a second metal wiring to fill the via contact hole to form a stacked structure of a nitride film and a titanium film at an interface between the second metal wiring and the interlayer insulating film;
상기 제2금속배선 측벽에 제3질화막 스페이서를 형성하는 공정과,Forming a third nitride film spacer on the sidewalls of the second metal wiring lines;
전체표면상부에 수소기를 발생시키는 제1보호막을 형성하고 그 상부에 제2보호막을 형성하는 공정을 포함하는 것을 특징으로한다.And forming a first protective film that generates hydrogen groups on the entire surface, and a second protective film formed thereon.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e 는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.2A through 2E are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
먼저, 반도체기판(31)에 소자분리막, 워드라인, 비트라인 및 캐패시터가 구비되는 하부절연층(33)을 형성한다.First, a lower insulating layer 33 including an isolation layer, a word line, a bit line, and a capacitor is formed on the semiconductor substrate 31.
그리고, 상기 반도체기판(31)을 노출시키는 금속배선 콘택홀(35)을 형성한다.A metal wiring contact hole 35 exposing the semiconductor substrate 31 is formed.
이때, 상기 금속배선 콘택홀(35)은 금속배선 콘택마스크(도시안됨)를 이용한 사진식각공정으로 상기 하부절연층(33)을 식각하여 형성한다.In this case, the metal wiring contact hole 35 is formed by etching the lower insulating layer 33 by a photolithography process using a metal wiring contact mask (not shown).
그 다음, 상기 콘택홀(35)을 통하여 상기 반도체기판(31)에 접속되는 제1금속배선(37)을 형성한다.Next, a first metal wiring 37 connected to the semiconductor substrate 31 through the contact hole 35 is formed.
이때, 상기 제1금속배선(37)은 상기 금속배선 콘택홀(35)을 매립하는 제1금속배선 물질층을 전체표면상부에 형성하고 이를 제1금속배선 마스크를 이용한 사진식각공정으로 패터닝하여 형성한다.In this case, the first metal wiring 37 is formed by forming a first metal wiring material layer filling the metal wiring contact hole 35 on the entire surface and patterning it by a photolithography process using a first metal wiring mask. do.
그 다음, 상기 제1금속배선(37) 포함한 전체표면상부에 층간절연막(39)을 형성하고 이를 평탄화시킨다.Next, an interlayer insulating film 39 is formed on the entire surface including the first metal wiring 37 and flattened.
그리고, 상기 층간절연막(39) 상부에 제1질화막(41)을 일정두께 형성한다.A first nitride film 41 is formed on the interlayer insulating film 39 at a predetermined thickness.
그리고, 상기 제1금속배선(17)을 노출시키는 비아콘택홀(60)을 형성한다.In addition, a via contact hole 60 exposing the first metal wiring 17 is formed.
이때, 상기 비아콘택홀(60)은 비아콘택마스크(도시안됨)를 이용한 사진식각공정으로 상기 상기 제1질화막(41)과 층간절연막(39)을 식각하여 형성한다.In this case, the via contact hole 60 is formed by etching the first nitride layer 41 and the interlayer insulating layer 39 by a photolithography process using a via contact mask (not shown).
그 다음, 전체표면상부에 제2질화막(43)을 일정두께 형성한다. (도 2a)Then, a second nitride film 43 is formed on the entire surface at a constant thickness. (FIG. 2A)
그리고, 상기 제2질화막(43)을 이방성식각하여 상기 비아콘택홀(60)의 측벽에 제2질화막(43) 스페이서를 형성한다.The second nitride layer 43 is anisotropically etched to form a second nitride layer 43 spacer on the sidewall of the via contact hole 60.
그 다음 전체표면상부에 티타늄막(45)을 일정두께 형성한다.Then, a titanium film 45 is formed on the entire surface at a constant thickness.
그리고, 상기 비아콘택홀을 매립하는 제2금속배선 물질층(47)을 전체표면상부에 형성하고 이를 평탄화시킨다.In addition, a second metal wiring material layer 47 filling the via contact hole is formed on the entire surface and flattened.
그리고, 상기 제2금속배선 물질층(47) 상부에 감광막패턴(49)을 형성한다.The photoresist pattern 49 is formed on the second metal wiring material layer 47.
이때, 상기 감광막패턴(49)은 제2금속배선 마스크(도시안됨)를 이용한 노광 및 현상공정으로 형성한다. (도 2b)In this case, the photoresist pattern 49 is formed by an exposure and development process using a second metal wiring mask (not shown). (FIG. 2B)
그 다음, 상기 감광막패턴(49)을 마스크로하여 상기 제2금속배선물질층(47), 티타늄막(45) 및 제1질화막(41)을 식각함으로써 제2금속배선 물질층(47)으로 제2금속배선을 형성한다.Next, the second metal wiring material layer 47, the titanium film 45, and the first nitride film 41 are etched using the photosensitive film pattern 49 as a mask to form the second metal wiring material layer 47. 2 Form metal wiring.
그리고, 상기 제2금속배선을 포함한 전체표면상부에 제3질화막(51)을 전체표면상부에 일정두께 형성한다. (도 2c)Then, a third nitride film 51 is formed on the entire surface including the second metal wiring at a predetermined thickness on the entire surface. (FIG. 2C)
그 다음, 상기 제3질화막(51)을 이방성식각하여 상기 제2금속배선 측벽에 제3질화막(51) 스페이서를 형성한다. (도 2d)Next, the third nitride film 51 is anisotropically etched to form a third nitride film 51 spacer on the sidewall of the second metal wiring. (FIG. 2D)
그 다음, 전체표면상부에 제1보호막(53)을 형성하고 그 상부에 제2보호막(55)을 형성한다.Next, a first protective film 53 is formed on the entire surface, and a second protective film 55 is formed on the first protective film 53.
이때, 상기 제1보호막(53)은 수소기를 다량 발생시킬 수 있는 절연물질로 형성한다.In this case, the first passivation layer 53 is formed of an insulating material capable of generating a large amount of hydrogen groups.
그리고, 상기 제2보호막(55)은 질화막으로 형성하여 상기 제1보호막(53)의 수소기가 외부로 유출되지않도록 실시한다. (도 2e)In addition, the second passivation layer 55 is formed of a nitride layer so that the hydrogen groups of the first passivation layer 53 do not flow out. (FIG. 2E)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 금속배선 형성방법은, 티타늄막 하부에 질화막을 형성하고 후속 공정을 실시함으로써 수소기와 티타늄막의 반응을 방지하여 새로운 격자 결함의 발생을 방지하여 상기 격자 결함에 의한 누설전류의 증가를 방지함으로써 반도체소자의 리프레쉬 특성을 향상시키고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키며 반도체소자의 고집적화를 가능하게 하는 효과를 제공한다.As described above, in the method of forming metal wirings of the semiconductor device according to the present invention, by forming a nitride film under the titanium film and performing a subsequent process, the reaction between the hydrogen and the titanium film is prevented, thereby preventing the occurrence of new lattice defects. By preventing an increase in leakage current by the semiconductor device, the refresh characteristics of the semiconductor device are improved, thereby improving the characteristics and reliability of the semiconductor device, and providing high integration of the semiconductor device.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990066331A KR20010058955A (en) | 1999-12-30 | 1999-12-30 | A method for forming a metal line of a semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019990066331A KR20010058955A (en) | 1999-12-30 | 1999-12-30 | A method for forming a metal line of a semiconductor device |
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| KR20010058955A true KR20010058955A (en) | 2001-07-06 |
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| KR1019990066331A KR20010058955A (en) | 1999-12-30 | 1999-12-30 | A method for forming a metal line of a semiconductor device |
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