KR20010058944A - Forming method for transistor of semiconductor device - Google Patents
Forming method for transistor of semiconductor device Download PDFInfo
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- KR20010058944A KR20010058944A KR1019990066320A KR19990066320A KR20010058944A KR 20010058944 A KR20010058944 A KR 20010058944A KR 1019990066320 A KR1019990066320 A KR 1019990066320A KR 19990066320 A KR19990066320 A KR 19990066320A KR 20010058944 A KR20010058944 A KR 20010058944A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 11
- 229920005591 polysilicon Polymers 0.000 claims abstract description 11
- 239000011248 coating agent Substances 0.000 claims abstract description 3
- 238000000576 coating method Methods 0.000 claims abstract description 3
- 238000011049 filling Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 description 8
- 239000007943 implant Substances 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
Abstract
Description
본 발명은 반도체소자의 트랜지스터 형성방법에 관한 것으로, 특히 엘.디.디. ( lightly doped drain, 이하에서 LDD 라 함 ) 공정을 이용한 트랜지스터 형성공정시 유발될 수 있는 단점을 해결하기 위해 트렌치 식각후 이를 매립하는 도전층으로 불순물 접합영역을 형성하는 기술에 관한 것이다.The present invention relates to a method for forming a transistor of a semiconductor device, in particular L. D. D .. The present invention relates to a technology of forming an impurity junction region with a conductive layer filling a trench after etching to solve a disadvantage that may occur during a transistor forming process using a lightly doped drain (hereinafter referred to as LDD).
일반적으로, 반도체 메모리 소자인 디램은 하나의 캐패시터와 하나의 트랜지스터로 구성된다.In general, a DRAM, a semiconductor memory device, is composed of one capacitor and one transistor.
이때, 상기 트랜지스터는 반도체소자가 고집적화됨에따라 소자의 크기가 감소하는데 소자의 크기 특히 게이트의 길이가 작은 모스펫 ( MOSFET ) 에서는 상기 소자의 특성 열화는 매우 중요해 진다.At this time, the transistor size of the transistor decreases as the semiconductor device is highly integrated. In the MOSFET (MOSFET) having a small device size, particularly, the deterioration of characteristics of the device becomes very important.
이와같은 소자의 특성열화를 줄이기위하여 여러가지 구조를 사용하는데 대표적인 것이 엘.디.디. ( LDD : light doped drain, 이하에서 LDD 라 함 ) 구조이다.In order to reduce the deterioration of the characteristics of the device, a typical example is L.D.D. (LDD: light doped drain, hereinafter referred to as LDD) structure.
상기 LDD 구조는 가볍게 불순물을 주입시켜 드레인을 형성한 것으로서 채널의 전계를 감소시켜 소자의 특성열화를 감소시킨다.The LDD structure is a lightly implanted impurity to form a drain to reduce the electric field of the channel to reduce the deterioration of the characteristics of the device.
그러나, 상기 LDD 구조는 하기와 같은 여러 가지 문제점이 유발되어 반도체소자의 고집적화를 충족시키지 못하는 문제점이 있다.However, the LDD structure causes various problems as described below, which does not satisfy high integration of semiconductor devices.
먼저, 상기 LDD 구조는 임플란트 공정에 의해 소오스/드레인 접합영역을 형성하기 때문에 접합 캐패시턴스에 의한 RC 딜레이를 유발할 수 있다.First, since the LDD structure forms a source / drain junction region by an implant process, the LDD structure may cause an RC delay due to junction capacitance.
그리고, 상기 임플란트 공정시 발생된 실리콘 인터스티셜 확산이 채널 불순물 재분포를 유발하여 리버스 숏채널효과 ( reverse short channel effect )를 심화시킨다.In addition, the silicon interstitial diffusion generated during the implant process causes redistribution of channel impurities to deepen the reverse short channel effect.
그리고, 구조적으로 소오스/드레인 접합영역의 접합 누설전류에 의해 리프레쉬 ( refresh ) 특성이 열화된다.In addition, the refresh characteristic is deteriorated structurally by the junction leakage current in the source / drain junction region.
그리고, 임플란트 후 도펀트의 활성화를 위한 어닐링 공정이 필요로 하여 공정이 복잡하다.In addition, an annealing process for activating the dopant after the implant is required, and the process is complicated.
또한, 상기 임플란트 공정으로 소오스/드레인 접합영역을 형성하기 때문에 접합영역의 깊이를 조절하기 어렵다.In addition, since the source / drain junction region is formed by the implant process, it is difficult to control the depth of the junction region.
도 1a 내지 도 1c 는 종래기술에 따른 반도체소자의 트랜지스터 형성방법을 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a transistor forming method of a semiconductor device according to the prior art.
먼저, 반도체기판(11)에 활성영역을 정의하는 소자분리막(도시안됨)을 형성하고 상기 반도체기판(11)의 활성영역 상부에 게이트전극(13)을 형성한다.First, an isolation layer (not shown) defining an active region is formed on the semiconductor substrate 11, and a gate electrode 13 is formed on the active region of the semiconductor substrate 11.
이때, 상기 게이트전극(13)은 전체표면상부에 게이트전극 물질층을 형성하고 이를 게이트전극 마스크(도시안됨)를 이용한 사진식각공정으로 식각하여 형성한다. (도 1a)In this case, the gate electrode 13 is formed by forming a gate electrode material layer on the entire surface and etching it by a photolithography process using a gate electrode mask (not shown). (FIG. 1A)
그 다음, 상기 게이트전극(13)을 마스크로하여 상기 반도체기판(11)에 저농도의 불순물을 이온주입함으로써 저농도의 소오스/드레인 접합영역(15)을 형성한다. (도 1b)Next, a low concentration source / drain junction region 15 is formed by ion implanting impurities of low concentration into the semiconductor substrate 11 using the gate electrode 13 as a mask. (FIG. 1B)
그리고, 상기 게이트전극(13) 측벽에 절연막 스페이서(17)를 형성한다.An insulating film spacer 17 is formed on sidewalls of the gate electrode 13.
이때, 상기 절연막 스페이서(17)는 전체표면상부에 절연막을 일정두께 증착하고 이를 이방성식각하여 상기 게이트전극(13) 측벽에만 형성한 것이다.In this case, the insulating film spacers 17 are formed on only the sidewalls of the gate electrode 13 by depositing an insulating film a predetermined thickness on the entire surface and anisotropically etching them.
그 다음, 상기 게이트전그(13) 및 절연막 스페이서(17)를 마스크로 하여 상기 반도체기판(11)에 고농도의 불순물을 임플란트 하여 고농도의 소오스/드레인 접합영역(19)을 형성함으로써 LDD 구조의 트랜지스터를 형성한다. (도 1c)Next, a transistor having an LDD structure is formed by forming a high concentration source / drain junction region 19 by implanting a high concentration of impurities into the semiconductor substrate 11 using the gate signal 13 and the insulating layer spacer 17 as a mask. Form. (FIG. 1C)
상기한 바와같이 종래기술에 따른 반도체소자의 트랜지스터 형성방법은, 불순물을 임플란트하여 소오스/드레인 접합영역을 형성함으로써As described above, the method for forming a transistor of a semiconductor device according to the related art is performed by forming a source / drain junction region by implanting impurities.
접합 캐패시턴스에 의한 RC 딜레이를 유발할 수 있고, 상기 임플란트 공정시 발생된 실리콘 인터스티셜 확산이 채널 불순물 재분포를 유발하여 리버스 숏채널효과 ( reverse short channel effect )를 심화시키고, 구조적으로 발생되는 접합 누설전류에 의해 리프레쉬 ( refresh ) 특성이 열화되고, 임플란트 후 도펀트의 활성화를 위한 어닐링 공정이 필요로 하여 공정이 복잡하며 상기 임플란트 공정으로 소오스/드레인 접합영역을 형성하기 때문에 접합영역의 깊이를 조절하기 어려운 등의 문제점이 있어 반도체소자의 특성 및 신뢰성을 저하시키고 그에 따른 반도체소자의 수율 및 생산성을 저하시키는 문제점이 있다.Induced RC delay due to junction capacitance, silicon interstitial diffusion generated during the implant process causes redistribution of channel impurities, deepening reverse short channel effect and structurally occurring junction leakage It is difficult to control the depth of the junction area because the refresh characteristics are deteriorated by the current and the annealing process for activation of the dopant after implantation is complicated and the source / drain junction region is formed by the implant process. There is a problem such as lowering the characteristics and reliability of the semiconductor device and thereby lowering the yield and productivity of the semiconductor device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 소오스/드레인 접합영역에 트렌치를 형성하고 상기 트렌치를 폴리실리콘으로 매립하여 소오스/드레인 접합영역을 형성하여 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 트랜지스터 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, a trench is formed in a source / drain junction region and the trench is filled with polysilicon to form a source / drain junction region, thereby improving characteristics and reliability of the semiconductor device. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a transistor of a semiconductor device that enables high integration of the semiconductor device.
도 1a 내지 도 1c 는 종래기술에 따른 반도체소자의 트랜지스터 형성방법을 도시한 단면도.1A to 1C are cross-sectional views showing a transistor forming method of a semiconductor device according to the prior art.
도 2a 내지 도 2d 는 본 발명의 실시예에 따른 반도체소자의 트랜지스터 형성방법을 도시한 단면도.2A to 2D are cross-sectional views showing a transistor forming method of a semiconductor device according to an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11,21 : 반도체기판 13 : 게이트전극11,21: semiconductor substrate 13: gate electrode
15 : 저농도의 소오스/드레인 접합영역15: low concentration source / drain junction region
17 : 절연막 스페이서 19 : 고농도의 소오스/드레인 접합영역17 insulating film spacer 19 high concentration source / drain junction region
23 : 트렌치 25 : 산화막23: trench 25: oxide film
27 : 감광막패턴 29 : 폴리실리콘막27: photosensitive film pattern 29: polysilicon film
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 트랜지스터 형성방법은,In order to achieve the above object, a method of forming a transistor of a semiconductor device according to the present invention,
소오스/드레인 접합영역으로 예정된 영역의 반도체기판을 식각하여 트렌치를형성하는 공정과,Forming a trench by etching a semiconductor substrate in a predetermined region as a source / drain junction region;
상기 트렌치를 포함한 전체표면상부에 산화막을 일정두께 형성하는 공정과,Forming a thickness of an oxide film on the entire surface including the trench;
상기 트렌치 부분만을 도포하는 감광막패턴을 형성하는 공정과,Forming a photoresist pattern for coating only the trench portion;
상기 감광막패턴을 마스크로 하여 상기 산화막을 식각하여 상기 트렌치의 저부에만 산화막을 남기는 공정과,Etching the oxide film using the photoresist pattern as a mask to leave an oxide film only at the bottom of the trench;
상기 감광막패턴을 제거하고 상기 트렌치를 매립하는 평탄화된 도핑된 폴리실리콘막을 형성하여 소오스/드레인 접합영역을 형성하는 공정을 포함하는 것을 특징으로한다.Removing the photoresist pattern and forming a planarized doped polysilicon film filling the trench to form a source / drain junction region.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 및 도 2d 는 본 발명의 실시예에 따른 반도체소자의 트랜지스터 형성방법을 도시한 단면도이다.2A and 2D are cross-sectional views illustrating a method of forming a transistor in a semiconductor device according to an embodiment of the present invention.
먼저, 반도체기판(21)의 활성영역을 정의하는 소자분리막을 형성한다.First, an isolation layer defining an active region of the semiconductor substrate 21 is formed.
그리고, 반도체소자의 활성영역에 소오스/드레인 접합영역으로 예정된 영역의 상기 반도체기판(21)을 일정깊이 식각하여 트렌치(23)를 형성한다.The trench 23 is formed by etching the semiconductor substrate 21 in a predetermined region as a source / drain junction region in the active region of the semiconductor device.
그 다음, 상기 트렌치(23) 표면을 포함한 전체표면상부에 산화막(25)을 일정두께 형성한다. (도 2a)Next, an oxide film 25 is formed on the entire surface including the surface of the trench 23 with a predetermined thickness. (FIG. 2A)
그리고, 상기 트렌치(23) 저부 상측을 도포하는 감광막패턴(27)을 형성한다. 이때, 상기 감광막패턴(27)은 전체표면상부에 감광막을 도포하고 이를 소오스/드레인 접합영역만을 노출시키는 노광마스크(도시안됨)를 이용한 노광 및 현상공정으로 패터닝하여 형성한다.Then, the photoresist pattern 27 is formed to apply the upper portion of the bottom of the trench 23. In this case, the photoresist layer pattern 27 is formed by applying a photoresist layer on the entire surface and patterning the photoresist layer using an exposure mask (not shown) that exposes only the source / drain junction region.
그리고, 상기 감광막패턴(27)을 마스크로하여 상기 산화막(25)을 식각함으로써 상기 트렌치(23) 저부에만 산화막(25)을 남긴다. (도 2b)Then, the oxide film 25 is etched by using the photosensitive film pattern 27 as a mask to leave the oxide film 25 only at the bottom of the trench 23. (FIG. 2B)
그 다음, 상기 감광막패턴(27)을 제거하고 상기 트렌치(23)를 매립하는 폴리실리콘막(29)을 전체표면상부에 형성한다.Next, the photoresist layer pattern 27 is removed and a polysilicon layer 29 filling the trench 23 is formed on the entire surface.
이때, 상기 폴리실리콘막(29)은 불순물이 도핑된 것이다. (도 2c)At this time, the polysilicon layer 29 is doped with impurities. (FIG. 2C)
그 다음, 상기 폴리실리콘막(29)을 평탄화식각하여 트렌치(23) 저부에 산화막(25)이 구비되고 그 상부를 폴리실리콘막(29)으로 매립하는 소오스/드레인 접합영역을 형성한다.Next, the polysilicon layer 29 is planarized and etched to form a source / drain junction region in which the oxide layer 25 is provided at the bottom of the trench 23 and the upper portion is filled with the polysilicon layer 29.
후속공정으로 게이트전극(도시안됨)을 형성하여 트랜지스터를 형성한다. (도 2d)In a subsequent process, a gate electrode (not shown) is formed to form a transistor. (FIG. 2D)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 트랜지스터 형성방법은, 산화막 상부에 소오스/드레인 접합영역을 형성하여 접합 캐패시턴스를 감소시키고 접합 누설전류를 감소시켜 리프레쉬 특성을 향상시키며, 실리콘 인더스티셜의 유발을 방지할 수 있어 일정한 채널 도펀트를 유지할 수 있고 그로인해 리버스 숏채널효과를 감소시키며, 도펀트의 활성화를 위한 어닐링공정을 생략할 수 있고 접합영역의 깊이를 트렌치 깊이로 조절할 수 있어 조절이 용이하여 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 수율 및 신뢰성을 향상시킬 수 있는 효과를 제공한다.As described above, in the method of forming a transistor of a semiconductor device according to the present invention, a source / drain junction region is formed on an oxide layer to reduce junction capacitance, reduce junction leakage current, and improve refresh characteristics, and induce silicon industrial. It is possible to maintain a constant channel dopant, thereby reducing the reverse short channel effect, to omit the annealing process for activation of the dopant, and to adjust the depth of the junction region to the depth of the trench for easy adjustment. It provides an effect that can improve the characteristics and reliability of the device and thereby improve the yield and reliability of the semiconductor device.
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