KR20070107936A - Method for manufacturing a semiconductor device having bulb type gate - Google Patents

Method for manufacturing a semiconductor device having bulb type gate Download PDF

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KR20070107936A
KR20070107936A KR1020060040526A KR20060040526A KR20070107936A KR 20070107936 A KR20070107936 A KR 20070107936A KR 1020060040526 A KR1020060040526 A KR 1020060040526A KR 20060040526 A KR20060040526 A KR 20060040526A KR 20070107936 A KR20070107936 A KR 20070107936A
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gate electrode
semiconductor substrate
threshold voltage
region
electrode region
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KR1020060040526A
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Korean (ko)
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김동석
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주식회사 하이닉스반도체
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Publication of KR20070107936A publication Critical patent/KR20070107936A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method for manufacturing a semiconductor device having a bulb type gate electrode is provided to obtain a stable threshold voltage by implanting ions for regulating the threshold voltage in a bulb type gate electrode region. A spacer oxide layer(120) is removed and a gate oxide layer(140) is formed by oxidizing a semiconductor substrate(100) having a gate electrode region(125). A doped polysilicon film(145) is formed to fill sufficiently the gate electrode region. A transition metal silicide film(150) is formed at the doped polysilicon layer, and then a hard mask(155) is deposited thereon. After patterning the transition metal silicide film, the hard mask and the polysilicon film, a gate spacer(165) is formed. Thus, a gate electrode construction is completed.

Description

벌브형 게이트 전극을 갖는 반도체 소자의 제조방법{Method for manufacturing a semiconductor device having bulb type gate} Method for manufacturing a semiconductor device having a bulb type gate electrode

도 1a 내지 도 1e는 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위한 각 공정별 단면도이다.1A to 1E are cross-sectional views of respective processes for explaining a method of manufacturing a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

100: 반도체 기판 120: 스페이서용 산화막100: semiconductor substrate 120: oxide film for spacer

125 : 게이트 전극 영역 130 : 플라즈마화된 이온 소스125 gate electrode region 130 plasmaized ion source

135 : 문턱 전압 조절 이온 영역135: Threshold voltage control ion region

본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 구체적으로는 반도체 소자의 문턱 전압 조절 이온 주입방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for implanting threshold voltage controlled ion of a semiconductor device.

반도체 소자의 집적 밀도가 증가함에 따라, 모스 트랜지스터의 크기 즉, 채널 길이가 스케일된다. 채널 길이가 감소되면 반도체 소자의 집적 밀도는 개선되나, 드레인 유기 장벽 저하(DIBL:drain induced barrier lowering), 핫 캐리어 이펙트(hot carrier effect) 및 펀치 스루(punch through)와 같은 단채널 효과(short channel effect)가 발생된다. As the integration density of the semiconductor device increases, the size of the MOS transistor, that is, the channel length, scales. Reducing the channel length improves the integration density of semiconductor devices, but short channel effects such as drain induced barrier lowering (DIBL), hot carrier effect, and punch through effect) occurs.

이러한 단채널 효과를 줄이기 위해서는 셀 트랜지스터의 문턱 전압 및 셀 커런트를 적절히 유지하는 것이 중요하고, 문턱 전압 및 셀 커런트를 조절하기 위하여, 리세스(recessed) 게이트 방식이 제안되었다. 상기 리세스 게이트 방식은 반도체 기판의 게이트 예정 영역에 리세스를 형성하고, 리세스 부분에 문턱 전압 조절 이온을 주입한다음, 이 리세스 내부에 게이트 물질을 충진시켜 게이트 전극을 형성한다. 현재에는 리세스 모서리 부분의 전게 집중등의 문제를 해결할 수 있도록 상기 리세스를 구(球) 형태로 형성하는 벌브 타입(bulb) 타입 게이트 전극이 개발되었다. In order to reduce such a short channel effect, it is important to properly maintain the threshold voltage and the cell current of the cell transistor, and a recessed gate method has been proposed to adjust the threshold voltage and the cell current. In the recess gate method, a recess is formed in a gate predetermined region of a semiconductor substrate, a threshold voltage regulating ion is implanted into the recess portion, and a gate material is filled in the recess to form a gate electrode. Currently, a bulb type gate electrode has been developed in which the recess is formed in a spherical shape so as to solve a problem such as concentration of electric charges in a recess edge portion.

그런데, 종래의 문턱 전압 조절 이온은 일반적인 빔 라인 커런트(beam line current)를 이용하는 이온 주입 장치에 의해 주입되고 있으나, 상기 빔 라인 방식의 이온 주입 장치는 벌브 형태의 기판 표면(이하, 벌브 영역)에 고르게 불순물을 주입할 수 없다는 단점을 갖는다. 즉, 벌브 영역의 깊이 만큼 이온 주입 에너지를 상승시켜, 즉, 이온 주입 깊이를 증대시켜야만 벌브 영역내에 이온 주입이 가능해진다. By the way, while the conventional threshold voltage control ion is implanted by an ion implantation apparatus using a general beam line current (beam line current), the ion implantation apparatus of the beam line method is a bulb type substrate surface (hereinafter, bulb region) The disadvantage is that it is impossible to inject impurities evenly. That is, the ion implantation energy must be increased by the depth of the bulb region, that is, the ion implantation depth must be increased to enable ion implantation into the bulb region.

이로 인해, 상기와 같이 이온 주입 에너지를 증대시켜 이온 주입 공정을 실시하면, 벌브 영역 외에 다른 영역에 까지 문턱 전압 조절 이온이 주입되어, 스토리지 노드에서의 전계를 상승시켜 접합 누설을 일으키거나 항복 전압 특성을 저하시킨다. Therefore, when the ion implantation process is performed by increasing the ion implantation energy as described above, the threshold voltage regulating ions are implanted in the region other than the bulb region, which raises the electric field at the storage node to cause junction leakage or breakdown voltage characteristics. Lowers.

따라서, 본 발명의 목적은 벌브 형태의 게이트 예정 영역에 문턱 전압 조절 이온을 고르게 주입시킬 수 있는 벌브 타입 게이트 전극을 갖는 반도체 소자의 제조방법을 제공하는 것이다. Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device having a bulb type gate electrode capable of evenly injecting threshold voltage control ions into a bulb-type gate predetermined region.

상기한 본 발명의 목적을 달성하기 위하여, 본 발명은, 반도체 기판의 선택된 영역에 벌브(bulb) 형태의 게이트 전극 영역을 형성한다음, 상기 게이트 전극 영역에 문턱 전압 조절용 이온 소스를 플라즈마 상태로 만들어, 상기 이온 소스를 도핑시킨다. 그 다음, 상기 이온 주입 영역에 게이트 전극을 형성한다.In order to achieve the above object of the present invention, the present invention, by forming a bulb-shaped gate electrode region in the selected region of the semiconductor substrate, and by making the ion source for adjusting the threshold voltage in the gate electrode region into a plasma state Doping the ion source. Next, a gate electrode is formed in the ion implantation region.

이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 설명하도록 한다. Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

도 1a 내지 도 1e는 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위한 각 공정별 단면도이다.1A to 1E are cross-sectional views of respective processes for explaining a method of manufacturing a semiconductor device according to the present invention.

도 1a를 참조하면, 반도체 기판(100) 상부에 패드 산화막(105) 및 마스크막(110)을 순차적으로 증착한다. 마스크막(110)으로는 폴리실리콘막 또는 실리콘 질화막이 이용될 수 있다. 마스크막(110) 상부에 게이트 전극 영역을 노출시키는 포토레지스트 패턴(115)을 공지의 포토리소그라피 공정에 의해 형성한다. Referring to FIG. 1A, the pad oxide layer 105 and the mask layer 110 are sequentially deposited on the semiconductor substrate 100. As the mask film 110, a polysilicon film or a silicon nitride film may be used. The photoresist pattern 115 exposing the gate electrode region on the mask film 110 is formed by a known photolithography process.

도 1b를 참조하면, 포토레지스트 패턴(115)의 형태로 마스크막(110) 및 패드 산화막(105)을 식각한 다음, 포토레지스트 패턴(115)을 제거한다. 다음, 잔류하는 마스크막(110)을 식각 마스크로 하여 반도체 기판(100)을 소정 두께만큼 식각하여, 트렌치를 형성한다. 상기 잔류하는 마스크막(110) 및 패드 산화막(105)을 제거한다. 그리고 나서, 상기 반도체 기판(100) 결과물 상부에 스페이서용 산화막(120)을 형성한다음, 트렌치 저면이 노출될 수 있도록 스페이서용 산화막(120)을 식각한다. 이때, 스페이서용 산화막(120)의 식각은 포토 리소그라피를 이용한 식각 방식을 이용하거나 혹은 비등방성 에치백 식각 방식을 이용할 수 있다. Referring to FIG. 1B, the mask layer 110 and the pad oxide layer 105 are etched in the form of the photoresist pattern 115, and then the photoresist pattern 115 is removed. Next, the semiconductor substrate 100 is etched by a predetermined thickness using the remaining mask film 110 as an etching mask to form a trench. The remaining mask film 110 and the pad oxide film 105 are removed. Then, after forming the spacer oxide film 120 on the semiconductor substrate 100, the spacer oxide film 120 is etched to expose the bottom of the trench. In this case, the etching of the spacer oxide layer 120 may use an etching method using photolithography or an anisotropic etch back etching method.

그후, 도 1c에 도시된 바와 같이, 스페이서용 산화막(120)을 마스크로 하여, 상기 반도체 기판(100)을 등방성 또는 비이방성 식각함으로써, 벌브 형태의 게이트 전극 영역(125)을 형성한다. 게이트 전극 영역(125)은 상기 노출된 반도체 기판(100)을 습식 식각하므로써 얻어질 수 있다.Thereafter, as shown in FIG. 1C, the semiconductor substrate 100 is isotropically or anisotropically etched using the spacer oxide film 120 as a mask to form a bulb-type gate electrode region 125. The gate electrode region 125 may be obtained by wet etching the exposed semiconductor substrate 100.

다음, 도 1d를 참조하면, 벌브 형태의 게이트 전극 영역(125) 표면에 문턱 전압 조절 이온을 주입하기 위하여 예컨대 BF3 소스를 플라즈마화한 상태에서 보론 이온을 또는 11B 또는 49BF2 이온을 주입한다. 플라즈마 형태의 불순물은 등방성 형태로 도핑됨에 따라, 상기 벌브 형태의 게이트 전극 영역에 문턱 전압 조절용 이온이 고르게 이온 주입된다. 여기서, 도면 부호 130은 플라즈마화된 문턱 전압 조절 이온 소스를 나타내고, 135는 문턱 전압 조절 이온 영역을 나타낸다. 이때, 문턱 전압 조절 이온으로서 BF3 소스를 사용하였지만, MOS 트랜지스터의 타입에 따라 다른 소스를 사용할 수 있음은 자명하다. Next, referring to FIG. 1D, boron ions or 11B or 49BF 2 ions are implanted in a plasma state of a BF 3 source, for example, to implant threshold voltage control ions into the bulb-type gate electrode region 125. As the impurities in the plasma form are doped in an isotropic form, the ion for threshold voltage is evenly implanted into the bulb-shaped gate electrode region. Here, reference numeral 130 denotes a plasmalized threshold voltage regulating ion source and 135 denotes a threshold voltage regulating ion region. At this time, although the BF 3 source is used as the threshold voltage control ion, it is obvious that other sources can be used depending on the type of the MOS transistor.

도 1e를 참조하면, 스페이서용 산화막(120)을 공지의 방식으로 제거한다음, 게이트 전극 영역(125)을 포함하는 반도체 기판(100)을 산화시켜 게이트 산화 막(140)을 형성한다. 이후, 벌브 형태의 게이트 전극 영역(125)이 충분히 매립되도록 도핑된 폴리실리콘막(145)을 형성하고, 도핑된 폴리실리콘막(145) 상부에 전이 금속 실리사이드막(150)을 형성한다음, 전이 금속 실리사이드막(150) 상부에 하드 마스크막(155)을 증착한다. 이어서, 하드 마스크막(155), 전이 금속 실리사이드막(150) 및 도핑된 폴리실리콘막(145)을 패터닝한다음, 도핑된 폴리실리콘막(145), 전이 금속 실리사이드막(150) 및 하드 마스크막(155)으로 구성된 구조물 측벽에 공지의 방식으로 게이트 스페이서(165)을 형성하여, 게이트 전극 구조체(165)를 완성한다. Referring to FIG. 1E, the spacer oxide film 120 is removed in a known manner, and then the semiconductor substrate 100 including the gate electrode region 125 is oxidized to form the gate oxide film 140. Thereafter, the doped polysilicon layer 145 is formed to sufficiently fill the gate electrode region 125 having a bulb shape, and the transition metal silicide layer 150 is formed on the doped polysilicon layer 145. The hard mask layer 155 is deposited on the metal silicide layer 150. Next, the hard mask layer 155, the transition metal silicide layer 150, and the doped polysilicon layer 145 are patterned, and then the doped polysilicon layer 145, the transition metal silicide layer 150, and the hard mask layer are patterned. A gate spacer 165 is formed on the sidewall of the structure composed of 155 in a known manner to complete the gate electrode structure 165.

이상에서 자세히 설명한 바와 같이, 본 발명에 의하면, 게이트 전극 영역을 벌브 형태로 형성한 다음, 문턱 전압 조절용 이온 소스를 플라즈마화 하여 도핑을 실시한다. 이에 의해, 상기 벌브 형태의 게이트 전극 영역에 문턱 전압 조절 이온을 고르게 주입하므로써, 안정한 문턱 전압을 확보할 수 있으며, 나아가 접합 누설 전류를 줄일 수 있다.As described above in detail, according to the present invention, the gate electrode region is formed in a bulb shape, and then the doping is performed by plasmalizing the ion source for adjusting the threshold voltage. As a result, a stable threshold voltage can be ensured by evenly injecting threshold voltage control ions into the bulb-type gate electrode region, thereby further reducing a junction leakage current.

이상 본 발명을 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 사상의 범위 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러가지 변형이 가능하다.Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. .

Claims (3)

반도체 기판의 선택된 영역에 벌브(bulb) 형태의 게이트 전극 영역을 형성하는 단계;Forming a bulb-shaped gate electrode region in a selected region of the semiconductor substrate; 상기 게이트 전극 영역에 문턱 전압 조절용 이온 소스를 플라즈마 상태로 만들어, 상기 이온 소스를 도핑시키는 단계; 및Doping the ion source by making a threshold voltage control ion source in a plasma state in the gate electrode region; And 상기 이온 주입 영역에 게이트 전극을 형성하는 단계를 포함하는 반도체 소자의 제조방법. Forming a gate electrode in the ion implantation region. 제 1 항에 있어서, 상기 게이트 전극 영역을 형성하는 단계는,The method of claim 1, wherein the forming of the gate electrode region comprises: 상기 반도체 기판상에 게이트 전극이 노출될 수 있도록 마스크 패턴을 형성하는 단계;Forming a mask pattern on the semiconductor substrate to expose a gate electrode; 상기 마스크 패턴의 형태로 상기 반도체 기판을 소정 깊이 만큼 식각하여 트렌치를 형성하는 단계;Forming a trench by etching the semiconductor substrate to a predetermined depth in the form of the mask pattern; 상기 트렌치의 저부가 노출되도록 스페이서용 산화막을 형성하는 단계; 및Forming an oxide film for a spacer to expose a bottom portion of the trench; And 상기 스페이서용 산화막을 마스크로 하여, 노출된 트렌치 저부의 반도체 기판을 식각하는 단계를 포함하는 반도체 소자의 제조방법.Etching the semiconductor substrate at the bottom of the exposed trench using the spacer oxide film as a mask. 제 1 항에 있어서, 상기 트렌치 저부의 반도체 기판을 식각하는 단계는 반도체 기판을 습식 식각하는 단계인 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the etching of the semiconductor substrate at the bottom of the trench is a wet etching of the semiconductor substrate.
KR1020060040526A 2006-05-04 2006-05-04 Method for manufacturing a semiconductor device having bulb type gate KR20070107936A (en)

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Publication number Priority date Publication date Assignee Title
CN114743880A (en) * 2022-04-12 2022-07-12 上海晶岳电子有限公司 Power semiconductor groove size control method and power semiconductor structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114743880A (en) * 2022-04-12 2022-07-12 上海晶岳电子有限公司 Power semiconductor groove size control method and power semiconductor structure
CN114743880B (en) * 2022-04-12 2023-06-06 上海晶岳电子有限公司 Power semiconductor groove size control method and power semiconductor structure

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