KR20010058450A - Method For Forming The Tungsten Plug Of Semiconductor Device - Google Patents
Method For Forming The Tungsten Plug Of Semiconductor Device Download PDFInfo
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- KR20010058450A KR20010058450A KR1019990065782A KR19990065782A KR20010058450A KR 20010058450 A KR20010058450 A KR 20010058450A KR 1019990065782 A KR1019990065782 A KR 1019990065782A KR 19990065782 A KR19990065782 A KR 19990065782A KR 20010058450 A KR20010058450 A KR 20010058450A
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- tungsten plug
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 title claims abstract description 40
- 229910052721 tungsten Inorganic materials 0.000 title claims abstract description 40
- 239000010937 tungsten Substances 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000010410 layer Substances 0.000 claims abstract description 52
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 239000011229 interlayer Substances 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 16
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims abstract description 16
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 15
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000010936 titanium Substances 0.000 claims abstract description 15
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000010030 laminating Methods 0.000 claims abstract description 3
- 238000000151 deposition Methods 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 20
- 238000000137 annealing Methods 0.000 description 6
- 230000005669 field effect Effects 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체장치에서 금속배선라인을 형성하는 방법에 관한 것으로서, 특히, 반도체기판 상에 메탈1을 형성하고, 층간절연막에 금속층을 매립하여 텅스텐프러그를 형성한 후, 층간절연막을 일정 두께로 식각하여 금속플러그를 노출시킨 후 티타늄층을 적층하여 어닐링공정으로 금속플러그 상에 넓은 면적을 갖는 티타늄텅스텐층을 형성하므로 후속 공정에서 마아진을 확보하도록 하는 반도체장치의 텅스텐플러그 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring line in a semiconductor device. In particular, a metal 1 is formed on a semiconductor substrate, a tungsten plug is formed by embedding a metal layer in an interlayer insulating film, and then the interlayer insulating film is etched to a predetermined thickness. The present invention relates to a method for forming a tungsten plug of a semiconductor device in which a titanium tungsten layer having a large area is formed on the metal plug by annealing by exposing the metal plug to expose the metal plug.
일반적으로, 반도체장치의 종류에는 여러 가지가 있고, 이 반도체장치 내에 형성되는 트랜지스터 및 커패시터등을 구성시키는 방법에는 다양한 제조기술이 사용되고 있으며, 최근에는 반도체기판 상에 산화막을 입혀 전계효과를 내도록 하는 모스형 전계효과트랜지스터(MOSFET; metal oxide semiconductor field effect transistor)와, 실리콘기판에 비하여 전자의 이동 속도가 6배나 큰 갈륨아세나이드 (GaAs)를 기판으로 사용하여 전계효과를 내는 메스형 전계효과트랜지스터(MESFET; metal semiconductor field effect transistor)와, 그 이외에 절연 게이트형 전계효과 트랜지스터(IGEFT; insulator gate field effect transistor) 등의 다양한 방식의 반도체장치가 사용되고 있다.In general, there are many kinds of semiconductor devices, and various manufacturing techniques are used to configure transistors, capacitors, and the like formed in the semiconductor device. In recent years, MOS is formed by applying an oxide film on a semiconductor substrate to produce an electric field effect. MESH-type field effect transistors (MESFETs) and gallium arsenide (GaAs), which have six times the electron movement speed compared to silicon substrates, as a substrate, and have a mes-type field effect transistor (MESFET). semiconductor devices of various types such as metal semiconductor field effect transistors and insulator gate field effect transistors (IGEFTs).
이와 같이, 반도체장치에는 배선라인(Metal Line)과 배선라인을 서로 연결하기 위하여 텅스텐층을 증착한 후에 식각하여서 상부배선라인과 하부배선라인을 서로 연결시키는 텅스텐 플러그(Tungsten Plug)를 형성시켜서 사용하고 있다.As such, in the semiconductor device, a tungsten plug is formed by depositing a tungsten layer and then etched to connect the wiring line (metal line) and the wiring line to each other, thereby connecting the upper wiring line and the lower wiring line to each other. have.
도 1은 종래의 제1실시예에 의한 텅스텐플러그의 형성구조를 보인 도면이고, 도 2는 종래의 제2실시예에 의한 텅스텐플러그의 형성구조를 보인 도면으로서, 반도체기판(1)(1a) 상에 소정의 하부구조를 형성한 후에 금속층을 적층하여 식각하여 메탈1(2)(2a)을 형성하도록 한다.FIG. 1 is a view showing a structure of forming a tungsten plug according to a first embodiment of the present invention, and FIG. 2 is a view showing a structure of forming a tungsten plug according to a second embodiment of the present invention, and includes a semiconductor substrate 1 (1a). After forming a predetermined substructure on the metal layer to be laminated and etched to form the metal 1 (2) (2a).
그리고, 상기 결과물 상에 층간절연막(3)(3a)을 적층하여 마스킹식각으로 비아홀을 형성한 후, 이 비아홀내에 텅스텐을 매립하고, 화학기계적연마공정으로 결과물을 평탄화한 후에 상부에 메탈2(5)(5a)를 형성하도록 한다.After the interlayer insulating films 3 and 3a are stacked on the resultant, via holes are formed by masking etching, tungsten is embedded in the via holes, and the resultant is flattened by chemical mechanical polishing. (5a).
한편, 상기 제1실시예의 경우에는 메탈2(5)가 텅스텐플러그(4)의 상부면에 넓게 오버랩(Overlap)되는 랜디드 비아(Landed Via) 타입이고, 상기 제2실시예의 경우에는 메탈2(5a)가 텅스텐프러그(4)에 정확하게 위치가 맞는 언랜디드 비아 (Unlanded Via) 타입이다.On the other hand, in the case of the first embodiment, the metal 2 5 is a landed via type that overlaps widely on the upper surface of the tungsten plug 4, and in the case of the second embodiment, the metal 2 5 5a) is an unlanded via type that is exactly positioned on the tungsten plug 4.
그런데, 최근 들어서 칩 설계 디자인 룰이 타이트해지면서 메탈과 비아의 오버랩이 거의 없는 제2실시예의 언랜디드 비아타입의 공정을 사용하여 텅스텐플러그 (4a)에 메탈2(5a)를 정확하게 위치를 맞추어서 형성하도록 하고 있으나, 이 경우에 상위 메탈 패터닝과정에서 오버레이 베리에이션(Overlay Variation)에 의하여 메탈2(5a)의 미스얼라인(Misalign)으로 인하여 비아 저항(Via Resistance))이 커지고 그로 인하여 소자의 전기적인 특성이 저하되는 문제점을 지닌다.However, in recent years, as the chip design rules become tighter, the metal 2 (5a) is accurately positioned on the tungsten plug (4a) using the unlanded via type process of the second embodiment with little overlap between the metal and the via. In this case, the via resistance is increased due to misalignment of the metal 2 (5a) due to the overlay variation during the upper metal patterning process, and thus the device electrical It has a problem of deterioration of characteristics.
본 발명은 이러한 점을 감안하여 안출한 것으로서, 반도체기판 상에 메탈1을 형성하고, 층간절연막에 금속층을 매립하여 텅스텐프러그를 형성한 후, 층간절연막을 일정 두께로 식각하여 금속플러그를 노출시킨 후 티타늄층을 적층하여 어닐링공정으로 금속플러그 상에 넓은 면적을 갖는 티타늄텅스텐층을 형성하므로 후속 공정에서 마아진을 확보하는 것이 목적이다.The present invention has been made in view of the above-described problems, metal 1 is formed on a semiconductor substrate, and a metal layer is embedded in an interlayer insulating film to form a tungsten plug, and the interlayer insulating film is etched to a predetermined thickness to expose the metal plug. Since the titanium layer is laminated to form a titanium tungsten layer having a large area on the metal plug by an annealing process, an object is to secure the margin in a subsequent process.
도 1은 종래의 일실시예에 따른 텅스텐플러그의 형성구조를 보인 도면이고,1 is a view showing a structure of forming a tungsten plug according to a conventional embodiment,
도 2는 종래의 다른 실시예에 따른 텅스텐플러그의 형성구조를 보인 도면이며,2 is a view showing a structure of forming a tungsten plug according to another conventional embodiment,
도 3a 내지 도 3i은 본 발명에 따른 텅스텐플러그 형성방법을 순차적으로 보인 도면이다.3A to 3I are views sequentially showing a tungsten plug forming method according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10 : 반도체기판 15 : 메탈110: semiconductor substrate 15: metal 1
20 : 층간절연막 25 : 콘택홀20: interlayer insulating film 25: contact hole
30 : 티타늄막 35 : 티타늄질화막30: titanium film 35: titanium nitride film
40 : 텅스텐층 45 : 텅스텐플러그40: tungsten layer 45: tungsten plug
50 : 티타늄층 55 : 티타늄질화막50: titanium layer 55: titanium nitride film
60 : 티타늄텅스텐층60: titanium tungsten layer
이러한 목적은 반도체기판 상에 메탈라인을 형성한 후, 층간절연막을 적층하여, 식각으로 콘택홀을 형성하는 단계와; 상기 콘택홀 내에 텅스텐 폴리2층을 형성하는 단계와; 상기 단계 후에 상기 층간절연막을 일정 두께 식각하여 텅스텐플러그를 노출시키는 단계와; 상기 결과물 상에 티타늄층을 적층하는 단계와; 상기 결과물을 급속열처리하여 노출된 텅스텐플러그를 티타늄텅스텐층으로 다른 부위의 티타늄층을 티타늄질화층으로 형성하는 단계와; 상기 티타늄질화층을 식각으로 제거하여 티타늄텅스텐층을 노출시키는 단계로 구성된 것을 특징으로 하는 반도체장치의 텅스텐플러그 형성방법을 제공함으로써 달성된다.This object is achieved by forming a metal line on a semiconductor substrate and then laminating an interlayer insulating film to form a contact hole by etching; Forming a tungsten poly2 layer in the contact hole; Exposing the tungsten plug by etching the interlayer insulating film to a predetermined thickness after the step; Depositing a titanium layer on the resultant; Rapidly heat-treating the resultant to form an exposed tungsten plug as a titanium tungsten layer and a titanium layer at another portion as a titanium nitride layer; It is achieved by providing a method for forming a tungsten plug of a semiconductor device, characterized in that the titanium nitride layer is removed by etching to expose the titanium tungsten layer.
그리고, 상기 텅스텐플러그를 노출하기 위한 층간절연막의 식각은, 300 ∼ 500Å의 두께로 진행하는 것이 바람직하다.In addition, the etching of the interlayer insulating film for exposing the tungsten plug is preferably performed at a thickness of 300 to 500 kPa.
상기 층간절연막의 식각은, 건식식각(Dry Etch)으로 진행하고, 100 ∼ 200 : 1의 비율로 희석된 HF용액을 사용하여 식각하는 것이 바람직 하다.The etching of the interlayer insulating film is performed by dry etching, and is preferably etched using an HF solution diluted at a ratio of 100 to 200: 1.
상기 텅스텐플러그 상에 적층되는 티타늄층은, 스퍼터링 증착법으로, 300 ∼500Å의 두께로 적층하는 것이 바람 직하다.The titanium layer laminated on the tungsten plug is preferably laminated at a thickness of 300 to 500 kPa by the sputtering deposition method.
상기 티타늄텅스텐층을 형성하기 위한 어닐링공정은, 급속열처리법(RTP; Rapid Thermal Processing)으로, 400 ∼ 450℃의 온도범위에서 진행하는 것이 바람직 하다.The annealing process for forming the titanium tungsten layer is preferably carried out in a temperature range of 400 to 450 ° C. by Rapid Thermal Processing (RTP).
상기 티타늄질화층을 제거할 때, 10 ∼ 20중량%의 NH4OH 수용액을 사용하는 것이 바람직 하다.When removing the titanium nitride layer, it is preferable to use 10 to 20% by weight aqueous NH 4 OH.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 일실시예에 대해 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도 3a 내지 도 3c에 도시된 바와 같이, 반도체기판(10)상에 메탈1(15)을 형성한 후, 층간절연막(20)을 적층하여, 마스킹식각으로 콘택홀(25)을 형성하도록 한다.As shown in FIGS. 3A to 3C, after the metal 1 15 is formed on the semiconductor substrate 10, the interlayer insulating layer 20 is stacked to form the contact hole 25 by masking etching.
도 3d에 도시된 바와 같이, 상기 콘택홀(25)내에 티타늄막(30) 및 티타늄질화막(35)을 순차적으로 박막의 상태로 적층한 후, 콘택홀(25)내에 텅스텐층(40)을 매립하도록 한다.As shown in FIG. 3D, the titanium film 30 and the titanium nitride film 35 are sequentially stacked in the contact hole 25 in the form of a thin film, and then the tungsten layer 40 is buried in the contact hole 25. Do it.
그리고, 도 3e에 도시된 바와 같이, 상기 결과물을 화학기계적연마법(CMP; Chemical Mechanical Polishing)으로 평탄화하도록 한다.And, as shown in FIG. 3e, the resultant is planarized by chemical mechanical polishing (CMP).
도 3f에 도시된 바와 같이, 상기 결과물에서 상기 층간절연막(20)을 일정 두께, 바람직 하게는 300 ∼ 500Å의 두께를 식각하여 텅스텐플러그(45)를 노출시키도록 한다.As shown in FIG. 3F, the interlayer insulating film 20 is etched in a predetermined thickness, preferably 300 to 500 kPa, to expose the tungsten plug 45.
상기 층간절연막(20)의 식각은, 건식식각으로 진행하고, 100 ∼ 200 : 1의비율로 희석된 HF용액을 사용하여 식각하는 것이 바람직 하다.The etching of the interlayer insulating film 20 is performed by dry etching, and is preferably etched using an HF solution diluted at a ratio of 100 to 200: 1.
도 3g에 도시된 바와 같이, 상기 결과물 상에 티타늄층(50)을 스퍼터링 증착법으로, 300 ∼ 500Å의 두께로 적층하도록 한다.As shown in FIG. 3G, the titanium layer 50 is deposited on the resultant by sputtering deposition to a thickness of 300 to 500 kPa.
도 3h에 도시된 바와 같이, 상기 결과물을 어닐링(Annealing)하여 노출된 텅스텐플러그(45)를 티타늄텅스텐층(60)으로 형성하고, 다른 부위의 티타늄층(50)을 티타늄질화층(55)으로 형성하도록 한다.As shown in FIG. 3H, the resultant annealing is performed to form the exposed tungsten plug 45 as the titanium tungsten layer 60, and the titanium layer 50 at another portion to the titanium nitride layer 55. To form.
상기 티타늄텅스텐층(60)을 형성하기 위한 어닐링공정은, 급속열처리법으로, 400 ∼ 450℃의 온도범위에서 진행하는 것이 바람직 하다.The annealing process for forming the titanium tungsten layer 60, it is preferable to proceed in a temperature range of 400 ~ 450 ℃ by a rapid heat treatment method.
도 3i에 도시된 바와 같이, 상기 티타늄질화층(55)을 식각으로 제거하여 티타늄텅스텐층(60)을 노출시키도록 한다.As shown in FIG. 3I, the titanium nitride layer 55 is etched to expose the titanium tungsten layer 60.
상기 티타늄질화층(55)을 제거할 때, 10 ∼ 20중량%의 NH4OH 수용액을 사용하도록 한다.When removing the titanium nitride layer 55, 10 to 20% by weight of NH 4 OH aqueous solution is to be used.
이와 같이, 상기 텅스텐플러그(45) 상에 형성되는 티타늄텅스텐층(60)은, 0.06 ∼ 0.1㎛ 정도인 물리적인 면적을 가지며, 접시모양으로 형성되어진다.As described above, the titanium tungsten layer 60 formed on the tungsten plug 45 has a physical area of about 0.06 to 0.1 µm and is formed in a dish shape.
상기한 바와 같이, 본 발명에 따른 반도체장치의 텅스텐플러그 형성방법을 이용하게 되면, 반도체기판 상에 메탈1을 형성하고, 층간절연막에 금속층을 매립하여 텅스텐프러그를 형성한 후, 층간절연막을 일정 두께로 식각하여 금속플러그를 노출시킨 후 티타늄층을 적층하여 어닐링공정으로 금속플러그 상에 넓은 면적을 갖는 티타늄텅스텐층을 형성하므로 후속 공정에서 텅스텐플러그 상에 적층되는 메탈2층의 오버랩 마아진을 충분하게 확보하여 저항의 증가를 방지하도록 하는 매우 유용하고 효과적인 발명이다.As described above, when the tungsten plug forming method of the semiconductor device according to the present invention is used, a metal 1 is formed on a semiconductor substrate, a tungsten plug is formed by embedding a metal layer in the interlayer insulating film, and then the interlayer insulating film is formed to a predetermined thickness. After etching the metal plug to expose the metal plug, the titanium layer is laminated to form a titanium tungsten layer having a large area on the metal plug by the annealing process, thereby sufficiently securing the overlap margin of the metal 2 layer laminated on the tungsten plug in a subsequent process. It is a very useful and effective invention to prevent the increase of resistance.
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