KR20010028532A - Liquid crystal display device - Google Patents

Abstract

PURPOSE: A liquid crystal display device is provided to be capable of reducing a resistance at an electrode path, through which a signal is transferred, without dropping of an aperture rate while using the same electrode material as a conventional art. CONSTITUTION: A lower film is formed on a gate insulating layer so as to have a prominence and depression part. An electrode has a prominence and depression part by uniformly forming the electrode along to a surface of the lower film, on which the prominence and depression part is formed, and an external signal is transferred through the electrode. The electrode is used as a data line(76), and the lower film is an active layer(74) made of a semiconductor material. A data pad or a drain electrode is contact with a surface of the data line and the external signal is transferred through the data pad. The data pad is a transparent electrode.

Description

Liquid Crystal Display Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device in which resistance in an electrode path through which a signal is transmitted is reduced without loss of aperture ratio while using the same electrode material as in the prior art.

In general, a liquid crystal display (LCD) displays an image corresponding to a data signal on a panel by adjusting light transmittance of liquid crystal cells arranged in a matrix form on a liquid crystal panel as a video data signal supplied thereto. . To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells forming pixel units are arranged in an active matrix form, and a driver integrated circuit (hereinafter, referred to as "IC") for driving the liquid crystal cells. In the liquid crystal panel, the lower substrate is disposed in a direction in which data lines for transmitting data signals from the data driver IC to the liquid crystal cells and gate lines for transmitting scan signals from the gate driver IC to the liquid crystal cells are perpendicular to each other. Is formed on the phase. Liquid crystal cells are formed at each intersection of these data lines and gate lines. Each of the liquid crystal cells is provided with a pixel electrode and a common electrode for applying an electric field to the liquid crystal layer. The pixel electrode is formed for each liquid crystal cell on the lower substrate, while the common electrode is integrally formed on the entire surface of the upper substrate. In addition, each liquid crystal cell is formed of a thin film transistor (hereinafter referred to as "TFT") used as a switch element. In liquid crystal cells in which a scan signal is supplied to the gate electrode of the TFT through the gate line, a conductive channel is formed between the source and drain electrodes of the TFT, and at this time, the data voltage supplied to the source electrode of the TFT via the data line is TFT. The light transmittance of the liquid crystal layer is adjusted by being supplied to the pixel electrode via the drain electrode of the liquid crystal layer. The gate driver IC sequentially supplies the scan signal to the plurality of gate lines so that the data signal supplied from the data driver IC is sequentially supplied to the liquid crystal cells in the liquid crystal panel by one line.

1 is a diagram illustrating a planar structure of a general liquid crystal cell in a liquid crystal display device. Referring to FIG. 1, the liquid crystal cell formed at the intersection of the data line 2 and the gate line 4 is the TFT 6 and the pixel electrode 14 connected to the drain electrode 12 of the TFT 6. It is provided. The source electrode 8 of the TFT 6 is connected to the data line 2, and the gate electrode 10 is connected to the gate line 4. The drain electrode 12 of the TFT 6 is connected to the pixel electrode 14 through a drain contact hole 16. Further, the TFT 6 is an active layer (not shown) for forming a conductive channel between the source electrode 8 and the drain electrode 12 by a scan signal supplied to the gate electrode 10 through the gate line 4. ) Is further provided. The TFT 6 is supplied to the source electrode 8 through the data line 2 by forming a conductive channel between the source electrode 8 and the drain electrode 12 in response to the scan signal from the gate line 4. The data signal is transmitted to the drain electrode 12. The pixel electrode 14 connected to the drain electrode 12 through the drain contact hole 16 is widely formed in a region where liquid crystal is located for each liquid crystal cell, and is transparently formed of an indium tin oxide (ITO) material having high light transmittance. do. The pixel electrode 14 generates an electric field in the liquid crystal layer together with a common transparent electrode (not shown) formed on the upper substrate by the data voltage supplied via the drain electrode 12. At this time, the liquid crystal of the liquid crystal layer is rotated by the dielectric anisotropy, and transmits the light supplied through the pixel electrode 14 from the back light toward the upper substrate. At this time, the amount of transmitted light in the liquid crystal layer is controlled by the data voltage.

Meanwhile, the storage electrode 20 connected to the pixel electrode 14 through the through-hole 22 forms a storage capacitor 18 together with the gate line 4 of the upper scan line. do. The storage capacitor 18 charges the scan voltage during the period in which the scan signal is applied to the gate line 4 of the upper scan line, and then charges during the period in which the next scan line is driven to supply the data voltage to the pixel electrode 14. The discharged voltage is discharged to prevent the voltage variation of the pixel electrode 14.

The cross-sectional structure of the liquid crystal panel having such a planar structure is as shown in FIGS. 2 to 5. FIG. 2 is a cross-sectional view showing a vertical cross-sectional structure taken along the line AA ′ shown in FIG. 1, showing the cross-sectional structure of the TFT 6 forming portion. Referring to FIG. 2, first, a metal material (metal such as Mo, Al, Cr, etc.) is sputter deposited on the lower substrate 1, and then patterned by photo-etching to form a gate electrode 10. ) Is formed. An insulating material such as SiNx is deposited on the lower substrate 1 on which the gate electrode 10 is formed to form the gate insulating layer 30. On the gate insulating layer 30, a semiconductor layer 32 made of amorphous silicon (Si) and an ohmic contact layer 34 made of n + amorphous silicon doped with phosphorus (P) are successively deposited. The semiconductor layer 32 and the ohmic contact layer 34 form an active layer 36. Metal materials such as Cr and Mo are deposited on the ohmic contact layer 34 and the gate insulating layer 30 and then patterned. The patterned metal material layer becomes the source electrode 8 and the drain electrode 12 of the TFT 6. The exposed ohmic contact layer 34 between the source electrode 8 and the drain electrode 12 is removed by an etching operation. Then, on the gate insulating layer 30 including the exposed semiconductor layer 32 and the source and drain electrodes 8 and 12, a SiNx passivation layer 38 is formed by a chemical vapor deposition (CVD) method. Is deposited on the front. A portion of the protective film 38 on the drain electrode 12 of the TFT 6 is removed by an etching operation to form a drain contact hole 16. Subsequently, the ITO material is deposited on the protective film 38 by sputtering and then patterned, thereby forming the pixel electrode 14. The pixel electrode 14 is connected to the drain electrode 12 through the drain contact hole 16. In the conventional liquid crystal display, a portion where the pixel electrode 14 and the drain electrode 12 contact each other is flat in a uniform flat shape as shown in FIG. 2.

3 is a cross-sectional view showing a vertical cross-sectional structure cut along the line B-B 'shown in FIG. 1, showing the cross-sectional structure of the data line 2 portion. Referring to FIG. 3, an active layer 36 is formed on the gate insulating layer 30, and a data line 2 is formed thereon. The active layer 36 is formed along the data line 2 to the pad portion, which is formed together when the active layer 36 is formed in the TFT 6 portion. The data line 2 is also formed together when the source and drain electrodes 8, 12 are formed in the TFT 6 portion. The passivation layer 38 is formed on the gate insulating layer 30 on which the data line 2 is formed. In the conventional liquid crystal display, the active layer 36 under the data line 2 is uniformly formed in a planar shape, and the portion where the data line 2 and the active layer 36 contact each other is flat.

4A and 4B are diagrams illustrating a planar structure and a cross-sectional structure of the data pad unit, respectively. 4A and 4B, a portion of the passivation layer 38 formed on the data pad 40 is removed to form a pad contact hole 44. The pad contact hole 44 is formed together when the drain contact hole 16 is formed on the drain electrode 12 of the TFT 6. The data pad 40 connected to the data line 2 is connected to the transparent electrode 42 through the pad contact hole 44. The transparent electrode 42 is connected to a tape carrier package (hereinafter referred to as "TCP") in which a data driver IC is mounted. The transparent electrode 42 serves to protect the data pad 40, which is a metal electrode, and to prevent oxidation of the data pad 40 when the TCP bonding process is repeated. The data voltage supplied from the data driver IC is supplied to the data pad 40 through the TCP and the transparent electrode 42. The data voltage supplied to the data pad 40 is again supplied to each liquid crystal cell through the data line 2. In the conventional liquid crystal display, a portion where the transparent electrode 42 is in contact with the data pad 40 is flat in a uniform flat shape as shown in FIG. 4B.

FIG. 5 is a cross-sectional view illustrating a vertical cross-sectional structure taken along the line CC ′ of FIG. 1 and illustrating a cross-sectional structure of the storage capacitor 18 forming portion. Referring to FIG. 5, a gate line 4 is first formed on a lower substrate 1, and a gate insulating layer 30 is formed thereon. The gate line 4 is formed together when the gate electrode 10 is formed in the TFT 6 portion. The storage electrode 20 is formed on the gate insulating layer 30. The storage electrode 20 is formed together when the source and drain electrodes 8, 12 are formed in the TFT 6 portion. The passivation layer 38 is formed on the gate insulating layer 30 on which the storage electrode 20 is formed. A portion of the protective film 38 formed on the storage electrode 20 is removed by the etching operation to form the through hole 22. The through hole 22 is formed together when the drain contact hole 16 is formed in the TFT 6 portion. Subsequently, the pixel electrode 14 is formed on the protective film 38. The pixel electrode 14 is connected to the storage electrode 20 through the through hole 22. In the conventional liquid crystal display, a portion where the pixel electrode 14 and the storage electrode 20 contact each other is flat in a uniform flat shape as shown in FIG. 5.

In the liquid crystal display device, the resistance in the transmission path through which the data signal is transmitted should be minimized so that the signal delay of the data voltage supplied from the data driver IC to charge each liquid crystal cell is minimized. The resistance present along the transmission path through which the data signal is transmitted has been a factor of lowering the luminance of the liquid crystal panel by delaying the data signal supplied to each liquid crystal cell and reducing the voltage charge amount of the liquid crystal cell. In addition, the signal delay phenomenon of the data voltage generated by the line resistance of the data line 2 causes a difference in the voltage charge amount between the liquid crystal cell connected to the upper end of the data line 2 and the liquid crystal cell connected to the lower end. This causes a difference in luminance between the upper end and the lower end of the liquid crystal panel. Conventionally, a method of increasing the output voltage of the data driver IC by a predetermined level or more and supplying it to the data line 2 so as to prevent the problems caused by the signal delay of the data voltage is used. However, when the liquid crystal panel is formed into a large screen, the signal delay of the data voltage becomes more severe due to the longer length of the data line 2. Accordingly, in order to solve the problem of deterioration of luminance, a higher driving voltage outside the output voltage range that the data driver IC can compensate for is required. In order to overcome this limitation, a method for reducing the line resistance of the data line 2 is required. In order to reduce the resistance of the data line 2, the width or thickness of the data line 2 may be increased to increase the cross-sectional area of the line, but this method is not suitable for applying to the conventional liquid crystal panel. The reason for this is that when the width of the data line 2 is increased, the aperture ratio of the liquid crystal cell is reduced, and thus the light transmittance is lowered, thereby decreasing the luminance of the liquid crystal panel. In addition, due to various problems in the actual manufacturing process, there is a limit to increasing the thickness of the data line (2), there is also a limit to reducing the resistance value through the material selection.

On the other hand, in addition to the data line 2, a portion where the resistance is to be reduced includes a pad contact portion in which the data pad 40 and the transparent electrode 42 contact each other in the data pad portion, a drain electrode 12 and a pixel in the TFT 6 portion. The drain contact portion contacting the electrode 14 and the through hole portion contacting the storage electrode 20 and the pixel electrode 14 in the storage capacitor 18 may be provided. In these areas too, the contact resistance should be minimized to minimize the signal delay of the transmitted signal. However, as described above, in the conventional liquid crystal panel, portions where the two electrodes contact each other in the pad contact portion, the drain contact portion, and the through hole portion are flat. This limits the contact area of the two electrodes under a limited width or area, limiting the reduction in contact resistance beyond any limit.

Accordingly, an object of the present invention is to provide a liquid crystal display device in which resistance in an electrode path through which a signal is transmitted is reduced without loss of aperture ratio while using the same electrode material as in the prior art.

1 is a view showing a planar structure of a general liquid crystal cell in a liquid crystal display device.

2 is a view showing a vertical cross-sectional structure cut along the line AA 'shown in FIG.

3 is a view showing a vertical cross-sectional structure cut along the line B-B 'shown in FIG.

4A and 4B show a planar structure and a cross-sectional structure of the data pad unit, respectively.

5 is a view showing a vertical cross-sectional structure cut along the line CC 'shown in FIG.

6A and 6B illustrate a planar structure and a cross-sectional structure of a data line unit in a liquid crystal display according to an exemplary embodiment of the present invention.

7A and 7B illustrate a planar structure and a cross-sectional structure of a contact portion in which two electrodes contact each other in a liquid crystal display according to an exemplary embodiment of the present invention.

<Description of the code | symbol about the principal part of drawing>

1,70: Lower substrate 2,76: Data line

4: gate line 6: TFT

8 source electrode 10 gate electrode

12,82 drain electrode 14,88 pixel electrode

16: drain contact hole 18: storage capacitor

20,84: storage electrode 22: through hole

30,72: gate insulating layer 32: semiconductor layer

34: ohmic contact layer 36,74: active layer

38,78: protective film 40,80: data pad

42,86 transparent electrode 44 pad contact hole

In order to achieve the above object, the liquid crystal display device of the present invention is formed to have a uniform thickness along the surface of the lower layer formed by patterning to have the uneven portion on the gate insulating layer, and the uneven portion is formed to have an uneven portion and an external signal Has an electrode to be transmitted.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6A to 7B.

6A and 6B illustrate a planar structure and a cross-sectional structure of a data line unit of a liquid crystal display according to an exemplary embodiment of the present invention, respectively. 6A and 6B, the liquid crystal display according to the exemplary embodiment of the present invention is the active layer 74 formed by patterning the uneven parts on the gate insulating layer 72, and the gate insulation on which the active layer 74 is formed. And a data line 76 formed on the layer 72 to have a uniform thickness and having irregularities along the surface of the active layer 74. First, an insulating material such as SiNx is deposited on the lower substrate 70 to form a gate insulating layer 72. After the gate insulating layer 72 is formed on the lower substrate 70, the active layer 74 is continuously deposited. The thickness x of the active layer 74 is formed to be about 2000 GPa. The active layer 74 is composed of a semiconductor layer made of amorphous silicon (Amorphous-Si) and an ohmic contact layer made of n + amorphous silicon doped with phosphorus (P). After the active layer 74 is formed, the center portion is removed so that the active layer 74 has an uneven portion as shown in FIG. 6B through an etching operation using a mask pattern. The operation of forming the concave-convex portion can be easily performed by only changing the shape of the mask pattern during the patterning operation of the active layer 74 without the need to add the number of processes or the number of masks as compared with the conventional manufacturing process. The width of each active layer 74 patterned and formed under the data line 76 is about 2.5 탆, and the width of the uneven portion between the two active layers 74 is about 1 탆. Next, the data line 76 is formed on the active layer 74 having the uneven portion formed with a uniform thickness along the surfaces of the active layer 74 and the uneven portion. Accordingly, the data line 76 has irregularities along the surface of the active layer 74. The thickness y of the data line 76 is formed to be about 1500 mV as in the prior art. In addition, the width of the data line 76 is also formed to be about 8 占 퐉 as in the prior art so that the aperture ratio is not reduced. Next, the SiNx passivation layer 78 is entirely deposited on the gate insulating layer 72 on which the data line 76 is formed by using a chemical vapor deposition (CVD) method.

In the liquid crystal display according to the present invention having the data line cross-sectional structure as described above, the volume of the data line 76 is increased in the same state as in the conventional case, so that the line resistance is reduced. Referring to FIG. 6B, in the liquid crystal display according to the present invention, the cross-sectional area of the data line 76 is increased by 2 A compared with the conventional case shown in FIG. 3. In FIG. 6B, the area A is an increased cross-sectional area compared to the conventional structure, and the height of the area A corresponds to the height of the active layer 74. With the addition of the A region, in practice, the width of the data line 76 has the same effect as the length corresponding to twice the height of the active layer 74. Accordingly, the volume increase rate of the data line 76 is calculated as (2 × active layer thickness) / (width of the data line) = (2 × 2000 μs) / (8 μm), so that the effect of about 5% cross-sectional area or volume increase is obtained. Will be obtained. Thus, by increasing the volume of the data line 76 without increasing the width of the data line 76, it is possible to effectively reduce the line resistance.

Considering the level of patterning technology with current resolutions on the order of 3-4 μm, two active layer 74 patterns are possible within 8 μm wide data line 76. However, considering the improvement in resolution with the development of patterning technology, three or four active layer patterns may be formed under the data line 76. Accordingly, if more uneven portions are formed in the active layer 74, the line resistance can be further reduced. When three active layer patterns are formed to form two uneven portions, the line resistance reduction rate of the data line 76 is about 10%, and when four active layer patterns are formed, the line resistance reduction effect is about 15%. .

7A and 7B illustrate a planar structure and a cross-sectional structure of a contact portion in which two electrodes contact each other in the liquid crystal display according to the exemplary embodiment of the present invention. In FIG. 4A, the pad contact hole 44 portion in contact with the data pad 40 and the transparent electrode 42, and the drain contact hole 16 portion in contact with the drain electrode 12 and the pixel electrode 14 in FIG. 1. The through hole 22 and the like in which the storage electrode 20 and the pixel electrode 14 contact each other correspond to this portion. First, a structure of a portion where a data pad contacts a transparent electrode in a pad contact hole portion will be described with reference to FIGS. 7A and 7B. In the liquid crystal display according to the exemplary embodiment of the present invention, the active layer 74 formed by patterning the uneven portions on the gate insulating layer 72 in the data pad part and on the gate insulating layer 72 in which the active layer 74 is formed. And a data pad 80 formed to have a uniform thickness on the active layer 74 to have an uneven portion along the surface of the active layer 74, and a transparent electrode 86 contacting the data pad 80. The active layer 74 of the data pad part is formed together when the active layer 74 is patterned and formed below the data line 76. Also in this case, part of the active layer 74 is removed so that the active layer 74 has an uneven portion through an etching operation using a mask pattern. The operation of forming the concave-convex portion can be easily performed by only changing the shape of the mask pattern during the patterning operation of the active layer 74 without the need to add the number of processes or the number of masks as compared with the conventional manufacturing process. Next, the data pads 80 are formed to have a uniform thickness along the surfaces of the active layer 74 and the uneven portions on the active layer 74 having the uneven portions. Accordingly, the data pad 80 has irregularities along the surface of the active layer 74. In this way, the transparent electrode 86 is formed on the surface of the data pad 80 having the uneven portion. The transparent electrode 86 is connected to a tape carrier package (hereinafter referred to as "TCP") in which a data driver IC is mounted.

In the liquid crystal display according to the present invention having the data pad cross-sectional structure as described above, the area of the contact portion between the data pad 80 and the transparent electrode 86 increases compared to the conventional structure, thereby reducing the contact resistance. That is, since the uneven portion is formed, the area of the portion where the actual data pad 80 and the transparent electrode 86 are in contact with each other has the same line width as the conventional case, thereby reducing the contact resistance. Accordingly, when the data voltage is supplied from the data driver IC to the data line 76 through the data pad 80, the amount of signal delay in the data pad 80 portion is reduced. The reduction rate of the contact resistance increases as more patterns are formed in the active layer 74 formed under the data pad 80 at the contact portion where the data pad 80 and the transparent electrode 86 contact each other.

In the liquid crystal display according to the exemplary embodiment of the present invention, the structure of the drain contact hole portion where the drain electrode and the pixel electrode are in contact is shown in FIGS. 7A and 7B. First, the active layer 74 is formed on the gate insulating layer 72. At this time, the active layer 74 is patterned to have the uneven portion. Also in this case, the mask used when forming the active layer 74 under the data pad 80 or the data line 76 is used as it is. The operation of forming the uneven portion can be easily performed by only changing the shape of the mask pattern in the patterning operation of the active layer 74 without the need to add the number of processes or the number of masks as compared with the conventional manufacturing process. Then, the drain electrode 82 is formed to a uniform thickness along the surfaces of the active layer 74 and the uneven portion on the active layer 74 where the uneven portion is formed. As a result, the drain electrode 82 has irregularities along the surface of the active layer 74. And the pixel electrode 88 is formed on the surface of the drain electrode 82 in which the uneven part was formed.

As the concave and convex portions are formed in the drain electrode hole in the drain contact hole formed as described above, the area of the portion where the actual drain electrode 82 and the pixel electrode 88 contact is wider while having the same line width as the conventional structure. All. As a result, the contact resistance between the drain electrode 82 and the pixel electrode 88 is reduced. Due to the decrease in the contact resistance, the signal delay amount of the data voltage supplied to the pixel electrode 88 through the drain electrode 82 and charged in the liquid crystal cell is reduced.

In addition, the portion where the storage electrode is in contact with the pixel electrode in the through hole has the structures of FIGS. 7A and 7B, the active layer 74 is formed on the gate insulating layer 72 to be patterned to have an uneven portion. Then, the storage electrode 84 is formed to have a uniform thickness along the surfaces of the active layer 74 and the uneven portion on the active layer 74 having the uneven portion. The storage electrode 84 has irregularities along the surface of the active layer 74. The pixel electrode 88 is formed on the surface of the storage electrode 84 where the uneven portion is formed to be in contact with each other. The operation of forming the active layer 74 and the concave-convex portion under the storage electrode 84 only changes the shape of the mask pattern during the patterning operation of the active layer 74 without the need to add a process number or a mask number as compared with a conventional manufacturing process. It can be easily carried out by. Instead of forming the active layer 74, an additional gate insulating layer may be patterned on the gate insulating layer 72 so that the storage electrode 84 has an uneven portion. However, in this case, a mask pattern and a process for patterning additional gate insulating layers are added.

Since the uneven portion is formed in the storage electrode 84 in the through hole portion, the area of the portion where the actual storage electrode 84 and the pixel electrode 88 contact is wider while having the same line width as the conventional structure. As a result, the contact resistance between the storage electrode 84 and the pixel electrode 88 is reduced. The reduction in contact resistance results in higher voltage charging efficiency in the storage capacitor than in the prior art.

As described above, in the liquid crystal display according to the present invention, the uneven portion is formed in the active layer formed under the data line. As a result, the thickness and width of the data line formed on the active layer can be made the same as in the conventional case, but the volume of the data line can be increased as compared with the conventional case. Accordingly, there is an advantage that the line resistance of the data line can be reduced without reducing the aperture ratio while using the same electrode material as in the prior art.

In addition, the contact area between the two electrodes may be increased by forming an uneven portion by patterning an active layer or a gate insulating layer formed under the electrode, such as a contact hole and a through hole. Accordingly, there is an advantage that the contact resistance at the contact portion where the two electrodes are in contact with each other can be reduced.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (8)

In a liquid crystal display device in which a signal supplied from the outside is transmitted to liquid crystal cells through an electrode path, A lower film formed by patterning the concave-convex portion on the gate insulating layer; And having an uneven portion along the surface of the lower layer on which the uneven portion is formed, the electrode having an uneven portion and transmitting the external signal. The method of claim 1, And the electrode is a data line, and the lower layer is an active layer made of a semiconductor material. The method of claim 1, And a second electrode in contact with the surface of the electrode to transmit the external signal. The method of claim 3, wherein Wherein the electrode is a data pad, the lower layer is an active layer of semiconductor material, and the second electrode is a transparent electrode. The method of claim 3, wherein Wherein the electrode is a drain electrode, the lower layer is an active layer made of a semiconductor material, and the second electrode is a pixel electrode. The method of claim 3, wherein Wherein the electrode is a storage electrode, and the second electrode is a pixel electrode. The method of claim 6, And the lower layer is an active layer made of a semiconductor material. The method of claim 6, And the lower layer is a second gate insulating layer.