KR20010028434A - Stacked bottom lead package and manufacturing method thereof - Google Patents

Stacked bottom lead package and manufacturing method thereof Download PDF

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Publication number
KR20010028434A
KR20010028434A KR1019990040685A KR19990040685A KR20010028434A KR 20010028434 A KR20010028434 A KR 20010028434A KR 1019990040685 A KR1019990040685 A KR 1019990040685A KR 19990040685 A KR19990040685 A KR 19990040685A KR 20010028434 A KR20010028434 A KR 20010028434A
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KR
South Korea
Prior art keywords
package
lead
exposed
chip
piece
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KR1019990040685A
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Korean (ko)
Inventor
송치중
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김영환
현대반도체 주식회사
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Priority to KR1019990040685A priority Critical patent/KR20010028434A/en
Publication of KR20010028434A publication Critical patent/KR20010028434A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers

Abstract

PURPOSE: A method for manufacturing a stacked bottom lead package is provided to simply separate upper and lower single unit packages from thermal tape in a repair process, by adhering the lower single unit package to the upper single unit package while intervening the thermal tape. CONSTITUTION: A semiconductor chip(21) is connected to a lead(22) with a wire and an exposed terminal part(22a) where an end part of a lead is exposed is formed in a lower single unit package(20) while a molding part is formed on the lower single unit package so that an exposed surface(21a) is formed at a side of the chip. Thermal tape(40) is adhered to the exposed surface of the lower single unit package. A semiconductor chip(31) is connected to a lead(32) with a wire and an end part of the lead is protruded and bent to form a protruded terminal part(32a) in an upper single unit package while a molding part is formed on the lower single unit package so that an exposed surface(31a) is formed at a side of the chip. The upper single unit package is adhered to the upper surface of the thermal tape.

Description

적층형 버틈 리드 패키지 및 그 제조방법{STACKED BOTTOM LEAD PACKAGE AND MANUFACTURING METHOD THEREOF}Stacked Bud Lead Package and Manufacturing Method thereof {STACKED BOTTOM LEAD PACKAGE AND MANUFACTURING METHOD THEREOF}

본 발명은 적층형 버틈 리드 패키지 및 그 제조방법에 관한 것으로, 특히 단품상태의 상,하부 단품 패키지를 양면 테이프를 이용하여 부착하는 것으로 간단히 적층할 수 있도록 하는데 적합한 적층형 버틈 리드 패키지 및 그 제조방법에 관한 것이다.The present invention relates to a laminated bump lid package and a method of manufacturing the same, and more particularly, to a laminated bump lid package suitable for enabling easy lamination by attaching a single-piece upper and lower one-piece package using double-sided tape. will be.

칩 사이즈 패키지의 일종인 버틈 리드 패키지의 적층된 일예가 도 1에 도시되어 있는 바, 이를 간단히 설명하면 다음과 같다.An example of a stacked stack lead package, which is a type of chip size package, is illustrated in FIG. 1.

도시된 바와 같이, 종래의 적층형 버틈 리드 패키지는 칩(1)과 와이어(2)로 연결된 리드(3)의 아웃단자부(3a)가 몰딩부(4)의 외측으로 돌출되도록 형성되어 있고, 그와 같이 돌출된 아웃단자부(3a)가 피시비(5)의 상면에 접합되도록 실장되어 있는 하부 단품 패키지(6)와, 그 하부 단품 패키지(6)의 상측에 배치되어 칩(11)과 와이어(12)로 연결된 리드(13)의 아웃단자부(13a)가 몰딩부(14)의 외측으로 노출되어 상기 하부 단품 패키지(6)의 아웃단자부(3a)에 솔더(15)로 접합되도록 적층구성되어 있는 상부 단품 패키지(16)으로 구성되어 있다.As shown, the conventional stacked recess lid package is formed such that the out terminal portion 3a of the lead 3 connected with the chip 1 and the wire 2 protrudes out of the molding portion 4. The lower one-piece package 6 is mounted to be joined to the upper surface of the PCB 5 and the upper one of the lower one-piece package 6 and the chip 11 and the wire 12 are protruded. The upper end part 13a of the lead 13 connected to the upper part is laminated so as to be exposed to the outside of the molding part 14 and bonded to the out terminal part 3a of the lower unit package 6 with the solder 15. The package 16 is comprised.

상기와 같이 구성되어 있는 종래 적층형 버틈 리드 패키지(17)는 하부 단품 패키지(6)와 상부 단품 패키지(16)을 각각 제작하여 하부 단품 패키지(6)의 상부에 상부 단품 패키지(16)를 솔더링으로 접합하는 순서로 제조된다.The conventional laminated bump lid package 17 having the above structure is manufactured by manufacturing the lower single package 6 and the upper single package 16, respectively, and soldering the upper single package 16 to the upper portion of the lower single package 6. It is manufactured in the order of bonding.

즉, 칩(1)의 리드(3)들을 부착하고, 그 리드(3)들과 칩(1)을 와이어(2)로 연결하며, 칩(1), 와이어(2), 리드(3)의 일정부분을 감싸도록 몰딩한 다음, 돌출된 리드(3)를 L형 으로 절곡하여 하부 단품 패키지(6)를 제작하고, 별도의 공정으로 제작된 상부 단품 패키지(16)를 하부 단품 패키지(6)의 상측에 위치시킨 상태에서 하부 단품 패키지(6)의 리드(3)들과 상부 단품 패키지(16)의 리드(13)들을 각각 솔더(15)로 솔더링 접합하여 적층형 버틈 리드 패키지(17)를 완성하였다.That is, the leads 3 of the chip 1 are attached, and the leads 3 and the chip 1 are connected with the wire 2, and the chips 1, the wire 2, and the leads 3 of the chip 3 are attached. After molding to cover a portion, the protruded lead 3 is bent into L shape to manufacture the lower one-piece package 6, and the upper one-piece package 16 manufactured by a separate process is the lower one-piece package 6. Solder-bonded the leads 3 of the lower one-piece package 6 and the leads 13 of the upper one-piece package 16 with the solder 15, respectively, in the state of being positioned on the upper side of the lower part package 6 to complete the stacked gap lead package 17. It was.

그러나, 상기와 같이 구성되는 종래의 적층형 버틈 리드 패키지(17)는 완성한 상태에서 전기적인 특성검사를 실시하여 이상이 발생되어 수리를 하는 경우에는 솔더(15)로 접합된 하부 단품 패키지(6)의 리드(3)와 상부 단품 패키지(16)의 리드(13)를 제거하여야 하기 때문에 수리가 번거롭고, 솔더(15)를 용융시키기 위하여 열을 가하여야 하기 때문에 열에 의한 패키지의 신뢰성 저하를 초래하는 문제점이 있었다.However, the conventional laminated bump lid package 17 constructed as described above is subjected to electrical characteristic inspection in a completed state, and when an abnormality is generated and repaired, the lower unit package 6 joined by solder 15 is repaired. Since the lead 3 and the lead 13 of the upper unit package 16 need to be removed, the repair is cumbersome, and since heat must be applied to melt the solder 15, the reliability of the package due to heat is reduced. there was.

상기와 같은 문제점을 감안하여 안출한 본 발명의 목적은 적층되어 있는 단품 패키지들의 해체가 용이하고, 열을 가하지 않고 간단히 해체할 수 있는 적층형 버틈 리드 패키지 및 그 제조방법을 제공함에 있다.SUMMARY OF THE INVENTION An object of the present invention devised in view of the above problems is to provide a stacked-type buried lid package and a method of manufacturing the same, which can be easily dismantled and separately dismantled.

도 1은 종래 적층형 버틈 리드 패키지의 구성을 보인 종단면도.1 is a longitudinal cross-sectional view showing the configuration of a conventional stacked gap lead package.

도 2는 종래 상부 단품 패키지의 구성을 보인 종단면도.Figure 2 is a longitudinal cross-sectional view showing the configuration of a conventional upper single-piece package.

도 3은 종래 하부 단품 패키지의 구성을 보인 종단면도.Figure 3 is a longitudinal cross-sectional view showing the configuration of a conventional lower single-piece package.

도 4는 종래 적층형 버틈 리드 패키지의 제조방법을 설명하기 위한 단면도.Figure 4 is a cross-sectional view for explaining a method of manufacturing a conventional stacked gap lead package.

도 5는 본 발명 적층형 버틈 리드 패키지의 구성을 보인 종단면도.Figure 5 is a longitudinal cross-sectional view showing the configuration of the present invention laminated bump lead package.

도 6은 본 발명 적층형 버틈 리드 패키지의 제조방법을 설명하기 위한 단면도.Figure 6 is a cross-sectional view for explaining a method of manufacturing the present invention laminated bump lid package.

도 7은 본 발명 적층형 버틈 리드 패키지가 실장된 상태를 보인 종단면도.Figure 7 is a longitudinal cross-sectional view showing a state in which the present invention laminated bump lead package is mounted.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

20 : 하부 단품 패키지 21,31 : 칩20: lower unit package 21, 31: chip

21a,31a : 노출면 22,32 : 리드21a, 31a: exposed surface 22, 32: lead

22a : 노출단자부 23,33 : 와이어22a: exposed terminal portion 23,33: wire

24,34 : 몰딩부 32a : 돌출단자부24, 34: molding portion 32a: protruding terminal portion

40 : 써멀 테이프40: thermal tape

상기와 같은 본 발명의 목적을 달성하기 위하여 반도체 칩과 리드들이 와이어로 각각 연결되고, 그 리드들의 노출단자부가 노출되도록 몰딩부가 형성되는 하부 단품 패키지와; 그 하부 단품 패키지의 상측에 배치되며 반도체 칩과 리드들이 와이어로 각각 연결되고, 상기 리드의 일정부분이 돌출되어 돌출단자부가 형성되도록 몰딩부가 형성됨과 아울러 그 돌출단자부가 노출단자부에 근접되도록 절곡되는 상부 단품 패키지와; 상기 하부 단품 패키지와 상부 단품 패키지의 사이에 개재되어 상,하부 단품 패키지를 접합시키기 위한 써멀 테이프를 구비하여서 구성되는 것을 특징으로 하는 적층형 버틈 리드 패키지가 제공된다.In order to achieve the above object of the present invention, the semiconductor chip and the leads are connected to each of the wire, the lower unit package is formed with a molding portion to expose the exposed terminals of the leads; The upper part is disposed above the lower unit package and the semiconductor chip and the leads are respectively connected by wires, and a molding part is formed to protrude a part of the lead to form a protruding terminal part, and an upper part of which the protruding terminal part is bent to approach the exposed terminal part. A la carte package; There is provided a stacked-type bump lead package, comprising a thermal tape interposed between the lower one piece package and the upper one piece package to bond the upper and lower one piece packages.

또한, 반도체 칩과 리드가 와이어로 연결되고, 리드의 단부가 노출되는 노출단부가 형성됨과 아울러 칩의 일측에 노출면이 형성되도록 몰딩부가 형성되어 있는 하부 단품 패키지의 노출면에 써멀 테이프를 부착하는 단계와;In addition, the semiconductor chip and the lead is connected by a wire, the exposed end portion is formed to expose the end of the lead, and the thermal tape is attached to the exposed surface of the lower single-piece package in which the molding part is formed to form an exposed surface on one side of the chip. Steps;

반도체 칩과 리드가 와이어로 연결되고, 리드의 단부가 돌출되어 절곡되도록 돌출단부가 형성됨과 아울러 칩의 일측에 노출면이 형성되도록 몰딩부가 형성되어 있는 상부 단품 패키지의 노출면이 상기 써멀 테이프의 상면에 부착되도록 상부 단품 패키지를 부착하는 단계의 순서로 제작되는 것을 특징으로 하는 적층형 버틈 리드 패키지의 제조방법이 제공된다.The exposed surface of the upper single-piece package in which the semiconductor chip and the lead are connected by a wire, a protruding end portion is formed to protrude and bend the end of the lead, and a molding part is formed to form an exposed surface on one side of the chip is the upper surface of the thermal tape. Provided is a method of manufacturing a stacked buckled lead package, characterized in that it is manufactured in the order of attaching the upper unit package to be attached to.

이하, 상기와 같이 구성되는 본 발명 적층형 버틈 리드 패키지 및 그 제조방법을 첨부된 도면의 실시예를 참고하여 보다 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in more detail with reference to an embodiment of the present invention, the laminated bump lid package and the manufacturing method of the accompanying drawings configured as described above.

도 5는 본 발명 적층형 버틈 리드 패키지의 구성을 보인 종단면도로서, 도시된 바와 같이, 반도체 칩(21)과 리드(22)가 와이어(23)로 연결되어 있고, 리드(22)의 단부가 노출단자부(22a)가 형성됨과 아울러 상기 칩(21)의 일측이 노출면(21a)이 형성되도록 몰딩부(24)가 형성되어 있는 하부 단품 패키지(20)와, 그 하부 단품 패키지(20)의 상측에 배치되어 반도체 칩(31)과 리드(32)가 와이어(33)로 연결되어 있고, 리드(32)의 단부가 돌츨되어 절곡되도록 돌출단부(32a)가 형성됨과 아울러 상기 칩(31)의 일측이 노출면(31a)이 형성되도록 몰딩부(34)가 형성되어 있는 상부 단품 패키지(30) 및 그 상,하부 단품 패키지(30)(20)들이 부착되도록 상,하부 단품 패키지(30)(20)의 사이에 개재되는 써멀 테이프(40)로 구성되어 있다.FIG. 5 is a longitudinal cross-sectional view showing the structure of the present invention, the stacked gap lead package. As shown in the drawing, the semiconductor chip 21 and the lead 22 are connected by a wire 23, and the ends of the lead 22 are exposed. The lower unit package 20 having the molding unit 24 formed thereon so that the terminal portion 22a is formed and one side of the chip 21 is formed with the exposed surface 21a, and an upper side of the lower unit package 20. The semiconductor chip 31 and the lead 32 are connected to each other by a wire 33, and the protruding end 32a is formed to protrude and bend the end of the lead 32, and one side of the chip 31. The upper and lower unit packages 30 and the upper and lower unit packages 30 and 20 to which the molding unit 34 is formed to form the exposed surface 31a and the upper and lower unit packages 30 and 20 are attached. It is comprised by the thermal tape 40 interposed between.

상기 상부 단품 패키지(30)의 몰딩부(34) 외측으로 돌출되어 있는 돌출단자부(32a)는 하부 단품 패키지(30)의 몰딩부(24) 외측에 노출되는 노출단자부(22a)에 근접되도록 "L"자형으로 절곡되어, 기판에 실장시 돌출단부(32a)와 노출단자부(22a)를 동시에 솔더링 접합 할 수 있도록 되어 있다.The protruding terminal portion 32a protruding outward from the molding portion 34 of the upper unit package 30 is positioned to be close to the exposed terminal portion 22a exposed outside the molding unit 24 of the lower unit package 30. It is bent in a shape so that the protruding end portion 32a and the exposed terminal portion 22a can be soldered together at the time of mounting on the substrate.

상기 써멀 테이프(40)는 솔더링 온도, 패키지 동작시 발생되는 온도, 패키지 설치시의 주변온도 등을 감안하여 약200℃내의 온도에도 떨어지지 않는 강한 접착력을 갖는 것이 바랍직하다.The thermal tape 40 preferably has a strong adhesive strength that does not drop even in the temperature of about 200 ℃ in consideration of the soldering temperature, the temperature generated during the package operation, the ambient temperature during the package installation.

상기와 같이 구성되어 있는 본 발명 적층형 버틈 리드 패키지(50)를 제조하는 순서를 다음과 같다.The procedure for manufacturing the present invention laminated bump lid package 50 configured as described above is as follows.

반도체 칩(21)과 리드(22)를 와이어(23)로 연결하고, 리드(22)의 단부가 노출되도록 노출단부(22a)를 형성시킴과 아울러 칩(21)의 일측에 노출면(21a)이 형성되도록 몰딩하여 몰딩부(24)를 형성하여 완성하는 하부 단품 패키지(20)의 제작한다.The semiconductor chip 21 and the lead 22 are connected by a wire 23, and an exposed end portion 22a is formed to expose an end portion of the lead 22, and an exposed surface 21a is formed on one side of the chip 21. Molding is formed so that the molding unit 24 is formed to produce a lower single-piece package 20 to be completed.

그리고, 그와는 별도로 반도체 칩(31)과 리드(32)를 와이어(33)로 연결하고, 리드(32)의 단부가 돌출되도록 돌출단자부(32a)를 형성시킴과 아울러 칩(31)의 일측에 노출면(31a)이 형성되도록 몰딩하여 몰딩부(34)를 형성하여 단품 패키지를 완성하는 상부 단품 패키지(30)를 제작한다.In addition, the semiconductor chip 31 and the lead 32 are connected to each other by the wire 33, and the protruding terminal portion 32a is formed so that the end of the lead 32 protrudes, and one side of the chip 31. The upper surface package 30 is formed by molding the exposed surface 31a to form the molding unit 34 to complete the single package.

그런 다음, 도 6과 같이 상기 하부 단품 패키지(20)의 상면에 써멀 테이프(40)를 부착하고, 그 써멀 테이프(40)의 상면에 상부 단품 패키지(30)를 부착고정하여 간단하게 적층형 반도체 패키지(50)를 완성한다.Then, as illustrated in FIG. 6, the thermal tape 40 is attached to the upper surface of the lower single package 20, and the upper single package 30 is attached and fixed to the upper surface of the thermal tape 40, thereby simplifying the stacked semiconductor package. Complete 50.

그리고, 상기와 같이 적층형 버틈 리드 패키지(50)는 전기적인 특성검사를 실시하게 되는데, 그와 같은 전기적인 특성검사를 실시하여 단품 패키지의 이상이 발견되면 써멀 테이프(40)로 부착된 상,하부 단품 패키지(30)(20)를 해체하고 수리하면 된다.Then, as described above, the laminated buried lid package 50 is subjected to the electrical property test, if the abnormality of the single package is found by performing such an electrical property test, the upper and lower parts attached to the thermal tape 40 What is necessary is to disassemble and repair the one-piece packages 30 and 20.

또한, 상기와 같은 적층형 버틈 리드 패키지(50)의 실장작업은 도 7에 도시된 바와 같이, 피시비(60)의 상면에 노출된 랜드(60a) 상면에 노출단자부(22a)와 돌출단자부(32a)가 얹혀지도록 얼라인 하고, 그 노출단자부(22a)와 돌출단자부(32a)를 솔더(61)로 일시에 접합한다.In addition, as shown in FIG. 7, the mounting work of the stacked gap lead package 50 may be performed by exposing the exposed terminal portion 22a and the protruding terminal portion 32a to the upper surface of the land 60a exposed to the upper surface of the PCB 60. Is aligned so that the exposed terminal portion 22a and the projecting terminal portion 32a are temporarily bonded with the solder 61.

이상에서 상세히 설명한 바와 같이, 본 발명 적층형 버틈 리드 패키지 및 그 제조방법은 하부 단품 패키지와 상부 단품 패키지가 부착고정되도록 써멀 테이프를 개재하여 간단히 구성함으로써, 품질이상으로 수리시에는 상부 단품 패키지와 하부 단품 패키지가 써멀 테이프에서 떨어지도록 간단히 해체하여 수리할 수 있고, 종래와 같이 솔더링으로 접합하지 않고 써멀 테이프를 이용하여 간단히 부착하여 제조함으로써 제조시간 및 비용을 절감하는 효과가 있다.As described in detail above, the present invention, the laminated buckle lead package and the manufacturing method thereof are simply configured through the thermal tape so that the lower single package and the upper single package are attached and fixed, so that the upper single package and the lower single piece are repaired at a quality or higher. The package can be easily disassembled and repaired so that the package is separated from the thermal tape, and there is an effect of reducing manufacturing time and cost by simply attaching and manufacturing the thermal tape instead of joining by soldering.

Claims (3)

반도체 칩과 리드들이 와이어로 각각 연결되고, 그 리드들의 노출단자부가 노출되도록 몰딩부가 형성되는 하부 단품 패키지와; 그 하부 단품 패키지의 상측에 배치되며 반도체 칩과 리드들이 와이어로 각각 연결되고, 상기 리드의 일정부분이 돌출되어 돌출단자부가 형성되도록 몰딩부가 형성됨과 아울러 그 돌출단자부가 노출단자부에 근접되도록 절곡되는 상부 단품 패키지와; 상기 하부 단품 패키지와 상부 단품 패키지의 사이에 개재되어 상,하부 단품 패키지를 접합시키기 위한 써멀 테이프를 구비하여서 구성되는 것을 특징으로 하는 적층형 버틈 리드 패키지.A lower one-piece package in which semiconductor chips and leads are respectively connected by wires, and molding parts are formed to expose exposed terminals of the leads; The upper part is disposed above the lower unit package and the semiconductor chip and the leads are respectively connected by wires, and a molding part is formed to protrude a part of the lead to form a protruding terminal part, and an upper part of which the protruding terminal part is bent to approach the exposed terminal part. A la carte package; Stacked gap lead package is characterized in that it is provided with a thermal tape interposed between the lower one-piece package and the upper one-piece package for bonding the upper, lower one-piece package. 제 1항에 있어서, 상기 돌출단자부는 노출단자부에 근접되도록 절곡되어 실장시 동시에 접합되도록 한 것을 특징으로 하는 적층형 버틈 리드 패키지.The stack type lead lid package of claim 1, wherein the protruding terminal portion is bent close to the exposed terminal portion so that the protruding terminal portion is simultaneously bonded during mounting. 반도체 칩과 리드가 와이어로 연결되고, 리드의 단부가 노출되는 노출단자부가 형성됨과 아울러 칩의 일측에 노출면이 형성되도록 몰딩부가 형성되어 있는 하부 단품 패키지의 노출면에 써멀 테이프를 부착하는 단계와;Attaching a thermal tape to the exposed surface of the lower single-piece package in which the semiconductor chip and the lead are connected by wires, and an exposed terminal portion at which the end of the lead is exposed, and a molding portion is formed to form an exposed surface on one side of the chip; ; 반도체 칩과 리드가 와이어로 연결되고, 리드의 단부가 돌출되어 절곡되도록 돌출단자부가 형성됨과 아울러 칩의 일측에 노출면이 형성되도록 몰딩부가 형성되어 있는 상부 단품 패키지의 노출면이 상기 써멀 테이프의 상면에 부착되도록 상부 단품 패키지를 부착하는 단계의 순서로 제작되는 것을 특징으로 하는 적층형 버틈 리드 패키지의 제조방법.The exposed surface of the upper single-piece package in which the semiconductor chip and the lead are connected by a wire, a protruding terminal portion is formed to protrude and bend the ends of the lead, and a molding portion is formed to form an exposed surface on one side of the chip, is an upper surface of the thermal tape. The manufacturing method of the laminated buried lid package, characterized in that the manufacturing in the order of the step of attaching the upper unit package to be attached to.
KR1019990040685A 1999-09-21 1999-09-21 Stacked bottom lead package and manufacturing method thereof KR20010028434A (en)

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