KR20010019862A - Duty cycle generator - Google Patents

Abstract

PURPOSE: A generator of duty cycle is provided to produce exactly 50% duty cycles without doubling the frequency of the voltage control oscillator through an amplifying process. CONSTITUTION: A generator of 50% duty cycle includes three inverters(10,20,30) connected in parallel between a power supply voltage source(VDD) and an earth voltage source(GND). Each inverter(10,20,30) includes a PMOS transistor(MP1,MP2,MP3) and a NMOS transistor(MN1,MN2,MN3) whose current lines are connected in a series. Here, the node(N3) of the drains of the third PMOS(MP3) and the third NMOS(MN3) makes a feedback loop by being connected to the node(N1) shared by the gates of the first PMOS(MP1) and the first NMOS(MN1). And a control voltage(Vctrl) occurs at the third node(N3) connected both to the drains of the third PMOS(MP3) and the first NMOS(MN3) of the third invertor(30). This control voltage(Vctrl) is feedbacked to the gates of the first PMOS(MP1) and first NMOS(MN1) of the first invertor(10). Between the control voltage(Vctrl) and the ground voltage(GND), the first resistance(R1) and the first capacitor(C1) come in a series. An input signal of the generator of 50% duty cycle is given to the first node(N1) and the second node(N2) produces an output signal.

Description

Duty cycle generator {DUTY CYCLE GENERATOR}

The present invention relates to a system clock generator, and more particularly to a 50% duty cycle generator.

In order to transmit and receive data accurately, the retention time of each bit of output data must be constant. This requires a system with an accurate 50% duty cycle with the same frequency as the transmission frequency of the data.

1 is a diagram illustrating a method of obtaining a duty cycle. Referring to Fig. 1, the duty cycle is defined as T1 / (T1 + T2) when there is a certain periodic signal. Thus, the 50% duty cycle means that T1 and T2 are the same.

Conventionally, a method of oscillating a voltage controlled oscillator at a frequency twice the transmission frequency and using the frequency divider to reduce the frequency of this signal in half to make this system clock is used. However, the conventional method suffers from the burden of oscillating the voltage controlled oscillator at twice the frequency.

Thus, what is needed is a system that can generate an accurate 50% duty cycle without oscillating the voltage controlled oscillator at twice the frequency.

Accordingly, an object of the present invention is to provide a duty cycle generator capable of generating an accurate 50% duty cycle without oscillating a voltage controlled oscillator at twice the frequency, which has been proposed to solve the above-mentioned problems.

1 is a diagram illustrating a method of obtaining a duty cycle;

2 shows a 50% duty cycle generator in accordance with a preferred embodiment of the present invention;

3A is a diagram to show an input signal of the 50% duty cycle generator shown in FIG. 2;

3B is a diagram for showing an output signal of the 50% duty cycle generator shown in FIG. 2 in accordance with the input signal of FIG. 3A;

3C is a diagram to show the control voltage Vctrl of the 50% duty cycle generator shown in FIG. 2;

4A is a diagram to show an input signal of the 50% duty cycle generator shown in FIG. 2;

4B is a diagram for showing an output signal of the 50% duty cycle generator shown in FIG. 2 according to the input signal of FIG. 4A; And

4C is a diagram to show the control voltage Vctrl of the 50% duty cycle generator shown in FIG.

* Description of the symbols for the main parts of the drawings *

10: first inverter 20: second inverter

30: third inverter 40: first current source

50: second current source 100: 50% duty cycle generator

According to a feature of the invention for achieving the object of the invention as described above, the duty cycle generator comprises: a first voltage source for supplying a power supply voltage; A second voltage source for supplying a ground voltage; A first inverter comprising a first PMOS transistor and a first NMOS transistor connected in series with a current path between the first and second voltage sources; A second inverter including a second PMOS transistor and a second NMOS transistor connected in series with a current path between the first and second voltage sources; A first current source connected in series with said first voltage source; A second current source connected in series with said second voltage source; A third inverter including a third PMOS transistor and a third NMOS transistor connected in series with a current path between the first and second current sources; A drain connected to the drains of the first PMOS transistor and the first NMOS transistors of the first inverter and the gates of the second PMOS transistor and the second NMOS transistors of the second inverter in common to receive an input signal; 1 node; A second terminal connected in common with the drains of the second PMOS transistor and the second NMOS transistors of the second inverter and the gates of the third PMOS transistor and the third NMOS transistors of the third inverter to generate an output signal; 2 nodes; The drains of the third and third NMOS transistors of the third inverter and the gates of the first and first NMOS transistors of the first inverter are commonly connected to generate a control voltage. A third node for feeding back to the first inverter; And a first resistor and a first capacitor connected in series between the third node and the second voltage source. Here, the third PMOS transistor and the third NMOS transistors of the third inverter serve as a switch for generating the control voltage by charging or discharging the voltage of the third node.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 2 through 4C.

The novel 50% duty cycle generator of the present invention includes first to third inverters connected in parallel between a power supply voltage source and a ground voltage source. These inverters each include a PMOS transistor and an NMOS transistor in which current paths are connected in series. In particular, first and second current sources for charging or discharging the third inverter are connected between the third inverter and the power supply voltage source and between the third inverter and the ground voltage source, respectively. The control voltage is generated according to the result of charging or discharging of the third inverter, and the control voltage is fed back to the first inverter to control the final output voltage to have a duty cycle of 50%.

2 is a diagram illustrating a 50% duty cycle generator 100 according to a preferred embodiment of the present invention. Referring to FIG. 2, the 50% duty cycle generator 100 according to the present invention includes first to third inverters 10, 20, and 30 composed of a PMOS transistor and an NMOS transistor. The first inverter 10 includes a first PMOS transistor MP1 and a first NMOS transistor MN1 having a current path connected in series, and the second inverter 20 has a second PMOS transistor (with a current path connected in series). The third inverter 30 includes a third PMOS transistor MP3 and a third NMOS transistor MN3 having a current path connected in series.

The first to third inverters 10, 20, and 30 are connected in parallel between the power supply voltage VDD and the ground voltage GND, respectively. In particular, the first current source 40 is connected between the source of the third PMOS transistor MP3 constituting the third inverter 30 and the power supply voltage VDD. The second current source 50 is connected between the source of the third NMOS transistor MN3 of the third inverter 30 and the ground voltage GND.

The connection point (ie, the first node N1) of the drain of the first PMOS transistor MP1 and the first NMOS transistor MN1 constituting the first inverter 10 constitutes the second inverter 20. Are connected to the gates of the second PMOS transistor MP2 and the second NMOS transistor MN2. Similarly, the connection point (that is, the second node N2) of the drain of the second PMOS transistor MP2 and the second NMOS transistor MN2 constituting the second inverter 20 connects the third inverter 30. The gates of the third PMOS transistor MP3 and the third NMOS transistor MN3 are commonly connected.

In addition, a connection point where the drains of the third PMOS transistor MP3 and the third NMOS transistor MN3 of the third inverter 10 meet each other may be connected to the first PMOS transistor MP1 and the first NMOS transistor (1) of the first inverter 10. Forming a feedback loop connected to the gates of MN1). Here, the control voltage Vctrl is generated at the third node N3, which is a connection point where the drains of the third PMOS transistor MP3 and the third NMOS transistor MN3 of the third inverter 10 meet. Vctrl is fed back to the gates of the first PMOS transistor MP1 and the first NMOS transistor MN1 of the first inverter 10. The first resistor R1 and the first capacitor C1 are connected in series between the control voltage Vctrl and the ground voltage GND. An input signal of the 50% duty cycle generator 100 according to the present invention is applied to the first node N1, and an output signal of the 50% duty cycle generator 100 according to the present invention is applied to the second node N2. Is generated.

First, the operation of the 50% duty cycle generator 100 when a signal having a duty cycle of less than 50% is input through the first node N1 is as follows.

FIG. 3A is a diagram for showing an input signal of the 50% duty cycle generator shown in FIG. 2, and FIG. 3B is a diagram for showing an output signal of the 50% duty cycle generator shown in FIG. 2 according to the input signal of FIG. 3A. Drawing. 3C is a diagram for illustrating a control voltage Vctrl of the 50% duty cycle generator illustrated in FIG. 2.

Referring to Figure 3A, the input signal has a duty cycle of 20%. In this case, the duty cycle at the second node N2 is smaller than 50%, and the level of the control voltage Vctrl is increased. Here, the third PMOS transistor MP3 and the third NMOS transistor MN3 of the third inverter 30 serve as a switch. As described above, when the level of the control voltage Vctrl increases to some extent, the resistance value of the first transistor MN1 becomes smaller than the resistance value of the second PMOS transistor MP2 at the first node N1. . As a result, the average value of the voltage levels of the first node N1 becomes smaller than the initial stage. Therefore, the duty cycle of the second node N2 becomes large.

Finally, the control voltage Vctrl is stabilized to an arbitrary value (for example, 1.674 V) as shown in FIG. 3C, wherein the output signal at the second node N2 is shown in FIG. 3B. As near to 50% duty cycle. As described above, the 50% duty cycle generator 100 according to the present invention performs an accurate 50% duty cycle without oscillating the voltage controlled oscillator at twice the frequency even when an input signal having a duty cycle of less than 50% is input. Can be generated.

Next, when a signal having a duty cycle of 50% or more is input through the first node N1, the operation of the 50% duty cycle generator 100 is as follows.

4A is a diagram for showing an input signal of the 50% duty cycle generator shown in FIG. 2, and FIG. 4B is a diagram for showing an output signal of the 50% duty cycle generator shown in FIG. 2 according to the input signal of FIG. 4A. Drawing. 4C is a diagram illustrating the control voltage Vctrl of the 50% duty cycle generator shown in FIG. 2.

4A, the input signal has a duty cycle of 80%. In this case, the duty cycle at the second node N2 is greater than 50%, and the level of the control voltage Vctrl is lowered. When the level of the control voltage Vctrl is lowered to some extent, the resistance value of the first transistor MN1 is greater than the resistance value of the second PMOS transistor MP2 at the first node N1. As a result, the average value of the voltage levels of the first node N1 becomes larger than the initial stage. Therefore, the duty cycle of the second node N2 becomes small.

Accordingly, the control voltage Vctrl is stabilized to an arbitrary value (for example, 1.271 V) as shown in FIG. 4C, where the output signal at the second node N2 is shown in FIG. 4B. As near to 50% duty cycle. As described above, even if an input signal having a duty cycle of 50% or more is input, the 50% duty cycle generator 100 according to the present invention generates an accurate 50% duty cycle without oscillating the voltage controlled oscillator at twice the frequency. You can.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely described, for example, and various changes and modifications are possible without departing from the spirit of the present invention. .

According to the present invention as described above, even if an input signal having a duty cycle of less than 50% or more than 50% is input, it is possible to generate an accurate 50% duty cycle without oscillating the voltage controlled oscillator at twice the frequency.

Claims (2)

For duty cycle generators: A first voltage source for supplying a power supply voltage; A second voltage source for supplying a ground voltage; A first inverter comprising a first PMOS transistor and a first NMOS transistor connected in series with a current path between the first and second voltage sources; A second inverter including a second PMOS transistor and a second NMOS transistor connected in series with a current path between the first and second voltage sources; A first current source connected in series with said first voltage source; A second current source connected in series with said second voltage source; A third inverter including a third PMOS transistor and a third NMOS transistor connected in series with a current path between the first and second current sources; A drain connected to the drains of the first PMOS transistor and the first NMOS transistors of the first inverter and the gates of the second PMOS transistor and the second NMOS transistors of the second inverter in common to receive an input signal; 1 node; A second terminal connected in common with the drains of the second PMOS transistor and the second NMOS transistors of the second inverter and the gates of the third PMOS transistor and the third NMOS transistors of the third inverter to generate an output signal; 2 nodes; The drains of the third and third NMOS transistors of the third inverter and the gates of the first and first NMOS transistors of the first inverter are commonly connected to generate a control voltage. A third node for feeding back to the first inverter; And And a first capacitor and a first capacitor connected in series between the third node and the second voltage source. The method of claim 1, And the third PMOS transistors and third NMOS transistors of the third inverter serve as a switch for generating the control voltage by charging or discharging the voltage of the third node.