KR100518240B1 - Circuit for generating substrate voltage of semiconductor memory - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate voltage generation circuit of a semiconductor memory. In the related art, the capacitances of the semiconductor memory have different capacities for distinguishing an active state with a large variation in the substrate voltage and a standby state with a small variation in the substrate voltage, such as a high-speed operation or an internal buffer operation. As each substrate voltage generator is used, it is difficult to obtain a stable substrate voltage VBB while consuming little power to generate the substrate voltage VBB. Therefore, in the substrate voltage generation circuit including the ring oscillator 10, the driver 11, and the charge pump 12, the non-inverting terminal supplies the VCC voltage and is applied to the inverting terminal. In accordance with CON1), and further comprising a transfer gate 13 for transmitting the pulse output from the drive unit 11 to the charge pump 12 as it is or to reduce the amplitude of the pulse, applied to the MOS capacitor of the charge pump It is possible to change the amplitude of the oscillation pulse, so that the pump can be appropriately pumped in a section with a high VBB fluctuation and a section with a small fluctuation during the memory operation. In addition, the pulse amplitude is reduced when the power supply voltage rises excessively to prevent the charge pump from excessively lowering the VBB power supply.

Description

CIRCUIT FOR GENERATING SUBSTRATE VOLTAGE OF SEMICONDUCTOR MEMORY}

The present invention relates to a substrate voltage generating circuit of a semiconductor memory for generating a substrate voltage (VBB) used in a semiconductor memory. In particular, the amplitude of a pulse applied to a pump capacitor is divided into a section having a high VBB variation and a section having a small variation. The present invention relates to a substrate voltage generation circuit of a semiconductor memory capable of simultaneously implementing a VBB generator having a separate pumping capability.

FIG. 1 is a configuration diagram of a substrate voltage generating circuit of a conventional semiconductor memory. As shown in FIG. 1, a ring oscillator 10 generating a constant oscillation pulse OSC and a buffering oscillation pulse OSC generated above are shown. And a driver 11 for outputting the buffered pulse OSCDRV, and a charge pump 12 for pumping the pulse OSCDRV driven by the driver 11 to generate a substrate voltage.

Referring to the prior art configured as described above in detail.

When the oscillation pulse OSC is output from the ring oscillator 10 composed of an odd number of inverters, the oscillation pulse OSC is outputted by the driving unit 11 to perform buffering.

The buffered oscillator OSCDRV is provided to the charge pump 12 by the driver 11.

Then, the MOS capacitor C1 of the charge pump 12 is charged, and the substrate voltage VBB is lowered by the transistors Q1 and Q2 which are always turned on when the MOS capacitor C1 is charged.

FIG. 2 illustrates a case in which different substrate voltage generators are used in the active period ACTIVE and the standby period STANDBY, respectively. The standby substrate voltage generator 21 is formed by the charge pump rather than the active substrate voltage generator 22. The capacity is designed to be small because the variation of the standby substrate is less than the active period.

However, in the prior art as described above, substrate voltage generators having different capacities are used for distinguishing between active at high substrate voltages and standby at low substrate voltages such as high-speed operation of internal circuits or buffer operation. Accordingly, there is a problem in that it is difficult to obtain a stable substrate voltage VBB while consuming little power to generate the substrate voltage VBB, and in particular, excessive pumping becomes a problem when the external power source rises.

Accordingly, an object of the present invention for solving the above problems is to provide a substrate voltage generation circuit of a semiconductor memory capable of changing the amplitude of the oscillation pulse applied to the MOS capacitor of the charge pump.

Another object of the present invention is to provide a substrate voltage generation circuit of a semiconductor memory having a separate pumping capability by adjusting an amplitude corresponding to a section in which VBB fluctuates greatly and a section in which the fluctuation is small during operation of the semiconductor memory.

It is still another object of the present invention to provide a substrate voltage generation circuit of a semiconductor memory which prevents the charge pump from dropping the VBB power supply excessively by reducing the pulse amplitude when the power supply voltage rises excessively.

In order to achieve the above object, the present invention provides a substrate voltage generation circuit including a ring oscillator, a driving unit, and a charge pump, wherein a non-inverting terminal is connected to a power terminal, and an inverting terminal is connected to a control terminal. It characterized in that it further comprises a transmission gate to adjust the output voltage of the driver in accordance with the signal applied to provide to the charge pump.

Hereinafter, with reference to the accompanying drawings in detail.

FIG. 3 is a first embodiment of a substrate voltage generation circuit of a semiconductor memory of the present invention. As shown in FIG. 3, a ring oscillator 10 for generating a constant oscillation pulse OSC and the oscillation pulse OSC generated above are shown. ) And a driver 11 for outputting the buffered pulse OSCDRV, a transfer gate 13 for transmitting the pulse output from the driver 11 as it is or reducing the amplitude, and the transfer gate 13. ) Is configured as a charge pump 12 for generating and outputting the required substrate voltage by pumping a pulse whose amplitude is adjusted.

FIG. 4 shows a second embodiment of the substrate voltage generating circuit of the semiconductor memory according to the present invention. As shown in FIG. 4, a ring oscillator 10 for generating a constant oscillation pulse OSC and the oscillation pulse OSC generated above are shown. ) Is buffered and outputs the buffered pulse OSCDRV and the amplitude of the pulse output to the driver 11 according to the first control signal CON1 applied to the inverting terminal. In the transfer gate 13, the charge pump 12 to generate the required substrate voltage by pumping the pulse output from the transfer gate 13, the active period of the substrate fluctuating and the standby period of the fluctuation is not severe The voltage selector 14 provides a second control signal CON2 for adjusting the pumping operation of the charge pump to the non-inverting terminal of the transfer gate 13.

FIG. 5 is a third embodiment of the substrate voltage generation circuit of the semiconductor memory of the present invention. As shown therein, a ring oscillator 10 for generating a constant oscillation pulse OSC, and the oscillation pulse OSC generated above, are shown in FIG. ) Is buffered and outputs the buffered pulse OSCDRV and the amplitude of the pulse output to the driver 11 according to the first control signal CON1 applied to the inverting terminal. A transfer gate 13, a charge pump 12 generating a desired substrate voltage by pumping pulses output from the transfer gate 13, and a control signal CON of the transfer gate 13 according to the level of an external power source. ) Is configured as a VCC power detector (15) for controlling.

Referring to the operation and effect of the present invention configured as described in detail as follows.

When a constant pulse OSC is generated in the ring oscillator 10 of FIG. 3, the buffered oscillator 10 is buffered as shown in FIG. 6A so as to be received and used by the driver 11, and transmits the buffered pulse OSCDRV. To the gate 13.

In this case, the control signal CON1 in the low state is applied to the inverting terminal in the active section in which the variation of the substrate is severe.

Since the VCC power source is continuously input to the non-inverting terminal of the transfer gate 13, the NMOS transistor MN1 is continuously turned on.

The PMOS transistor MP1 is also turned on by applying the control signal CON1 in the low state to the inverting terminal of the transfer gate 13.

Accordingly, the driving pulse OSCDRV provided from the driving unit 11 passes through the transmission gate 13 as it is, as shown in FIG. 6C, and is caught by the NA node.

In addition, when the control circuit CON1 of the high state is provided to the inverting terminal of the transfer gate 13 in the standby period in which only the refresh circuit operates, as shown in FIG. 6B, the PMOS transistor MP1 is turned off. The node NA is reduced to the amplitude of VCC-VT as shown in (c) of FIG. 6. Here, VT is the threshold voltage of the NMOS transistor MN1 of the transfer gate 13.

Therefore, in interval A, node B has an amplitude of VT-VCC during the pumping operation, and in interval B, node B has an amplitude of 2VT-VCC during the pumping operation.

As a result, the pumping suppression effect is more pronounced in the standby period than in the active period.

4 and 7, when the driving unit 11 provides the buffering pulse OSCDRV to the transfer gate 13 as shown in FIG. In FIG. 7B, the first control signal CON1 and the second control signal CON2 in a low state are applied.

Since the second control signal CON2 in the low state is inverted through the inverter I1, the node N1 becomes high.

Accordingly, the first transmission gate TG1 is turned on and the second transmission gate TG2 is turned off.

As the first transmission gate TG1 is turned on, the VCC power is applied to the non-inverting terminal of the transmission gate 13 via the node N2.

Accordingly, both the PMOS and NMOS transistors MP1 and MN1 of the transfer gate 13 are turned on, and the driving pulse OSCDRV provided from the driver 11 is provided at the node NA as shown in FIG. Pulses appear.

In the standby period in which only the refresh circuit operates, the first control signal CON1 in the high state as shown in (b) of FIG. 7 and the second control signal CON2 in the low state as shown in (c) of FIG. Is authorized.

The VCC power is applied to the non-inverting terminal of the transfer gate 13 by the second control signal CON2 in the low state, and the PMOS of the transfer gate 13 is applied by the first control signal CON1 in the high state. Since the transistor MP1 is turned off, the node NA is reduced to the amplitude of VCC-VT as shown in FIG.

In this state, when the standby section waits only for the next operation, as shown in section C of FIG. 7C, the second control signal CON2 is changed from the low state to the high state.

This is inverted by the inverter I1 and brought to a low state at the node N1.

Since the first transfer gate TG1 is turned off and the second transfer gate TG2 is turned on by the low signal, the reference voltage VREF is applied to the node N2. It is applied to the non-inverting terminal of 13).

Therefore, the voltage applied to the node NA via the transfer gate 13 becomes VREF-VT as shown in FIG.

Where VREF is a reference voltage lower than VCC-VT.

5 and 8, the semiconductor memory may vary from 3.0V to 3.6V based on 3.3V.

If the external power is 3.6 V or more, the amplitude of the driving pulse OSCDRV output from the driving unit 11 of FIG. 5 has an amplitude of 3.6 V or more, causing excessive pumping of the charge pump 12.

Therefore, in this case, the VCC power detector 15 supplies the output signal OUT of the high state as shown in (b) of FIG. 8 to the inverting terminal of the transmission gate 13.

Then, since the PMOS transistor MP1 of the transfer gate 13 is turned off and the NMOS transistor MN1 is turned on, the threshold voltage of the NMOS transistor MN1 is applied to the output pulse OSCDRV of the driver 11. The charge pump 12 is applied to a voltage reduced by VT), that is, a VCC-VT voltage as shown in FIG.

Therefore, overpumping of the charge pump 12 is suppressed.

When the external power source is 3.6 V or less, the PMOS transistor MP1 is turned on by providing the low signal OUT to the inverting terminal of the transfer gate 13.

Therefore, the driving pump OSCDRV output from the driving unit 11 to the charge pump 12 is directly provided to the charge pump 12.

By the above operation, the amplitude of the oscillation pulse applied to the MOS capacitor C1 of the charge pump 12 can be changed and provided.

As described in detail above, it is possible to change the amplitude of the oscillation pulse applied to the MOS capacitor of the charge pump, so that the pump can be suitably pumped in a section having a high VBB fluctuation and a section having a small fluctuation during the memory operation. In addition, the pulse amplitude is reduced when the power supply voltage rises excessively, thereby preventing the charge pump from excessively lowering the VBB power supply.

1 is a circuit diagram of a substrate voltage generation of a conventional semiconductor memory.

2 is a diagram illustrating a case where different substrate voltage generators are used in an active section and a standby section, respectively.

3 is a first embodiment of a substrate voltage generation circuit of the semiconductor memory of the present invention;

Fig. 4 is a second embodiment of the substrate voltage generation circuit of the semiconductor memory of the present invention.

Fig. 5 is a third embodiment of the substrate voltage generation circuit of the semiconductor memory of the present invention.

FIG. 6 is a signal waveform diagram of each part shown in FIG. 3; FIG.

FIG. 7 is a signal waveform diagram of each part shown in FIG. 4; FIG.

FIG. 8 is a signal waveform diagram of each part shown in FIG. 5; FIG.

*** Explanation of symbols for main parts of drawing ***

10 ring oscillator 11 drive unit

12 charge pump 13 transfer gate

14: voltage selector 15: VCC power detector

C1: MOS capacitor I1: Inverter

Claims (4)

In the substrate voltage generation circuit composed of the ring oscillator 10, the driver 11, and the charge pump 12, the non-inverting terminal is supplied with the VCC voltage, and according to the control signal CON1 applied to the inverting terminal. And a transfer gate (13) for transmitting the pulse output from the driver (11) to the charge pump (12) as it is or reducing the amplitude of the pulse. In the substrate voltage generation circuit composed of the ring oscillator 10, the drive unit 11, and the charge pump 12, the non-inverting terminal supplies the VCC voltage or the reference voltage VREF and is applied to the inverting terminal. According to the first control signal (CON1) according to the transmission gate 13 for transmitting the pulse output from the drive unit 11 to the charge pump 12 as it is or to reduce the amplitude of the pulse and the second control signal (CON2) And a voltage selector (14) for supplying a VCC voltage or a reference voltage (VREF) to the non-inverting terminal of the transfer gate (13). The inverter of claim 2, wherein the voltage selector is configured to receive an inverter I1 for inverting the second control signal CON2, the second control signal as an inverting terminal, and an output signal of the inverter I1 as a non-inverting terminal. The first transmission gate TG1 for transmitting or blocking the VCC power to the non-inverting terminal of the transmission gate 13 and the second control signal CON2 as the non-inverting terminal and receiving the output signal of the inverter I1. Is a second transfer gate (TG2) for receiving or transmitting a reference voltage (VREF) to the non-inverting terminal of the transfer gate (13) by applying an inverting terminal. In the substrate voltage generation circuit composed of the ring oscillator 10, the driving unit 11, and the charge pump 12, the non-inverting terminal is supplied with the VCC voltage, according to the signal OUT applied to the inverting terminal. Transmission gate 13 for transmitting the pulse output from the driver 11 to the charge pump 12 as it is or to reduce the amplitude of the pulse and a signal for detecting the magnitude of the external power source to have a small amplitude if the predetermined voltage or more And a VCC power detector (15) for providing OUT to the inverting terminal of the transfer gate (13).