KR20010018733A - Circuit For Switching Synchronous Signal in Display Apparatus and Method thereof - Google Patents

Abstract

PURPOSE: A circuit and a method for switching synchronous signal for a displayer is provided to make on screen display possible regardless of image signal input and manufacturing company of liquid crystal display. CONSTITUTION: The circuit for switching synchronous signal for a displayer includes a horizontal synchronous separating part(6), a vertical synchronous separating part(4), a free running signal generating part(2), and a logic part. The horizontal synchronous separating part(6) extracts horizontal synchronous signal from inputted image signal. The vertical synchronous separating part(4) extracts vertical synchronous signal from the image signal. The free running signal generating part(2) generates free running signal of prescribed frequency. The logic part outputs the horizontal and vertical synchronous signals by cutting off the free running signal while image signal is supplied. The logic part generates a second horizontal synchronous signal and a second vertical synchronous signal by using the free running signal while the image signal is not supplied.

Description

Circulation for Switching Synchronous Signal in Display Apparatus and Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization signal switching circuit and method for a display device, and more particularly to a synchronization signal switching circuit and method for enabling an on-screen display regardless of whether an image signal is inputted.

In general, a cathode water tube television generates a synchronization signal for an On Screen Display (OSD) using an output signal of a flyback transformer.

On the other hand, in a liquid crystal display device in which a flyback transformer is not used, it is not easy to generate an on-screen display synchronization signal in the absence of an image signal. In order to obtain such a synchronization signal, horizontal and vertical synchronization signals input to the liquid crystal display panel must be applied to a microcomputer (μ-COM). Then, the microcomputer can supply the on-screen display data to the liquid crystal panel based on the horizontal and vertical synchronization signals input from the liquid crystal panel.

However, liquid crystal display panels have different input / output terminals for each manufacturer, and since input / output terminals cannot be changed, input / output lines should be changed according to the liquid crystal display panel when the liquid crystal display panel is changed. That is, in order to enable the on-screen display, three lines for supplying the horizontal synchronizing signal, the vertical synchronizing signal, and the ground voltage (GND) must be connected between the liquid crystal display panel and the microcomputer. Is inevitably dependent on the liquid crystal display panel of a particular manufacturer.

In order to enable the on-screen display regardless of the manufacturer of the liquid crystal display panel, a method of separating the synchronization signal included in the image signal and using it as a reference signal of the on-screen display may be considered. However, if there is no video signal, on-screen display becomes impossible.

Accordingly, it is an object of the present invention to provide a synchronization signal switching circuit and method for a display device that enables on-screen display regardless of whether an image signal is input.

Another object of the present invention is to provide a synchronization signal switching circuit and method for a display device that enables on-screen display regardless of the manufacturer of the liquid crystal display panel.

1 is a circuit diagram showing a synchronization signal switching circuit for a display device according to an embodiment of the present invention.

FIG. 2 is a waveform diagram illustrating voltages on the first and second nodes shown in FIG. 1. FIG.

3 is a waveform diagram illustrating a horizontal synchronizing signal and a vertical synchronizing signal extracted from the video signal shown in FIG. 1;

4 is a waveform diagram illustrating an output signal of the low frequency filters illustrated in FIG. 1.

FIG. 5 is a truth table showing the operation of NAND gates having the threshold voltage shown in FIG.

FIG. 6 is a truth table showing the calculation of NOT gates with the threshold voltage shown in FIG. 1; FIG.

<Description of the code | symbol about the main part of drawing>

1: Oscillator 2: Free Running Synchronization Signal Generator

4: vertical synchronous separator 6: horizontal synchronous separator

8: divider 10,14,26,32: NOT gate with threshold voltage

12,30: Low frequency filter 16,18,20,24,34,36: NAND gate with threshold voltage

22: one-shot multivibrator

In order to achieve the above object, the synchronous signal switching circuit for a display device of the present invention comprises a horizontal synchronous separating means for extracting a horizontal synchronous signal from the input video signal, a vertical synchronous separating means for extracting a vertical synchronous signal from the video signal; And a prerunning signal generating means for generating a prerunning signal having a predetermined frequency, and outputting horizontal and vertical synchronizing signals by cutting off the prerunning signal in a period in which the video signal is supplied, and freeing the signal in a period other than the video signal supply period. Logic means for generating a second horizontal synchronizing signal and a second vertical synchronizing signal using the running signal.

According to an aspect of the present invention, there is provided a method of switching a synchronous signal for a display device, the method including generating a prerunning signal having a predetermined frequency, interrupting the prerunning signal while a video signal is supplied, And outputting a second horizontal synchronizing signal and a second vertical synchronizing signal using the free running signal during a period other than the video signal supply period.

Other objects and features of the present invention in addition to the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 1 to 6.

Referring to FIG. 1, a free-running synchronizing signal generator 2 for generating a free-running synchronizing signal, a horizontal synchronizing separator 6 for separating a horizontal synchronizing signal and a vertical synchronizing signal from an input video signal, and a vertical unit, respectively. A synchronous signal switching circuit for a display device according to the present invention having a synchronous separator 4 is shown.

The operation of the synchronous signal switching circuit for the display device according to the present invention will be described by dividing the video signal is not input and the video signal is input.

In the period in which the video signal is not input, the horizontal synchronous separator 6, the vertical synchronous separator 4, the third node C and the fourth node D maintain the logical state as shown in Table 1 below. .

Output of horizontal sync separator Output of vertical sync separator Third node (C) 4th node (D) LOW LOW HIGH HIGH

When the video signal is not input, the output signals of the horizontal synchronous separator 6 and the vertical synchronous separator 4 maintain low logic as the ground potential GND. The output signal of the horizontal synchronizing separator 6 maintains low logic when no video signal is input. The output signal of the horizontal synchronization separator 6 is supplied to the second NAND gate 18 (hereinafter referred to as "NAND gate") 18 and is also referred to as a first NOT gate (hereinafter referred to as "NOT gate"). The phase inversion is performed by 10) and supplied to the first low frequency filter 12 in which the capacitor C1 and the resistor R1 are connected in parallel. At this time, the free running synchronization signal generator 2 generates a free running synchronization signal of a predetermined frequency generated from the oscillator 1. This free running synchronization signal is commonly supplied to the first input terminal of the first NAND gate 16 and the input terminal of the oscillator 8 via the first node A. FIG. Here, the voltage waveform Va on the first node A, that is, the free running synchronization signal has a frequency of about 15.734 KHz (Fh ≒ 15.734 KHz) as shown in FIG. 2 when the image is displayed in the NTSC method. . The first NAND gate 16 performs an AND logic operation on the output signal of the first low frequency filter 12 and the free-running synchronous signal to supply the input terminal of the third NAND gate 20. As can be seen in FIG. 5, since the output signal of the first low frequency filter 12 maintains high logic, the first NAND gate 16 phases the free running synchronization signal depending on the logic value of the free running synchronization signal. Reversed. That is, the first NAND gate 16 supplies low logic to the third NAND gate 20 when the logic value of the free-running sync signal is high, while high logic is applied to the third NAND gate 20 when the logic value of the free-running sync signal is low. It is supplied to the NAND gate 20. Meanwhile, as shown in the truth table of FIG. 6, the second NOT gate 18 phase-inverts the output signal of the first low frequency filter 12 maintaining high logic to supply the second NAND gate 18. Since low logic signals are input to the two input terminals of the second NAND gate 18, the second NAND gate 18 supplies only the high logic to the third NAND gate 20 during a period in which the image signal is not input. do. Accordingly, the third NAND gate 20 performs an AND logic operation on the output signal of the first NAND gate 16 and the output signal of the second NAND gate 18 to output the horizontal synchronization signal for the on-screen display. Since the output signal of the second NAND gate 18 maintains high logic, the third NAND gate 20 phases the output signal of the first NAND gate 16 depending on the output signal of the first NAND gate 16. Reversed. That is, the third NAND gate 20 outputs a low logic horizontal synchronization signal when the output signal of the first NAND gate 16 is high logic, while the output signal of the first NAND gate 16 is high logic when the output signal of the first NAND gate 16 is low logic. Outputs a horizontal horizontal synchronization signal. Accordingly, the horizontal synchronization signal output from the third NAND gate 20 has the same phase as the free running synchronization signal.

When the video signal is not input, the output signal of the vertical synchronization separator 4 is supplied to one input terminal of the third NOT gate 26 and the fifth NAND gate 34. At this time, the free running synchronization signal generated from the free running synchronization signal generation unit 2 is divided into 256 by the divider 8. The output signal of the divider 8 has a duty ratio of 50 and a frequency near 60 Hz (Fv # 60). The one-shot multivibrator 22 converts the signal of duty ratio 50 output from the divider 8 into a small duty ratio and supplies it to the input terminal of the fourth NAND gate 24. As a result, the duty ratio of the voltage Vb on the second node B becomes smaller as shown in FIG. 2. The duty ratio is reduced in this way in order to be suitable for the microcomputer or the signal processor of the next stage. In other words, if the duty cycle of the vertical synchronization signal becomes large and the high section becomes very long compared to the low section, the signal processing unit of the microcomputer or the next stage becomes difficult to recognize the inputted vertical synchronization signal, thereby making the on-screen display impossible or malfunction. do. The third NOT gate 26 phase-inverts the output signal of the vertical synchronization separator 4 to supply the input terminals of the second low frequency filter 30 and the third NAND gate 24. Therefore, the high logic of the output signal of the third NOT gate 26 is maintained during the period in which the image signal is not input. The fourth NAND gate 24 performs an AND logic operation on the output signal of the one-shot multivibrator 22 and the output signal of the third NOT gate 26 to supply the input terminal of the sixth NAND gate 36. Since the output signal of the third NOT gate 26 maintains high logic, the fourth NAND gate 24 outputs the phase signal by inverting the output signal of the one-shot multivibrator 22. On the other hand, the fourth NOT gate 32 phase-inverts the output signal of the third NOT gate 26 input via the second low frequency filter 30 to supply to the input terminal of the fifth NAND gate 34. The fifth NAND gate 34 performs an AND logic operation on the output signal of the vertical synchronization separator 4 maintaining the low logic and the output signal of the fourth NOT gate 32 to supply the sixth NAND gate 36. do. The fifth NAND gate 34 generates a high logic output signal during a period in which the video signal is not input because the two input signals maintain low logic. The sixth NAND gate 36 performs an AND logic operation on the output signals of the fourth NAND gate 24 and the fifth NAND gate 34 to generate a vertical synchronization signal for the on-screen display. Since the output signal of the fifth NAND gate 34 maintains high logic, the sixth NAND gate 36 inverts the output signal of the fourth NAND gate 24. Therefore, the vertical synchronization signal output from the sixth NAND gate 36 has the same frequency and phase as the output signal of the one-shot multivibrator 22.

As a result, the horizontal synchronizing signal output from the third NAND gate 20 during the period when no image signal is inputted has the same frequency and phase as the pre-running synchronizing signal of approximately 15.734 KHz generated from the free-running synchronizing signal generator 2. Will have The vertical synchronization signal output from the sixth NAND gate 20 has the same frequency and phase as the signal of approximately 60 Hz output from the one-shot multivibrator 22.

When the video signal is input, the horizontal synchronizing separator 6 separates the horizontal synchronizing signal H included in the input video signal, and the vertical synchronizing separator 4 is configured to include the vertical synchronizing signal ( V) will be separated. The horizontal synchronizing signal H and the vertical synchronizing signal V are as shown in FIG. As can be seen in FIG. 3, the horizontal synchronization signal H has a frequency of 15.734 KHz. In addition, the horizontal synchronization signal H has one cycle of 63 µs, the low logic state included in one cycle is 10 µs, and the high logic state is 53 µs. The horizontal synchronizing signal H is phase-inverted by the first NOT gate 10 and its duty ratio is changed very small, such as (10/63) x 100 = 16, and is supplied to the first low frequency filter 12. The first low frequency filter 12 filters the output signal of the first NOT gate 10 and supplies it to the input terminal of the first NAND gate 16 and the input terminal of the second NOT gate 14. As shown in FIG. 4, the output signal of the first low frequency filter 12, that is, the voltage Vc on the third node C, becomes an integrated wave whose maximum level is lower than the threshold voltages Vth of the NOT gate and the NAND gate. Accordingly, the first NAND gate 16 and the second NOT gate 14 recognize the low frequency logic integrated wave input from the first low frequency filter 12. The second NOT gate 14 phase-inverts the output signal of the first integrator 12 and supplies it to the input terminal of the second NAND gate 18. Therefore, the output signal of the second NOT gate 6 maintains high logic in the period in which the image signal is input. The first NAND gate 16 performs an AND logic operation on the output signal of the first low frequency filter 12 and the free running synchronization signal to supply the input terminal to the third NAND gate 20. Here, since the output signal of the first low frequency filter 12 maintains low logic, the output signal of the first NAND gate 16 maintains high logic regardless of the logic state of the free-running synchronous signal. The second NAND gate 18 performs an AND logic operation on the output signal of the second NOT gate 14 and the horizontal synchronizing signal H to supply the input terminal of the third NAND gate 20. Since the output signal of the second NOT gate 14 maintains high logic, the second NAND gate 18 inverts the phase of the horizontal synchronizing signal H and supplies it to the third NAND gate 20. The third NAND gate 20 performs an AND logic operation on the output signals of the first NAND gate 16 and the second NAND gate 18 to output a horizontal synchronization signal for the on-screen display. Since the output signal of the first NAND gate 16 maintains high logic, the third NAND gate 20 inverts the output signal of the second NAND gate 18 in which the horizontal synchronization signal H is phase inverted. It generates a horizontal synchronization signal for the on-screen display. Therefore, the output signal of the third NAND gate 20 has the same frequency as the horizontal synchronizing signal H included in the video signal and its duty ratio becomes smaller than that of the horizontal synchronizing signal H. Meanwhile, the free running synchronization signal is blocked by the first NAND gate 16 as can be seen above.

In the period in which the video signal is input, the vertical synchronization signal V extracted from the vertical synchronization separator 4 has a frequency of 60 Hz as shown in FIG. 3. The vertical synchronization signal V is supplied to input terminals of the third NOT gate 26 and the fifth NAND gate 34. The third NOT gate 26 phase inverts the vertical synchronization signal from the vertical synchronization separator 4. One period of the vertical synchronization signal / V phase-inverted by the third NOT gate 26 is 17 ms, and the low logic state included in one period occupies 200 μs. The duty ratio of this vertical synchronizing signal / V becomes very small, about (200/17000) x 100 = 12. At this time, the free running synchronization signal generated from the free running synchronization signal generation unit 2 is divided into 256 by the divider 8. The output signal of the divider 8 has a duty ratio of 50 and a frequency near 60 Hz (Fv # 60). The one-shot multivibrator 22 converts the signal of duty ratio 50 output from the divider 8 into a small duty ratio and supplies it to the input terminal of the fourth NAND gate 24. Meanwhile, the second low frequency filter 30 filters the phase inverted vertical synchronization signal / V from the third NOT gate 26 to filter the input terminal of the fourth NAND gate 24 and the fourth NOT gate 32. Supply to the input. As shown in FIG. 4, the output signal of the second low frequency filter 30, that is, the voltage Vd on the fourth node D, is an integrated wave whose maximum level is lower than the threshold voltages Vth of the NOT gate and the NAND gate. On the other hand, the output signal of the first low frequency filter 12 and the second low frequency filter 30 in the period in which the image signal is input has a frequency difference but has an integrated waveform form below the threshold voltage Vth. Accordingly, the fourth NAND gate 24 and the fourth NOT gate 32 recognize the integrated wave received from the second low frequency filter 30 as low logic. Therefore, the fourth NOT gate 32 supplies the high logic output signal to the input terminal of the fifth NAND gate 34, and the fourth NAND gate 24 provides logic of the signal output from the one-shot multivibrator 22. The high logic output signal is supplied to the input terminal of the sixth NAND gate 36 regardless of the value. Since the output signal of the fourth NOT gate 32 maintains high logic, the fifth NAND gate 34 inverts the vertical synchronization signal V extracted from the vertical synchronization separator 4 to phase shift the sixth NAND gate ( It is supplied to the input terminal of 36). The sixth NAND gate 36 performs an AND logic operation on the output signals of the fourth NAND gate 24 and the fifth NAND gate 34 to generate a vertical synchronization signal for the on-screen display. Since the output signal of the fourth NAND gate 24 maintains high logic, the sixth NAND gate 36 inverts the output signal of the fifth NAND gate 34. Therefore, it has the same frequency and phase as the vertical synchronization signal V extracted from the vertical synchronization separator 4 generated from the sixth NAND gate 36. As such, during the period in which the video signal is supplied, the free running signal is blocked, and the horizontal and vertical synchronization signals separated from the video signal are synchronized with the video signal.

The horizontal synchronizing signal and the vertical synchronizing signal are used as screen display reference signals input to the microcomputer.

As described above, the synchronous signal switching circuit and method for a display device according to the present invention use the free running signal as the horizontal synchronous signal for the on-screen display while the video signal is not input, and divide the free running signal by 256. It generates a vertical sync signal for the screen display. On the other hand, in the period in which the video signal is input, the free running signal is blocked, and the horizontal sync signal and the vertical sync signal are extracted from the input video signal and used as a reference signal for the on-screen display. Accordingly, according to the synchronization signal switching circuit and method for the display device according to the present invention, the on-screen display is possible regardless of whether or not the video signal is input. In addition, since three lines for supplying the horizontal synchronizing signal, the vertical synchronizing signal, and the ground voltage GND connected between the liquid crystal display panel and the microcomputer are not required, an on-screen display is possible regardless of the manufacturer of the liquid crystal display panel.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (11)

Horizontal synchronous separating means for extracting a horizontal synchronizing signal from an input video signal; Vertical synchronization separating means for extracting a vertical synchronization signal from the video signal; Free running signal generating means for generating a free running signal of a predetermined frequency; The horizontal and vertical synchronizing signals are output by cutting off the free running signal during the period in which the video signal is supplied, and the second horizontal synchronizing signal and the second horizontal synchronizing signal are used by using the free running signal during a period other than the image signal supply period. And a logic means for generating a vertical synchronizing signal. The method of claim 1, And the horizontal synchronizing signal and the vertical synchronizing signal outputted from the horizontal synchronizing separating means and the vertical synchronizing separating means maintain a low logic in a period other than the video signal supply period. The method of claim 1, The logic means includes a first phase inverter for phase inverting the horizontal synchronizing signal; A first low frequency filter for low frequency filtering the output signal of the first phase inverter and converting the signal into an integrated wave; A first negative AND product for negative AND operation of the free running signal and the output signal of the first low frequency filter; A second phase inverter for phase inverting an output signal of the first low frequency filter; A second negative AND product for negative AND operation of the output signal of the second phase inverter and the horizontal synchronization signal; Negative AND operation of the output signals of the first and second negative AND products outputs the horizontal synchronization signal during the period when the video signal is supplied, and the second non-period during the period when the video signal is supplied. And a third negative AND product for outputting a horizontal synchronizing signal. The method of claim 3, wherein The first low frequency filter converts an output signal of the first phase inverter into an integrated wave having a maximum level less than or equal to a threshold voltage of the first negative AND product during a period when the image signal is supplied. Synchronous signal switching circuit for display device. The method of claim 1, The logic means may include: a divider for dividing the free running signal into a predetermined divided value; A phase modulator for reducing the duty ratio of the output signal of the divider; A third phase inverter for phase inverting the vertical synchronization signal; A second low frequency filter for low frequency filtering the output signal of the third phase inverter and converting the integrated signal into an integrated wave; A fourth negative AND product for negative AND operation of the output signal of the phase modulator and the output signal of the second low frequency filter; A fourth phase inverter for phase inverting the output signal of the second low frequency filter; A fifth negative AND product for negative AND operation of the output signal of the fourth phase inverter and the vertical synchronization signal; Negative AND operation of the output signals of the fourth and fifth negative AND products outputs the vertical synchronization signal during a period when the video signal is supplied, and the second second period during a period other than the period during which the video signal is supplied. And a sixth negative AND product for outputting the vertical synchronization signal. The method of claim 5, And the divider divides the free running signal by 256. The method of claim 5, And said phase modulator is a one-shot multivibrator. The method of claim 5, The second low frequency filter converts an output signal of the third phase inverter into an integrated wave having a maximum level less than or equal to a threshold voltage of the fourth negative AND product during a period when the image signal is supplied. Synchronous signal switching circuit for display device. Generating a free running signal having a predetermined frequency; Blocking the free running signal and outputting horizontal and vertical synchronization signals included in the video signal while a video signal is supplied; And generating a second horizontal synchronizing signal and a second vertical synchronizing signal using the free running signal during a period other than the video signal supply period. The method of claim 9, The generating of the second vertical synchronizing signal further includes dividing the free running signal into a predetermined division value. The method of claim 10, And reducing the duty ratio of the divided signals.