JPH10117298A - Synchronous processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the write control of the stable video data by replacing such an unstable horizontal synchronization signal, approximate to a vertical synchronization signal as a special reproduction video signal of a VTR with a stable free run horizontal synchronization signal and then switching this signal to a regular horizontal synchronization signal after the said replacement period. SOLUTION: An equivalent pulse detection circuit 8 detects the presence or absence of an equivalent pulse in a 1H to 2H period, after a vertical synchronizing signal VD starts. When no equivalent pulse is detected, a switching period generation control signal is produced and supplied to a switching period generation circuit 9 to produce the switching signals for a fixed period (e.g. a period including VD through 10). A free-run horizontal synchronization signal generation circuit 7 serves as a self-exciting pulse oscillator, which can be triggered externally and is usually triggered by the signal VD. When no trigger pulse is available, the circuit 7 performs the self-oscillation almost in a horizontal signal cycle. The number of output horizontal synchronization signals HD produced after the signal VD starts are counted by a counter of a vertical write start signal generation circuit 5. Then a control signal is produced for the start of a vertical writing operation of a video memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for digitally processing a video signal and generating a synchronization signal used for temporarily storing the digital data in a video memory.

[0002]

2. Description of the Related Art In a matrix drive type display device, a video signal is digitally processed, and digital data of the video is temporarily written to a video memory. Of the write control signals for the video memory, the write start timing in the vertical direction is determined by counting the number of HDs from the start of VD. In FIG. 3, an input video signal 1 is separated into HD3 and VD4 by a sync separation circuit 2 and output respectively. The vertical write start timing of the video memory is
As shown in FIG. 4A, when the HD is counted from the VD and reaches a predetermined number, the HD is generated by a vertical write start signal generating circuit 5 which outputs a vertical write start signal. The vertical writing start signal 6 determines the vertical start position of the display screen. Of the input video signals, in many cases of special reproduction signals such as VTRs, the HD near the vertical synchronization is disturbed by noise or lacks an equivalent pulse (b) in the vertical synchronization period. At this time, the number of HDs from the VD decreases or fluctuates, and the phase of the vertical writing start signal is shifted, thereby causing a drop or a vertical vibration near the start position of the display screen on the screen.

[0003]

An object of the present invention is to provide a VT
An object of the present invention is to generate a stable synchronization signal with respect to a synchronization signal such as a missing HD or an equivalent pulse disturbed by noise near the VD such as an R special reproduction signal.

[0004]

The present invention detects the presence or absence of an equivalent pulse within a predetermined time from the start point of VD of an input signal. If there is no equivalent pulse, outputs an output horizontal synchronization signal for a predetermined period of time. , A stable vertical write start signal is generated.

[0005]

DETAILED DESCRIPTION OF THE INVENTION A video signal is processed by digital signal processing.
A synchronizing signal processing circuit of a device for temporarily storing the digital data in a video memory, a synchronizing separation circuit for separating VD and HD from an input video signal, and a horizontal equivalent in a VD period from the VD and the input composite synchronizing signal. An equivalent pulse detection circuit for detecting the presence / absence of a pulse; and a free-run horizontal synchronizing signal generator for synchronizing with the HD and generating a free-run horizontal synchronizing signal (hereinafter referred to as FHD) substantially equal to the frequency of the horizontal synchronizing signal even when the HD is absent. A switching period generating circuit for generating a control signal for switching an input horizontal synchronizing signal when there is no equivalent pulse;
A synchronous switching circuit for switching between D and FHD.

[0006]

FIG. 1 shows an embodiment of the present invention. 2 is a sync separation circuit for synchronizing and separating VD4 and HD3 from the input composite sync signal 1. 5 is a vertical write start signal generating circuit for generating a vertical write start control signal 6 for the video memory. A synchronizing signal generating circuit, 8 an equivalent pulse detecting circuit for detecting the presence or absence of an equivalent pulse in the VD period, 9 a switching period generating circuit for generating a switching control signal with FHD when there is no equivalent pulse, and 10 a switching control signal By H
This is a synchronization switching circuit that switches between D and FHD and outputs the horizontal synchronization signal 11.

The operation will be described below with reference to FIG. The input video signal 1 is synchronized and separated by a synchronization separation circuit 2.
(A) is a partially enlarged view near VD. In the VD period 20, there are equivalent pulses at 1 / 2H intervals. In an input video signal for special reproduction or the like from a VTR, as shown in (b), there is no equivalent pulse in the VD period, or there are many synchronization signals disturbed by noise. In the prior art, the write start position of the video data fluctuates directly due to lack of HD. In this embodiment, V
The equivalent pulse detection circuit 8 detects the presence or absence of the equivalent pulse during a period of 1 to 2 H from the start of D. When there is no pulse, a switching period generation control signal is issued. The control signal is supplied to a switching period generation circuit 9 for a predetermined period (for example, VD
(10H period). The free-run horizontal synchronizing signal generating circuit is a self-excited pulse oscillator capable of external triggering and is normally triggered by VD. However, when there is no trigger, self-excited oscillation is performed at substantially the horizontal synchronizing signal cycle.

The output horizontal synchronizing signal is normally output as HD. When the equivalent pulse detecting circuit 8 detects no equivalent pulse, the synchronizing switching circuit 10 switches to FHD. The number of the output horizontal synchronizing signals from the start of VD is measured by a counter in the vertical write start signal generating circuit 5, and a control signal for starting the vertical write of the video memory is generated.

[0009]

The present invention is embodied in the form described above and has the following effects.

A synchronization separation circuit for separating VD and HD from the input video signal, an equivalent pulse detection circuit for detecting the presence or absence of an equivalent pulse in the VD period from VD and the input composite synchronization signal,
A free-run horizontal synchronizing signal generating circuit that generates an FHD substantially equal to the frequency of the horizontal synchronizing signal even when there is no HD, and a switch that generates a control signal for switching the output horizontal synchronizing signal when there is no equivalent pulse It is composed of a period generating circuit and a synchronous switching circuit for switching between HD and FHD by the switching control signal. As a result, an unstable HD near the VD, such as a special playback video signal of a VTR, is replaced with a stable FHD, and immediately after the end of the period, switching to a regular HD is performed to perform stable video data writing control. Comes out.

[0011]

[Brief description of the drawings]

FIG. 1 is a block diagram of a main part of an embodiment of a synchronization processing circuit according to the present invention.

FIG. 2 is an enlarged view of a vertical synchronization signal section of the embodiment according to the present invention.

FIG. 3 is a block diagram of a main part of a conventional synchronous processing circuit.

FIG. 4 is an enlarged view of a vertical synchronization signal section of a synchronization processing circuit according to the related art.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 input composite synchronization signal 2 synchronization separation circuit 3 HD 4 VD 5 vertical write start signal generation circuit 6 write start control signal 7 free-run horizontal synchronization signal generation circuit 8 equivalent pulse detection circuit 9 switching period generation circuit 10 synchronization switching circuit 20 Output horizontal synchronization signal 21 VD period 22 Equivalent pulse detection period

Claims (3)

[Claims] A synchronous processing circuit used for digitally processing a video signal and temporarily storing the digital data in a video memory, wherein a horizontal synchronizing signal (hereinafter referred to as HD) is converted from an input composite synchronizing signal. Vertical sync signal (hereinafter V
D), an equivalent pulse detection circuit for detecting the presence or absence of an equivalent pulse in a VD period from the VD and the input composite synchronization signal, and an HD synchronized with the HD.
A free-run horizontal synchronizing signal generating circuit that generates a free-run horizontal synchronizing signal (hereinafter referred to as FHD) substantially equal to the frequency of the horizontal synchronizing signal, the HD when there is the equivalent pulse, and the FHD when there is no equivalent pulse. A switching period generating circuit for generating a control signal for switching for a predetermined period and an output horizontal synchronizing signal by the switching control signal, HD is output when there is an equivalent pulse in the VD portion of the input video signal, and FHD is output when there is no equivalent pulse. A synchronization processing circuit comprising a synchronization switching circuit. 2. A synchronizing signal processing circuit of a device for digitally processing a video signal and temporarily storing the digital data in a video memory.
A synchronous separation circuit that separates the horizontal synchronization signal from the VD and the input composite synchronization signal, and an equivalent pulse detection circuit that detects the presence or absence of an equivalent pulse during the VD period. A free-run horizontal synchronizing signal generating circuit for generating substantially the same FHD, a switching period generating circuit for generating a control signal for switching the HD when the equivalent pulse is present and switching to the FHD when the equivalent pulse is not present, and the switching control signal A synchronous switching circuit for switching and outputting HD when there is an equivalent pulse in the VD portion of the input video signal as an output horizontal synchronizing signal and FHD when there is no equivalent pulse as the output horizontal synchronizing signal;
A vertical write start signal generating circuit for measuring the number of the output horizontal synchronizing signals from the start of D and outputting a vertical write start position control signal for the video memory which is output at a timing equal to a predetermined number. A synchronous processing circuit comprising: 3. The free-running horizontal synchronizing signal generating circuit is a resettable clock counting counter, and the VD
2. A synchronous processing circuit according to claim 1, wherein the reset signal is used as a reset signal, and an output at the time when the count reaches substantially one horizontal period can be reset.