KR20010011003A - Manufacturing method for semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent parasitic capacitance from high dielectric constant and stress of a wafer and to improve the reliability of device's operation and the yield rate of the process by use of an SiC layer. CONSTITUTION: An oxide layer(11) is formed on a semiconductor(10) and a gate oxide layer(12) is formed on the oxide layer(11). A gate electrode(13), overlapped on the pattern of a mask SiC layer(21), is formed on the gate oxide layer(13). A spacer(22) which consists of an SiC is formed on the gate electrode(13) and the sidewell of the Sic layer. An interlayer dielectric(18) is formed an entire surface of the structure and planized the upper portion.

Description

Manufacturing method for semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, in particular, has a lower stress and dielectric constant than an nitride film as an etch barrier layer in a self align contact (hereinafter referred to as SAC) using an etching barrier layer, and an etching with an oxide film. The present invention relates to a method for fabricating a semiconductor device capable of increasing the contact formation process margin by reducing parasitic capacitance caused by stress generation or dielectric constant by using a SiC film having a large selection ratio.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology. For the formation of fine patterns, photoresist patterns of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are used in the manufacturing process of semiconductor devices. Micronization is a must.

The resolution (R) of the photoresist pattern is closely related to the material of the photoresist itself or the adhesion to the substrate, but is primarily proportional to the light source wavelength (λ) and the process variable (k) of the reduction exposure apparatus used. It is inversely proportional to the lens aperture (NA, numerical aperture) of the device.

[R = k * λ / NA, ~ R = resolution, ~ λ = wavelength of light source, NA = opening number ~]

Here, the wavelength of the light source is reduced to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of a line / space pattern. The limit is about 0.7 and 0.5 μm, respectively, and in order to form a fine pattern of 0.5 μm or less, deeper ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or 193 nm An exposure apparatus using an ArF laser as a light source should be used.

In addition to the reduction exposure apparatus, a process method may be used as a phase shift mask instead of a conventional photo mask, or a separate thin film may be formed on the wafer to improve image contrast. A tri-layer resister (hereinafter referred to as TLR) is formed by interpolating a CEL method or an intermediate layer such as spin on glass (SOG) between two photoresist layers. Method or a silicide method for selectively injecting silicon into the upper side of the photosensitive film has been developed to lower the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings has a larger design rule than the above line / space pattern. As the device becomes more integrated, the size of the contact hole and the distance between the peripheral wirings are reduced. As the aspect ratio, which is a ratio of depth, increases, highly integrated semiconductor devices having multilayer conductive wirings require accurate and strict alignment between masks in a manufacturing process to form contacts, thereby reducing process margin. .

These contact holes can be used for misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, Since the mask must be formed in consideration of factors such as registration between the masks, the process margin is further reduced to prevent high integration of the device.

These contact holes can be used for misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, The mask is formed by considering factors such as registration between the masks.

As a method of forming the contact hole as described above, there are a direct etching method, a method using a sidewall spacer, a SAC method, and the like.

In addition, the SAC method, which is designed to overcome the limitations of the lithography process in forming contact holes, can be divided into polysilicon layer, nitride film, or oxynitride film, depending on the material used as the etch barrier layer. Can be used as an etch shield.

1A and 1B are a manufacturing process diagram of a semiconductor device according to the prior art, which is an example of an EMSAC method.

First, an element isolation oxide film 11, a gate oxide film 12, a gate electrode 13, a source / drain region 15, and the like that define a predetermined substructure on the semiconductor substrate 10, for example, an active region. A MOS field effect transistor (hereinafter referred to as a MOS FET) is formed. In this case, the mask nitride layer 14 and the nitride layer 16 pattern overlap each other on the gate electrode 13, and the nitride layer spacer 17 is formed on sidewalls of the gate electrode 13, and the nitride layer spacer 17 is etched together with the nitride layer 16. It becomes a barrier.

Thereafter, an interlayer insulating film 18 is formed on the entire surface of the structure, and the upper portion of the interlayer insulating film 18 is planarized by a chemical-mechanical polishing (hereinafter referred to as CMP) method. (See FIG. 1A).

Thereafter, the semiconductor substrate 10 is formed with a photoresist pattern 19 exposing the interlayer insulating film 18 on a portion intended to be in contact with the charge storage electrode and the bit line, and then exposed by the photoresist pattern 19. The interlayer insulating film 18 is etched to expose the upper portion of the nitride film 16 pattern, and a contact hole 20 is formed to expose a predetermined portion to the contact of the semiconductor substrate 10. (See FIG. 1B).

Here, when the state of FIG. 1B is viewed as a plane, the state as shown in FIG. 2 is shown. The portion exposed by the photoresist pattern 19 has an overall T-shape, and is positioned between the four gate electrodes 13. The semiconductor substrate 10 is exposed.

Subsequently, subsequent contact plug formation and conductive wiring and contact processes are performed.

In the method of manufacturing a semiconductor device according to the prior art as described above, a nitride film is used as an etching barrier layer. When the nitride film is deposited on the entire surface, the wafer is bent due to the high stress of the nitride film, which causes a defect in a subsequent process. Since the nitride film has a dielectric constant of about 6 to 9, the parasitic capacitance is increased during the small intestine operation, which hinders the fast operation of the device.

The present invention is to solve the above problems, the object of the present invention is

The etching barrier layer in the SAC process has a smaller stress and dielectric constant than the nitride film and a SiC film having a large etching selectivity difference for the oxide film, thereby preventing defects by preventing wafer warpage and parasitic capacitor generation due to high dielectric constant. In addition, the present invention provides a method of manufacturing a semiconductor device, which can improve process yield and device operation reliability by increasing a contact process margin.

1A and 1B are manufacturing process diagrams of a semiconductor device according to the prior art.

2 is a plan view after the process of FIG. 1B;

3A and 3B illustrate a manufacturing process of a semiconductor device according to an embodiment of the present invention.

4 is a plan view after the step 3b;

5 is a sectional view of a semiconductor device according to another embodiment of the present invention.

FIG. 6 is a plan view after the FIG. 5 step; FIG.

<Explanation of symbols for main parts of drawing>

10 semiconductor substrate 11: device isolation oxide film

12 gate oxide film 13 gate electrode

14 mask myth film 15 source / drain area

16 nitride film 17 nitride film spacer

18: interlayer insulating film 19: photosensitive film pattern

20: contact hole 21; SiC film

22 SiC film spacer 24 Bit line contact hole

23 photoresist pattern for bit line contact mask

Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,

In the method of manufacturing a semiconductor device using a SAC process using an etching barrier layer,

Forming a device isolation oxide film defining an active region on the semiconductor substrate;

Forming a gate oxide film on the semiconductor substrate;

Forming a gate electrode on which the mask SiC film pattern is superimposed on the gate oxide film;

Forming a spacer of an SiC film on sidewalls of the gate electrode and the SiC film pattern;

Forming an interlayer insulating film on the entire surface of the structure and flattening the upper portion;

And forming a contact hole by removing the interlayer insulating film on the portion of the semiconductor substrate, which is supposed to be a contact.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

3A and 3B are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, which is an example of an EMSAC process using a SiC film as an etch barrier layer.

First, as shown in FIG. 1A, the device isolation oxide film 11, the gate oxide film 12, the gate electrode 13, and the source / drain regions defining the T-shaped active region on the semiconductor substrate 10 may be sequentially processed. The MOS FET of 15) is formed. Here, the mask myth film 14 pattern and the SiC film 21 pattern overlap each other on the gate electrode 13, and the SiC film spacer 22 is formed on the sidewalls of the patterns to form the semiconductor substrate 10. The mask oxide layer 14 may not be formed, and the SiC layers may be formed by chemical vapor deposition (CVD) or physical vapor deposition (hereinafter referred to as CVD). Called PVD).

Then, an interlayer insulating film 18 having its top planarized is formed on the entire surface by the CMP method. (See FIG. 3A).

Thereafter, the semiconductor substrate 10 has an interlayer photosensitive film pattern 19 exposing the interlayer insulating film 18 on the portion, which is supposed to be a contact between the charge storage electrode and the bit line, in a T-shape using a mask for defining an active region. After the insulating film 18 is formed, the interlayer insulating film 18 exposed by the photosensitive film pattern 19 is dry-etched to form a contact hole 20 exposing a predetermined portion of the semiconductor substrate 10 as a contact. do. (See Figure 3b).

Referring to the state of FIG. 3A, as shown in FIG. 4, the semiconductor substrate 10 of the detail is exposed, the photosensitive film pattern 19 is formed in a T-shape, and the SiC film 21 used as an etch barrier. You can see exposing the patterns.

FIG. 5 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention. After the process of FIG. 3A is performed in the same manner, a photosensitive film pattern 23 for a bit line contact mask is formed on the interlayer insulating film 18. The interlayer insulating film 18 exposed by the photosensitive film pattern 23 is etched to form a bit line contact hole 24 exposing the semiconductor substrate 10, which is supposed to be a bit line.

In this state, as shown in FIG. 6, two semiconductor substrates 10, which are intended as bit line contacts, are exposed, and circular contacts in which the SiC film 21 is exposed on both sides thereof are formed.

As the interlayer insulating film etching equipment, plasma sources such as HELICAL, HELICON, electron cyclotron resonance (ECR), transformer coupled plasma (TCP), mgnetic enhanced reactive ion etching (MERIE), and syrup wave plasma (SWP) are used. The contact mask for defining the area can be applied to all types such as T-shape, I-shape and Z-shape, and the SiC film of the present invention can be used not only for EMSAC but also for buried & space SAC or capping SAC process. .

As described above, the semiconductor device manufacturing method according to the present invention uses a SiC film having a relatively low stress and dielectric constant as the etch barrier layer in the SAC process using the etch barrier layer. No defects such as wafer warpage due to stress, and low dielectric constant, low parasitic capacitance during operation of the device, does not interfere with the fast operation of the device, and the etching selectivity difference with the oxide film is large, resulting in a contact hole etching process margin. There is an advantage that can be increased to improve the process yield and the reliability of device operation.

Claims (7)

In the method of manufacturing a semiconductor device using a self-aligned contact process using an etching barrier layer, Forming a device isolation oxide film defining an active region on the semiconductor substrate; Forming a gate oxide film on the semiconductor substrate; Forming a gate electrode on which the mask SiC film pattern is superimposed on the gate oxide film; Forming a spacer of an SiC film on sidewalls of the gate electrode and the SiC film pattern; Forming an interlayer insulating film on the entire surface of the structure and flattening the upper portion; And forming a contact hole by removing the interlayer insulating film on the portion of the semiconductor substrate which is supposed to be a contact. The method of claim 1, And forming a mask oxide film pattern between the gate electrode and the mask SiC film pattern. The method of claim 1, The method of manufacturing a semiconductor device, wherein the SiC film and the SiC film spacer are formed by CVD or PVD. The method of claim 1, The interlayer insulating film is formed of an oxide film, and the upper part is planarized by a CMP method. The method of claim 1, A method of manufacturing a semiconductor device, characterized in that the interlayer insulating film exposed by the photoresist pattern used in the contact etching process is any one of a T-shape, an I-shape, a Z-shape, or a hole. The method of claim 1, And manufacturing the contact hole etching process using any one of HELICAL, HELICON, ECR, TCP, MERIE, or SWP. The method of claim 1, Wherein the contact etching process is one of an EMSAC, a buried & space SAC, or a capping SAC process.