KR20010010436A - Method for forming contact of semiconductor devices and their structure - Google Patents

Abstract

PURPOSE: A method of forming a contact and a structure of a semiconductor device are to increase a contact area between a via or a contact plug and a metal interconnect and to improve contact properties, thereby reducing a mutual contact resistance therebetween. CONSTITUTION: A method of forming a contact comprises the steps of: depositing the first conductive layer(210) and an insulation layer(214) on a semiconductor substrate in this order; etching the insulating layer to form a via hole; filling the via hole with the second conductive layer to form a via(220); etching an upper portion of the insulating layer to protrude the via; and depositing the third conductive layer(224) on the insulating layer and the via. Further, a structure of a semiconductor device comprises: the first conductive layer; the insulating layer formed on the first conductive layer; the third conductive layer formed on the insulation layer; and the via adapted to be electrically connected to the first and the third conductive layer passing through the insulation layer, wherein an upper and a lower portion of the via is inserted into the first and the third conductive layer, respectively.

Description

TECHNICAL FIELD OF THE CONTACT FORMATION AND CONSTRUCTION OF A SEMICONDUCTOR DEVICE

The present invention relates to a structure and a manufacturing method of a semiconductor device, and more particularly to a structure and a contact forming method of a semiconductor device.

As semiconductor devices become more integrated, integrated circuits become more complex and more and more wires connect devices with each other. In addition, as the size of each device is reduced, the distance between the wirings and the wirings is gradually decreasing. Therefore, the wiring area occupies several ten percent in the semiconductor chip. Reducing the pattern width of the wiring in accordance with the size reduction of the device has limitations due to problems such as current capacity and wiring resistance. Therefore, a multilayer wiring structure has been proposed and applied in a single layer wiring structure.

In the multilayer wiring structure, a wiring is formed by depositing a layer of a metal film on a substrate on which an element is formed, and then depositing another layer of metal film after forming an interlayer insulating film. In this way, two-layer structures and further three-layer structures are becoming increasingly multilayered.

As the devices are connected to each other in a multilayer wiring structure, an important point is contacts between wirings. The contact between the element and the wiring is realized by forming a contact plug by drilling a contact hole in the interlayer insulating film and filling it with a conductive film. Similarly, the contact between the metal wiring and the metal wiring is realized by forming a via by drilling a via hole in the interlayer insulating film and filling it with a conductive film.

When vias or contact plugs are formed, there are some problems with the contact between the contact plug and the device, vias and metallization, such as junction spiking, silicon nodule, contact resistance and contact failure. have. In order to overcome this problem, a barrier metal film is deposited on the contact interface. The barrier metal film improves contact resistance, suppresses reaction between dissimilar materials at the interface, and facilitates adhesion between dissimilar materials.

1 is a cross-sectional view showing a problem of contact formation of a conventional semiconductor device.

Referring to FIG. 1, a lower metal wiring 110 is formed on a semiconductor substrate. An interlayer insulating layer 112 is formed on the lower metal wiring 110. Vias 114 are formed in the interlayer insulating layer 112 to contact the lower metal wires 110. An upper metal line 116 is formed on the interlayer insulating layer 112 to contact the via 114.

The contact between the via 114 and the metal wires 110 and 116 is a one-dimensional cross-sectional contact. As a result, the contact area and contact characteristics between the via 114 and the metal wires 110 and 116 are inferior. Accordingly, contact resistance between the via 114 and the metal wires 110 and 116 may increase, resulting in excessive power consumption and heat generation, resulting in a failure.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and an object thereof is to provide a structure of a semiconductor device and a method for forming a contact that reduce contact resistance at a contact end when a contact plug or a via is connected with a metal wire.

1 is a cross-sectional view showing a problem of contact formation of a conventional semiconductor device;

2 is a cross-sectional view showing a structure of a semiconductor device according to an embodiment of the present invention;

3A through 3E are cross-sectional views sequentially illustrating a method for forming a contact in a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

210: lower metal wiring 212: first barrier metal film

214: interlayer insulating film 216: via hole

218: second barrier metal film 220: via

222: third barrier metal film 224: upper metal wiring

According to the present invention for achieving the above object, a structure of a semiconductor device includes a first conductive film formed on a semiconductor substrate; An insulating film formed on the first conductive film 210; A second conductive film formed on the insulating film; And vias formed through the insulating layer to be electrically connected to the first and second conductive layers, wherein upper and lower portions of the vias are inserted into the first and second conductive layers.

In a preferred embodiment of this structure, a barrier metal film is further included between the via and the first conductive film.

In a preferred embodiment of this structure, a barrier metal film is further included between the via and the second conductive film.

In a preferred embodiment of this structure, a barrier metal film is further included between the via and the insulating film.

In a preferred embodiment of this structure, the barrier metal film is one or a combination of TiN, TiW and Ti.

According to the present invention for achieving the above object, in the method for forming a contact of a semiconductor device, a first conductive film and an insulating film are sequentially deposited on a semiconductor substrate. The insulating layer is etched to form via holes. The via hole is filled with a second conductive layer to form a via. An upper portion of the insulating layer is etched to protrude the via. A third conductive film is deposited on the insulating film and the via.

In a preferred embodiment of the method, the method further includes etching a portion of the first conductive film to extend the via hole into the first conductive film.

In a preferred embodiment of the method, the method further includes forming a first barrier metal film between the first conductive film and the insulating film.

In a preferred embodiment of the method, the method further includes forming a second barrier metal film on the inner wall of the via hole.

In a preferred embodiment of the method, the method further comprises forming a third barrier metal film between the via and the insulating film and the third conductive film.

In a preferred embodiment of this method, the insulating film etching is performed in the range of 100-1500 Å thickness.

In a preferred embodiment of this method, the first, second and third barrier metal films are one or a combination of TiN, TiW and Ti, each formed in a thickness range of 100-1000 kPa.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2 and 3.

2 shows a structure of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2, a lower metal wiring 210 is formed on a semiconductor substrate, and a first barrier metal film 212 is formed thereon. An interlayer insulating layer 214 is deposited on the first barrier metal layer 212, and a via 220 formed as a second conductive layer is formed therein. A second barrier metal layer 218 is formed on the outer wall of the via 220. A third conductive layer 224 is formed on the via 220 and the interlayer insulating layer 214. The via 220 has a structure inserted into the first and third conductive layers. A third barrier conductive layer 222 is formed between the via 220 and the third conductive layer.

Referring to the method of forming a contact of a semiconductor device having a structure as described above is as follows.

In the contact forming method of the novel semiconductor device of the present invention, an interlayer insulating film is deposited on the lower metal wiring. Via holes are formed in the interlayer insulating film. The via hole is filled with a conductive film to form a via. The upper portion of the interlayer insulating layer is partially etched. A barrier metal film is formed on the entire surface of the substrate. An upper metal wiring is formed on the barrier metal film. As a result, the contact resistance between the via and the upper metal wiring is reduced.

3A through 3E are cross-sectional views sequentially illustrating a method for forming a contact between semiconductor devices according to an embodiment of the present invention.

Referring to FIG. 3A, a lower metal wiring 210 is formed on a semiconductor substrate. As the lower metal wire 210, aluminum (Al) is generally used. The aluminum has the advantages of excellent adhesion to silicon (Si) or silicon oxide (SiO ₂ ), ohmic resistance, and relatively low electrical resistivity. However, the aluminum has a disadvantage of low melting point (670 ° C.) and phenomena such as electro-migration, stress-migration, silicon nodule, and junction spiking. . In order to overcome this disadvantage, the first barrier metal film 212 is deposited on the lower metal wire 210 in the thickness range of 100-1000 Å. The first barrier metal film 212 is generally formed of TiN, and may also be formed of TiW and Ti. The barrier metal film should have a low and stable resistance value, low stress, low sheet resistance and stability at high temperatures. In a preferred embodiment of the present invention TiN is used in which Ti and N are composed of a chemical stoichiometric ratio of 1: 1. The TiN has a relatively low resistivity of 25-180 μΩ-cm.

An interlayer insulating film 214 is deposited on the first barrier metal film 212. The interlayer insulating layer 214 is generally formed of a silicon oxide film (SiO ₂ ), but may be formed by chemical vapor deposition (CVD), reflow, or HDP (High Density Plasma), or USG (Undoped Silicate Glass), SiON, or BPSG. (Boron Phosphorus Silicate Glass), SiN, HDP oxide film or PSG (Phosphorus Silicate Glass) may be formed. The thickness of the interlayer insulating layer 214 should be deposited sufficiently thick in consideration of the short and the step coverage between the wirings.

3B, a photoresist film (not shown) is deposited on the interlayer insulating film 212. The photoresist layer is patterned to form a via hole etching mask. The interlayer insulating layer 214 and the first barrier metal layer 212 are etched to expose the lower metal wiring 212 by using the via hole etching mask. At this time, it is sufficiently etched so that the lower metal wiring 210 is recessed. Alternatively, the interlayer insulating film 214 and the first barrier metal film 212 may be etched to expose only the upper surface of the lower metal wire 210. As a result, a via hole 216 is formed in the interlayer insulating layer 214 and the lower metal wiring 210.

As shown in FIG. 3C, the second barrier metal film 218 is deposited on the entire surface of the substrate, and the second barrier metal film 218 is deposited on the inner wall of the via hole 216. The second barrier metal film 218 is formed of the same material as the first barrier metal film 212 in a thickness range of 100-1000 Å. A second conductive layer 220 is deposited on the interlayer insulating layer 214 to fill the via hole 216. The second conductive layer 220 is formed of tungsten (W) by LPCVD (tungsten, W), chemical vapor deposition (CVD), or silicide by sputtering. The tungsten has a low electrical resistivity of 5-10 μΩ-cm and a high melting point (3410 ° C.). The second conductive layer 220 and the second barrier metal layer 218 are planarized and etched to expose the upper surface of the interlayer insulating layer 214. The planarization etching process is performed through a chemical mechanical polishing (CMP) method or an etch back method. As a result, vias 220 are formed in the interlayer insulating layer 214.

Referring to FIG. 3D, a portion of the upper surface of the interlayer insulating layer 214 is etched to expose a portion of the upper portion of the via 220. The etching process is a wet etching using a hydrofluoric acid (HF) or phosphoric acid (H ₃ PO ₄ ) solution. At this time, the depth that the interlayer insulating film 214 is etched is about 100-1500 kPa.

Referring to FIG. 3E, a third barrier metal layer 222 is deposited on the via 220 and the interlayer insulating layer 214. The third barrier metal film 222 is the same material as the first barrier metal film 212 and is formed to have a thickness in the range of 100-1000 Å. An upper metal line 224 is formed on the third barrier metal layer 222. Since the vias 220 are formed to protrude beyond the interlayer insulating layer 214 and are connected to the upper metal wires 224, the contact area between the vias 220 and the upper metal wires 224 may be increased and contacted. Characteristics are improved.

In another embodiment of the present invention, a case in which a semiconductor device (for example, a transistor) is contacted with a contact plug and connected to an upper metal wire instead of the lower metal wire may be considered.

In the above, the method of forming the via contact according to the present invention is illustrated according to the above description and the drawings, but this is merely an example, and various changes and modifications can be made without departing from the technical spirit of the present invention. to be.

The present invention has the effect of reducing the contact resistance of each other by increasing the contact area of the via or contact plug and the metal wiring and improving the contact characteristics.

Claims (11)

Sequentially depositing a first conductive film and an insulating film (210, 214) on the semiconductor substrate; Etching the insulating layer 214 to form a via hole 216; Filling the via hole 216 with a second conductive layer 220 to form a via 220; Etching the upper portion of the insulating layer 214 so that the vias 220 protrude; Depositing a third conductive film (224) on the insulating film (214) and via (220). The method of claim 1, And etching the portion of the first conductive layer (210) to extend the via hole (216) into the first conductive layer (210). The method of claim 1, And forming a first barrier metal film (212) between the first conductive film (210) and the insulating film (214). The method of claim 1, And forming a second barrier metal film (218) on an inner wall of the via hole (226). The method of claim 1, And forming a third barrier metal film (222) between the via (220) and the insulating film (214) and the third conductive film (224). The method of claim 1, And etching the insulating film (214) in a thickness range of 100-1500 kV. In the structure of a semiconductor device, A first conductive film 210; An insulating film 214 formed on the first conductive film 210; A second conductive film 224 formed on the insulating film 214; A via (220) formed through the insulating film (214) to be electrically connected to the first and second conductive films (210, 224); The upper and lower portions of the vias 220 are inserted into the first and second conductive layers 210 and 224. The method of claim 7, wherein And a barrier metal film (218) between the via (220) and the first conductive film (210). The method of claim 7, wherein And a barrier metal film (222) between the via (220) and the second conductive film (224). The method of claim 7, wherein And further comprising a barrier metal film (218) between the via (220) and the insulating film (214). The method according to claim 8 or 9 or 10, And the barrier metal film (218, 222) is one or a combination of TiN, TiW, and Ti.