JP4214922B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device in which an element formation region in a surface layer portion of a semiconductor substrate is divided by a buried trench.

  In a semiconductor device in which a large number of elements are formed, in order to prevent mutual interference between elements formed on the same semiconductor substrate, the element formation region is formed with a plurality of elements by using isolation isolation using a buried trench or PN junction isolation. It is divided into areas. Insulation isolation by a buried trench enables more reliable isolation between element formation regions in a surface layer portion of a semiconductor substrate divided into a plurality of parts, as compared with PN junction isolation.

  A cap insulating film that covers the buried trench is usually formed on the buried trench. In a semiconductor device using a single crystal silicon substrate, the buried trench is generally formed of a sidewall oxide film and buried polycrystalline silicon, and the cap insulating film is formed by thermally oxidizing the surface of the buried polycrystalline silicon.

  As described above, in the semiconductor device in which the element formation region in the surface layer portion of the semiconductor substrate is divided by the buried trench, the lower layer wiring connecting the divided element formation regions through the field oxide film straddles the buried trench. Many are formed. Further, an upper layer wiring connected to the lower layer wiring is formed through the interlayer insulating film. Normally, n-conductivity type polycrystalline silicon (poly-Si) is used for the lower layer wiring, and aluminum (Al) is used for the upper layer wiring.

  FIG. 11 is a plan view schematically showing the periphery of the buried trench 2 in the conventional semiconductor device 90.

  In the conventional semiconductor device 90, the element formation region of the Si substrate 1 is divided into two element formation regions 1 a and 1 b by the buried trench 2. The contact C1 between the lower layer wiring 4 and the upper layer wiring 6 in the semiconductor device 90 is not flat on the surface of the buried trench 2 and is prone to problems such as spikes and voids. Placed inside. In addition, if an element is disposed immediately below the contact C1, a problem is likely to occur in the element when the contact C1 is formed. For this reason, the region surrounded by the alternate long and short dash line DS in the drawing around the contact C1 is a dead space in which elements cannot be formed, which hinders the increase in the degree of integration of the semiconductor device 90.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a high degree of integration while an element forming region is reliably insulated and isolated by a buried trench.

According to the first aspect of the present invention, an element formation region in a surface layer portion of a semiconductor substrate made of single crystal silicon includes a sidewall oxide film of a trench formed in the surface layer portion and a buried polycrystalline silicon embedded in the trench. by isolation by comprising embedding the trench from being divided into a plurality of element formation regions, through said field oxide film formed on a semiconductor substrate, a lower layer wiring connected to the divided element formation region is formed, an interlayer through the insulating film, the upper layer wiring for connecting the lower wiring is formed, the contact of the lower interconnect and the upper interconnect, the embedding surface of the buried polycrystalline silicon formed on the trench is thermally oxidized form in the semiconductor device is formed by being disposed on the cap insulating film to be the surface of the cap insulating film, you immediately above the buried polycrystalline silicon Has a recess Te, over the lowermost point of the recess, the contact is characterized by comprising disposed.

In the semiconductor device, since the contact of the lower layer wiring and the upper layer wiring is arranged on the cap insulating film formed on the buried trench, the dead space associated with the arrangement of the existing contact in the element formation region, No longer exists. Therefore, the semiconductor device can be a semiconductor device having a high degree of integration while the element forming region is reliably insulated and separated by the buried trench.
The semiconductor device having the buried trench structure is a semiconductor device that can be easily manufactured by a general semiconductor manufacturing technique. Accordingly, the semiconductor device can be an inexpensive semiconductor device in which the element formation region is reliably insulated and separated and has a high degree of integration.
Further, depending on the manufacturing process, a recess is easily formed on the surface of the cap insulating film immediately above the buried polycrystalline silicon. Even when the surface of the cap insulating film is not flat as described above, by arranging the contact so as to cover the lowest point of the depression as described above, the angle formed by the side wall of the contact hole with respect to the lower layer wiring is increased. , 90 ° or more (forward taper). As a result, it is possible to prevent deterioration of the coverage of the upper layer wiring due to the angle formed by the contact hole side wall with respect to the lower layer wiring being smaller than 90 ° (reverse taper), and the occurrence of problems such as spikes and voids. Can be suppressed. Therefore, the semiconductor device is an inexpensive and highly integrated semiconductor device in which contacts are arranged on the cap insulating film without performing any special treatment on the surface of the cap insulating film, and contacts due to spikes, voids, etc. A semiconductor device having good electrical characteristics free from increased resistance due to defects can be obtained.

3. The semiconductor device according to claim 2 , wherein an element formation region in a surface layer portion of a semiconductor substrate made of single crystal silicon includes a sidewall oxide film of a trench formed in the surface layer portion and a buried polycrystalline silicon embedded in the trench. Insulating isolation by a buried trench consisting of: and divided into a plurality of element formation regions, and via a field oxide film formed on the semiconductor substrate, a lower layer wiring connected to the divided element formation region is formed, An upper layer wiring connected to the lower layer wiring is formed through an interlayer insulating film, and the contact between the lower layer wiring and the upper layer wiring thermally oxidizes the surface of the buried polycrystalline silicon formed on the buried trench. in the semiconductor device in which is disposed on the cap insulating film formed, the surface of the cap insulating film, smell immediately above the side wall oxide film Has a constricted portion, with the exception of the constricted portion, the contact is characterized by comprising disposed directly above the buried polycrystalline silicon.

  Depending on the manufacturing process, a constricted portion is easily formed on the surface of the cap insulating film immediately above the sidewall oxide film of the trench. Even when the surface of the cap insulating film is not flat as described above, the contact of the upper layer wiring above the constricted portion can be obtained by arranging the contact directly on the buried polycrystalline silicon except for the constricted portion as described above. Deterioration can be prevented and the occurrence of problems such as spikes and voids can be suppressed. Therefore, the semiconductor device is also an inexpensive and highly integrated semiconductor device in which contacts are arranged on the cap insulating film without performing any special treatment on the surface of the cap insulating film, and contacts due to spikes, voids, etc. A semiconductor device having good electrical characteristics free from an increase in resistance due to defects can be obtained.

According to a third aspect of the present invention, the semiconductor device is a semiconductor device in which the lower layer wiring is made of n conductivity type polycrystalline silicon (poly Si) and the upper layer wiring is made of aluminum (Al). it can.

  As an inexpensive wiring material having good electrical characteristics, n-conductivity type poly-Si is often used for the lower layer wiring, Al is used for the upper layer wiring, and semiconductor devices are often used. When the n-conductivity type poly-Si and Al are in direct contact, Al diffuses into the n-conductivity type poly-Si and the poly-Si is easily changed to the p-conductivity type, or Al alloy spikes are easily formed in the poly-Si. For this reason, generally, a barrier metal is deposited after the formation of the contact hole, and thereafter, Al which is an upper layer wiring is deposited. Since the barrier metal has a small film thickness, if the reverse taper of the side wall of the contact hole occurs or a constriction exists on the surface of the cap insulating film in the contact hole, the coverage deteriorates. However, in the semiconductor device having the lower wiring made of n-conductivity type poly-Si and the upper wiring made of Al, the deterioration of the barrier metal coverage can be prevented, and the semiconductor device should be inexpensive and have good electrical characteristics. Can do.

The invention described in claim 4 is characterized in that a barrier metal is laminated on the lower layer wiring, and the upper layer wiring is connected to the lower layer wiring through the barrier metal.

  According to this, by forming the barrier metal on the lower layer wiring before forming the interlayer insulating film, the coverage of the barrier metal with respect to the lower layer wiring is improved. As a result, a semiconductor device having good electrical characteristics can be obtained.

As described in claim 5 , for example, titanium silicide (TiSi) or tungsten silicide (WSi) can be used as the barrier metal.

  The barrier metal made of the above material has good barrier performance against the lower layer wiring made of n-conducting type poly-Si and the upper layer wiring made of Al, and it is formed on the lower layer wiring by a general semiconductor manufacturing technology. It can be formed at low cost. Therefore, a semiconductor device using the barrier metal can be an inexpensive semiconductor device having favorable electrical characteristics.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a plan view schematically showing the periphery of a buried trench 20 in a semiconductor device 100 of the present invention. FIG. 2 is a cross-sectional view taken along the line AA in the semiconductor device 100 of FIG. 1 and shows the cross-sectional structure of the buried trench 20 in more detail. In the semiconductor device 100 shown in FIGS. 1 and 2, the same components as those in the conventional semiconductor device 90 shown in FIG.

  As shown in FIGS. 1 and 2, in the semiconductor device 100, as in the conventional semiconductor device 90 shown in FIG. 11, two element formation regions in the surface layer portion of the semiconductor substrate 1 are separated by insulating isolation by the buried trench 20. It is divided into element formation regions 1a and 1b. On the other hand, as shown in FIG. 1, the contact C <b> 2 of the lower layer wiring 4 and the upper layer wiring 6 in the semiconductor device 100 is arranged immediately above the buried trench 20, unlike the conventional semiconductor device 90. As shown in FIG. 2, LOCOS (LOCal Oxidation of Silicon) 3 is formed on the element formation regions 1 a and 1 b around the buried trench 20.

  The semiconductor substrate 1 in the semiconductor device 100 is made of single crystal silicon. The buried trench 20 includes a trench side wall oxide film 20 a formed in the surface layer portion of the silicon substrate 1 and a buried polycrystalline silicon 20 b buried in the trench. Further, the surface of the buried polycrystalline silicon 20b is thermally oxidized, and a cap insulating film 30 that covers the buried trench 20 is formed on the buried trench 20 so as to be connected to the LOCOS 3. The buried trench structure can be easily manufactured by using a general semiconductor manufacturing technique.

  In the semiconductor device 100, the lower layer wiring 4 is formed on the field oxide film (not shown), the LOCOS 3, and the cap insulating film 30. The lower layer wiring 4 is connected to the divided element formation regions 1 a and 1 b through a field oxide film formed on the semiconductor substrate 1. For the lower layer wiring 4, n-conducting type polycrystalline silicon (poly Si) is used which is inexpensive and has good electrical characteristics. An interlayer insulating film 5 and an upper layer wiring 6 are formed on the lower layer wiring 4, and the upper layer wiring 6 is connected to the lower layer wiring 4 through a contact hole 5 h formed in the interlayer insulating film 5. For the interlayer insulating film 5, BPSG (Boron-doped Phospho-Silicate Glass) is used. The upper wiring 6 is made of aluminum (Al) which is inexpensive and has good electrical characteristics. When the n-conductivity type poly-Si of the lower layer wiring 4 and the Al of the upper-layer wiring 6 are in direct contact, Al diffuses into the n-conductivity type poly-Si, and the poly-Si changes to the p-conductivity type. It is easy to form an alloy spike. For this reason, a barrier metal (not shown) such as titanium (Ti) or titanium nitride (TiN) is deposited after the contact hole 5h is formed, and then Al as the upper wiring 6 is deposited.

  As described above, in the semiconductor device 100 shown in FIGS. 1 and 2, unlike the conventional semiconductor device 90 shown in FIG. 11, the contact C <b> 2 of the lower layer wiring 4 and the upper layer wiring 6 is formed on the buried trench 20. It is disposed on the insulating film 30. For this reason, in the semiconductor device 100, the dead space DS associated with the contact C1 disposed in the element formation region 1a in the conventional semiconductor device 90 does not exist. Therefore, the semiconductor device 100 can be a semiconductor device having a high degree of integration while the element forming regions 1a and 1b are reliably insulated and separated by the buried trench 20.

  As shown in FIG. 2, in the semiconductor device 100, the surface of the cap insulating film 30 is a depression K1 immediately above the buried polycrystalline silicon 20b, and the surface of the cap insulating film 30 is not flat. The cap insulating film 30 having such a depression K1 has a narrow width of the buried trench 20 and is an etching back process after the deposition of buried polycrystalline silicon, and only by dry etching without using CMP (Chemical Mechanical Polishing) or the like. It is easy to form when flattening. The semiconductor device 100 in FIG. 2 is a semiconductor device that can be manufactured at low cost because the surface of the cap insulating film 30 is not subjected to special treatment even though the surface of the cap insulating film 30 is not flat.

In the semiconductor device 100 of FIG. 2, the contact C <b> 2 of the lower layer wiring 4 and the upper layer wiring 6 is disposed so as to cover the lowest point L _K <b> 1 of the depression K <b> 1 on the surface of the cap insulating film 30. On the other hand, FIG. 3 shows a cross-sectional view of another semiconductor device 101. In the semiconductor device 101 of FIG. 3, the contact C3 between the lower layer wiring 4 and the upper layer wiring 6 is arranged away from the lowest point L _K1 of the surface depression K1 in the cap insulating film 30.

In the semiconductor device 101 of FIG. 3, since the contact C3 is positioned off from the lowermost point L _K1 of the recessed portion K1, the angle θ2 is smaller than 90 ° portions of the side wall of the contact hole 5h to lower wiring 4 (reverse Taper). When reverse taper occurs in the contact hole 5h, the coverage of the upper wiring 6 is deteriorated. In particular, the above-described barrier metal (not shown) deposited before the formation of the upper wiring 6 has a large influence due to the thin film thickness, and the coverage is deteriorated at the portion where the reverse taper is generated, so that the barrier function is not performed. For this reason, in the semiconductor device 101, Al diffuses into the n-conductivity type poly-Si of the lower layer wiring 4, so that the poly-Si changes to the p-conductivity type, or an Al alloy spike 6s is formed in the poly-Si.

On the other hand, in the semiconductor device 100 of FIG. 2, by arranging the contact C2 covers the lowest point L _K1 of the depression portion K1, the angle θ1 formed by the side wall of the contact hole 5h to the underlying wiring 4, 90 ° or more (forward Taper). Therefore, since reverse taper does not occur in the contact hole 5h, it is possible to suppress the occurrence of problems such as spikes and voids. In this manner, the semiconductor device 100 shown in FIGS. 1 and 2 can be a semiconductor device having good electrical characteristics with no contact failure.

  As described above, the semiconductor device 100 of the present invention shown in FIGS. 1 and 2 has the contact C2 on the cap insulating film 30 without performing any special treatment even though the surface of the cap insulating film 30 is not flat. The semiconductor device is a low-cost and highly integrated semiconductor device that has good electrical characteristics with no increase in resistance due to contact failure due to spikes or voids.

  FIG. 4 shows a cross-sectional view of another semiconductor device 102 according to the present invention. In the semiconductor device 102 shown in FIG. 4, the same parts as those in the semiconductor device 100 shown in FIGS.

  In the semiconductor device 102 of FIG. 4, similarly to the semiconductor device 100 shown in FIGS. 1 and 2, the element formation region in the surface layer portion of the semiconductor substrate 1 is divided into two element formation regions 1 a and 1 b by insulation isolation by the buried trench 21. It is divided. The buried trench 21 in the semiconductor device 102 includes a trench side wall oxide film 21 a formed in the surface layer portion of the silicon substrate 1 and a buried polycrystalline silicon 21 b buried in the trench. Further, the surface of the buried polycrystalline silicon 21b is thermally oxidized, and a cap insulating film 31 that covers the buried trench 21 is formed on the buried trench 21 so as to be connected to the LOCOS 3. The buried trench structure can also be easily manufactured using a general semiconductor manufacturing technique.

  In the semiconductor device 102 of FIG. 4 as well, the contact C4 of the lower layer wiring 4 and the upper layer wiring 6 is arranged on the cap insulating film 31 formed on the buried trench 21 as in the semiconductor device 100 shown in FIGS. ing. Therefore, the dead space DS associated with the contact C1 disposed in the element formation region 1a in the conventional semiconductor device 90 of FIG. Therefore, the semiconductor device 102 can also be a semiconductor device having a high degree of integration while the element forming regions 1a and 1b are reliably insulated and separated by the buried trench 21.

  In the semiconductor device 100 shown in FIG. 2, the surface of the cap insulating film 30 is a depression K1 immediately above the buried polycrystalline silicon 20b, and the surface of the cap insulating film 30 is not flat. On the other hand, in the semiconductor device 102 of FIG. 4, the surface of the cap insulating film 31 is a constricted portion K2 immediately above the sidewall oxide film 21a, and the surface of the cap insulating film 31 is not flat. The cap insulating film 31 having such a depression K2 is formed when the buried trench 21 is wide and is planarized using CMP (Chemical Mechanical Polishing) in an etch-back process after depositing buried polycrystalline silicon. easy. The semiconductor device 102 in FIG. 4 is also a semiconductor device that can be manufactured at low cost because the surface of the cap insulating film 31 is not subjected to special treatment even though the surface of the cap insulating film 31 is not flat.

  In the semiconductor device 102 of FIG. 4, the contact C4 of the lower layer wiring 4 and the upper layer wiring 6 is directly above the buried polycrystalline silicon 21b indicated by the arrow L in the figure except for the constricted portion K2 on the surface of the cap insulating film 31. Has been placed. On the other hand, FIG. 5 shows a cross-sectional view of another semiconductor device 103. In the semiconductor device 103 of FIG. 5, the contact C5 of the lower layer wiring 4 and the upper layer wiring 6 includes the constricted portion K2 on the surface of the cap insulating film 31, and from directly above the buried polycrystalline silicon 21b indicated by the arrow L in the drawing. They are offset.

  In the semiconductor device 103 of FIG. 5, since the contact C5 is disposed including the constricted portion K2, a portion having an angle smaller than 90 ° is formed on the surface of the lower layer wiring 4 above the constricted portion K2. For this reason, the coverage of the upper wiring 6 is deteriorated, and a void 6v is generated. Further, the barrier metal (not shown) deposited before the formation of the upper layer wiring 6 has a large influence because of its thin film thickness, and the coverage is deteriorated so that the barrier function is not performed. For this reason, in the semiconductor device 103, Al diffuses into the n-conductivity type poly-Si of the lower layer wiring 4, so that the poly-Si changes to the p-conductivity type, or Al alloy spikes 6s are formed in the poly-Si.

  On the other hand, in the semiconductor device 102 of FIG. 4, by disposing the contact C4 immediately above the buried polycrystalline silicon 21b except for the constricted portion K2, deterioration of the coverage of the upper wiring 6 above the constricted portion K2 can be prevented. The occurrence of problems such as spikes and voids can be suppressed. In this manner, the semiconductor device 102 shown in FIG. 4 can also be a semiconductor device having good electrical characteristics with no contact failure.

  As described above, the semiconductor device 102 of the present invention shown in FIG. 4 also has the contact C4 disposed on the cap insulating film 31 without performing any special treatment even though the surface of the cap insulating film 31 is not flat. In addition, the semiconductor device is inexpensive and has a high degree of integration, and has good electrical characteristics without an increase in resistance due to contact failure due to spikes or voids.

  6 and 7 are sectional views of other semiconductor devices 104 and 105 according to the present invention. In the semiconductor devices 104 and 105 shown in FIGS. 6 and 7, the same parts as those of the semiconductor device 102 shown in FIG.

  The semiconductor devices 104 and 105 shown in FIGS. 6 and 7 are different from the semiconductor device 102 shown in FIG. 4 in that barrier metals 4 a and 4 b are stacked on the lower wiring 4. In the semiconductor devices 104 and 105, the upper layer wiring 6 is connected to the lower layer wiring 4 through contacts C6 and C7 via the barrier metals 4a and 4b. For example, titanium silicide (TiSi) or tungsten silicide (WSi) can be used as the barrier metals 4a and 4b. The barrier metal made of these materials has good barrier performance with respect to the lower layer wiring made of n-conducting type poly-Si and the upper layer wiring made of Al. It can be formed inexpensively. In the semiconductor device 104 shown in FIG. 6, after depositing n-conductivity type poly-Si that is a material of the lower layer wiring 4, titanium (Ti) or tungsten (W) is deposited and silicide is formed, and then the lower layer wiring 4. It is formed by patterning. On the other hand, in the semiconductor device 105 shown in FIG. 7, after depositing n-conductivity type poly-Si, it is patterned on the lower layer wiring 4 and salicide is formed by titanium (Ti) or tungsten (W).

  In the semiconductor devices 104 and 105 shown in FIGS. 6 and 7, by forming the barrier metals 4a and 4b on the lower wiring 4 before the formation of the interlayer insulating film 5, the lower layers of the barrier metals 4a and 4b are formed. The coverage for the wiring 4 is improved. As a result, a semiconductor device having good electrical characteristics can be obtained.

  FIG. 8 shows a cross-sectional view of another semiconductor device 106 according to the present invention. Note that in the semiconductor device 106 illustrated in FIG. 8, the same portions as those of the semiconductor device 102 illustrated in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted.

  The semiconductor device 106 shown in FIG. 8 is different from the semiconductor device 102 shown in FIG. 4 in that the silicon oxide film 33 is embedded in the constricted portion K2, and the surfaces of the cap insulating film 32 and the LOCOS 3 are flattened.

  9A to 9C are cross-sectional views for each process showing a flattening process of the cap insulating film 32 in the manufacturing process of the semiconductor device 106 of FIG.

First, as shown in FIG. 9A, a silicon oxide (SiO ₂ ) film 33 is deposited on the entire surface of the semiconductor substrate 1 by CVD, and the silicon oxide film 33 is embedded in the constricted portion K2. The silicon oxide film 33 may be formed using ozone (O ₃ ) -TEOS (Tetra-Etyl Ortho-Silicate), high-density plasma (HDP) -TEOS, or the like.

  Next, as illustrated in FIG. 9B, the silicon oxide film 33 is left only on the LOCOS 3 and the cap insulating film 32 by a photoetching process using the resist 70.

  Finally, as shown in FIG. 9C, planarization is performed by polishing.

  10A to 10C are cross-sectional views for each process showing another flattening process of the cap insulating film 32 in the manufacturing process of the semiconductor device 106 of FIG.

As shown in FIG. 10A, in this step, the silicon nitride (Si ₃ N ₄ ) mask 3m at the time of forming the LOCOS 3 is left on the semiconductor substrate 1, and a silicon oxide film 33 is deposited thereon. The silicon oxide film 33 is embedded in the constricted portion K2.

  Next, as shown in FIG. 10B, a resist 71 is deposited on the entire surface of the silicon oxide film 33. Instead of the resist 71, SOG (Spin On Glass) may be used.

  Finally, as shown in FIG. 10C, the entire surface is etched back by dry etching to perform planarization.

  In the semiconductor device 106 shown in FIG. 8, since the surface of the cap insulating film 32 is flattened, a reverse taper of the side wall of the contact hole 5h does not occur, and the unevenness of the lower layer wiring 4 due to the constricted portion K2 on the surface of the cap insulating film 32. Does not exist. For this reason, the deterioration of the coverage of the upper wiring 6 can be prevented, and the occurrence of problems such as spikes and voids can be suppressed. Therefore, the semiconductor device 106 of FIG. 8 is also a highly integrated semiconductor device in which the contact C8 is disposed on the cap insulating film 32, and can be a semiconductor device having good electrical characteristics without contact failure. .

  As described above, the semiconductor device 100 shown in FIGS. 1 and 2, the semiconductor device 102 shown in FIG. 4, and the semiconductor devices 104 to 106 shown in FIGS. In addition, a semiconductor device having a high degree of integration can be obtained.

It is the top view which showed typically the circumference | surroundings of the buried trench in the semiconductor device of this invention. FIG. 2 is a cross-sectional view taken along line AA in the semiconductor device of FIG. 1, showing a cross-sectional structure of a buried trench in more detail. FIG. 10 is a cross-sectional view of another semiconductor device in which the contacts are arranged away from the lowest point of the surface depression in the cap insulating film. It is sectional drawing of another semiconductor device in this invention. FIG. 11 is a cross-sectional view of another semiconductor device in which a contact is arranged so as to be displaced from immediately above buried polycrystalline silicon including a constricted portion K2 on the surface of a cap insulating film. It is sectional drawing of another semiconductor device in this invention. It is sectional drawing of another semiconductor device in this invention. It is sectional drawing of another semiconductor device in this invention. (A)-(c) is sectional drawing according to process which shows the planarization process of the cap insulating film in the manufacturing process of the semiconductor device of FIG. (A)-(c) is sectional drawing according to process which shows another planarization process of the cap insulating film in the manufacturing process of the semiconductor device of FIG. It is the top view which showed typically the circumference | surroundings of the buried trench in the conventional semiconductor device.

Explanation of symbols

90, 100 to 106 Semiconductor device 1 Semiconductor substrate 1a, 1b Element formation region 2, 20, 21 Buried trench 20a, 21a Side wall oxide film 20b, 21b Buried polycrystalline silicon 30-32 Cap insulating film 3 LOCOS
33 Silicon oxide film 4 Lower layer wiring 4a, 4b Barrier metal 5 Interlayer insulating film 5h Contact hole 6 Upper layer wiring C1 to C8 Contact K1 Recessed portion K2 Constricted portion

Claims (5)

The element formation region in the surface layer portion of the semiconductor substrate made of single crystal silicon is insulated by a buried trench made of a sidewall oxide film of the trench formed in the surface layer portion and a buried polycrystalline silicon buried in the trench, Divided into a plurality of element formation regions,
A lower layer wiring connected to the divided element formation region is formed through a field oxide film formed on the semiconductor substrate,
An upper layer wiring connected to the lower layer wiring is formed through an interlayer insulating film ,
In the semiconductor device in which the contact between the lower layer wiring and the upper layer wiring is disposed on a cap insulating film formed by thermally oxidizing the surface of the buried polycrystalline silicon formed on the buried trench ,
The surface of the cap insulating film is a recess directly above the buried polycrystalline silicon,
A semiconductor device characterized in that the contact is arranged so as to cover the lowest point of the depression . The element formation region in the surface layer portion of the semiconductor substrate made of single crystal silicon is insulated by a buried trench made of a sidewall oxide film of the trench formed in the surface layer portion and a buried polycrystalline silicon buried in the trench, Divided into a plurality of element formation regions,
A lower layer wiring connected to the divided element formation region is formed through a field oxide film formed on the semiconductor substrate,
An upper layer wiring connected to the lower layer wiring is formed through an interlayer insulating film,
In the semiconductor device in which the contact between the lower layer wiring and the upper layer wiring is disposed on a cap insulating film formed by thermally oxidizing the surface of the buried polycrystalline silicon formed on the buried trench,
The surface of the cap insulating film is a constricted portion immediately above the sidewall oxide film,
Except for the constriction, semi conductor arrangement, characterized in that said contact is disposed directly above the buried polycrystalline silicon. The lower wiring is made of n-conducting polycrystalline silicon (poly-Si), the upper layer wiring, the semiconductor device according to claim 1 or 2, characterized in that it consists of aluminum (Al). A barrier metal is laminated on the lower layer wiring,
The upper layer wiring through the barrier metal, a semiconductor device according to any one of claims 1 to 3, characterized in that connected to the lower wiring. 5. The semiconductor device according to claim 4 , wherein the barrier metal is titanium silicide (TiSi) or tungsten silicide (WSi) .

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