KR20010004925A - Pulse word line signal generator - Google Patents

Abstract

PURPOSE: A pulse word line signal generator is provided to reduce a current consumption by generating a pulse word line signal in response to a signal sensing a variation of a sensing operation after consisting of a latch circuit for the pulse word line signal generator and then disabling the pulse word line signal after sensing. CONSTITUTION: A pulse word line signal generator of a semiconductor memory device includes a sensing detector(20) and a latch portion(30). The sensing detector receives an output signal of a sense amplifier and senses a time point when a sensing operation is completed. The sensing detector has a NAND gate(NA3). The latch portion generates a pulse word line signal when a pulse equalization signal is a first logic state and latches the pulse word line signal until when an output signal of the sensing detector becomes a second logic state. The latch portion has a flip-flop consisting of NOR gates(NR1,NR2). The first logic state is a logic high.

Description

Pulse word line signal generator

The present invention relates to a pulse word line signal generator for activating a word line, and more particularly, so that a pulse word line signal (PWL) is not affected by a change in power supply voltage and temperature. The present invention relates to a pulse word line signal generator which reduces current consumption by automatically turning off a pulse word line (PWL) signal after sensing by configuring a latch circuit instead of a conventional delay circuit and detecting a change in sensing operation. .

In general, when a data stored in a cell of a semiconductor memory is read out, first, when a row address is input, a word line corresponding to the address is activated, and a bit line sense amplifier is operated after a predetermined time to activate the cell of the active word line. The data is latched (row active time tRCD). After inputting the column address, information of the selected bit line sense amplifier is transmitted to the data line sense amplifier through the data line, amplified, and transmitted to the data output buffer.

FIG. 1 is a circuit diagram of a conventional pulse word line signal generator. The inverter INV1 inputs a pulse equalization signal (PEQ) signal and outputs an inverted signal to the node Nd1 and the node Nd1. Inverters INV2 and INV3 for amplifying the signal and outputting the signal to the node Nd2, a first delay circuit unit 10 for outputting the signal of the node Nd2 to the node Nd3 after a predetermined time delay; A NAND gate NA1 for outputting a signal calculated by inputting the signals of the node Nd1 and the node Nd3 to the node Nd4, an inverter INV4 for inverting and outputting the signal of the node Nd4; The second delay circuit unit 12 outputs the output of the inverter INV4 to the node Nd5 after a predetermined time delay, and the output signals of the nodes Nd1 and Nd5 are input. And a NAND gate NA2 output as a pulse word line signal.

The operation by the above configuration will be described with reference to the operation waveform diagrams shown in Figs. 2A to 2F.

First, when the pulse equalization signal PEQ is input, the pulse equalization bar PEQB signal Nd1, which is a signal inverted by the inverter IMV1, is generated, and the pulse equalization bar PEQB signal is converted into the inverters INV2 and INV3. After the amplification through the first delay circuit 10, the node Nd3, which is a signal delayed by (a) to the pulse width of the pulse equalization bar PEQB, is generated. This signal is inputted to the pulse equalizing bar (PEQB) signal Nd1 and the NAND gate NA1 input terminal, and then generates a node Nd4 signal. The signal of this node Nd4 is inverted again by the inverter INV4 and then input to the second delay circuit section 12. The second delay circuit unit 12 outputs the inverted signal of the node Nd4 by the signal (b) to the node Nd5. The signal of the delayed node Nd5 and the signal of the node Nd1 are input to the NAND gate NA2, and then NAND-operated to generate a pulse word line PWL signal. The finally generated pulse word line PWL signal has a delay width corresponding to the time delayed by the first delay circuit unit 10 and the second delay circuit unit 12.

However, in the conventional pulse word line signal generator configured as described above, the pulse word line (PWL) signal, which is an output signal, is formed by the first and second delay circuit parts 10 and 12 which determine the pulse width. PWL) pulse width is determined, the change of each delay value is large at the operating voltage having a wide bandwidth. This affects the operating time of all circuits operated by the pulse word line signal, so that the pulse word line pulse width can be set in accordance with the worst condition for stable operation. As a result, in circuits having different operating states, the circuits are unnecessarily kept in the enabled state, thereby increasing the current consumption. In particular, when the power supply voltage and temperature change are large, the change in the pulse word line (PWL) pulse width may be severe, causing unnecessary circuit operation.

Accordingly, an object of the present invention is to solve the above problems, and an object of the present invention is to configure a sensing circuit by using a latch circuit instead of a delay circuit so that a pulse word line (PWL) signal is not affected by a change in power supply voltage and temperature. By generating the signal by detecting the change of the, it is to provide a pulse word line (PWL) generator to reduce the current consumption by automatically turning off the pulse word line (PWL) signal after sensing.

1 is a circuit diagram of a conventional pulse word line signal generator

2A to 2F are operational waveform diagrams of a conventional pulse word line signal generator.

3 is a circuit diagram of a pulse word line signal generator of the present invention;

4A to 4F are operational waveform diagrams of the pulse word line signal generator of the present invention.

Explanation of symbols on the main parts of the drawings

10: first delay circuit portion 12: second delay circuit portion

20: sensing detection unit 30: flip flop unit

In order to achieve the above object, the pulse word line signal generator according to the present invention,

Sensing detection means for detecting a time point at which a sensing operation is completed by inputting the output signal of the sense amplifier at least;

And latch means for generating a pulse wordline signal when the pulse equalization signal has a first logic state and latching it until the output signal of the sensing detection means has a second logic state.

In addition to the above configuration, the sensing detection means is preferably constituted by a NAND gate.

The latch means is a flip flop, wherein the flip flop is preferably a NOR gate.

In addition, the first logic state is a state transitioned from 'logic low' to 'logic high'.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

3 is a circuit diagram of a pulse word line signal generator according to the present invention, which includes a sensing detector 20 for detecting a time point when a sensing operation of a sense amplifier is completed, an output signal Nd6 of the sensing detector 20, and a pulse equalization ( And a latch circuit section 30 for outputting a pulse word line (PWL) signal as a PEQ signal.

The sensing detector 20 is configured as a NAND gate NA3 that outputs a signal detected by a sensing change to the node Nd6 by inputting the output signals SA10 and SA10b of the sense amplifier. The latch circuit unit 30 includes a flip flop including NOR gates NR1 and NR2 for outputting a pulse word line PWL signal by inputting the node Nd6 and a pulse equalization signal PEQ.

The operation by the above configuration will be described with reference to the operation waveform diagrams shown in Figs. 4A to 4F.

Before sensing data from the sense amplifier, the output signals SA10 and SA10b of the sense amplifier are always precharged with the power supply voltage Vdd, and are respectively input to the NAND gate NA3 as a 'high' signal to connect the node Nd6. Make it a 'low' signal. At this time, when the 'low' signal of the node Nd6 is input to the latch circuit unit 30, the pulse word line PWL signal is reset to 'low' by the NOR gate NR1 to perform the pulse equalization (PEQ) signal. Wait for input. At this time, when the pulse equalization signal is input, the pulse word line PWL signal is turned on by the NOR gate NR2 at the rising portion of the pulse equalization signal PEQ.

Then, when data sensing is performed through the data read path, one of the SA10 and SA10b signals output from the sense amplifier drops to the low potential level. The sensing detector 20 senses this and the node Nd6, which is a reset signal, changes to 'high', and the reset signal Nd6 is input to the NOR gate NR1 to turn off the pulse word line PWL signal. do.

The pulse word line (PWL) generator of the present invention can reduce the current consumption of the entire circuit used in the read operation of the memory device, can be applied to a high-integrated circuit, and can be effectively used for a memory device used for portable use. This can lead to improved competitiveness.

As described above, according to the pulse word line PWL generator according to the present invention, the pulse word line PWL signal is configured by a latch circuit instead of a conventional delay circuit and sensed so as not to be affected by changes in power supply voltage and temperature. By generating the signal by detecting a change in operation, the pulse word line (PWL) signal is automatically turned off after sensing, thereby reducing current consumption.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (5)

In a semiconductor memory device, Sensing detection means for detecting a time point at which a sensing operation is completed by inputting the output signal of the sense amplifier at least; A pulse word line signal comprising a latch means for generating a pulse word line signal when the pulse equalization signal has a first logic state and latching it until the output signal of the sensing detection means has a second logic state generator. The method of claim 1, And said sensing detecting means comprises a NAND gate. The method of claim 1, And said latch means comprises a flip flop. The method of claim 1, And the flip flop is a flip flop with a NOR gate. The method of claim 1, And the first logic state is a state transitioned from 'logic low' to 'logic high'.