KR100256902B1 - Control circuit for semiconductor memory device - Google Patents

Abstract

PURPOSE: A control circuit of a semiconductor memory device is provided to reduce current consumption when writing operation is performed by using a pulse. CONSTITUTION: The control circuit includes an address transition detecting portion(100), a dummy bit line(200), a logic unit, a pulse generating portion(300), a sense enable signal generating portion(400), a write signal generating portion(500) and an enable signal generating portion(600). The address transition detecting portion detects the transition of an address signal inputted from the outside and outputs a precharging signal. The dummy bit line inputs the precharging signal together with a word line enabling signal. The logic unit the precharging signal together with a write signal. A signal from the logic unit is inputted to the pulse generating portion and the pulse generating portion generates a pulse signal. An output signal of the dummy bit line, the precharging signal and the pulse signal are inputted to the sense enable signal generating portion and the sense enable signal generating portion outputs a sense enabling signal. A signal transmitted from the sense enable signal generating portion, a signal from the logic unit and the pulse signal are inputted to the write signal generating portion, and the write signal generating portion outputs a write signal. The precharging signal, the sense enabling signal and the pulse signal are inputted to the enable signal generating portion, and the enable signal generating portion outputs an X-decoder enabling signal.

Description

Control Circuit of Semiconductor Memory Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit of a semiconductor memory device, and more particularly, to a control circuit of a semiconductor memory device capable of preventing power consumption by controlling write and read operations of an SRAM.

In general, an SRAM cell consists of a memory flip-flop circuit and two switches. When a cell transistor is turned on by applying a pulse to a word line, data can be transferred between a pair of bit lines and a pair of data bus lines. Unlike the DRAM, as long as the power is applied, the flip-flop feedback effect allows the static data to be preserved without the refresh operation.

An SRAM of a general semiconductor memory device will be described with reference to FIG. 1.

Referring to FIG. 1, an SRAM of a general semiconductor memory device may be used for precharge for precharging the bit line BL and the inverting bit line / BL, respectively, by a precharge signal PRE applied to a gate. NMOS transistors NM1 and NM2, a pull-up NMOS transistor NM3 connected between the bit line BL and the power supply voltage, and a pull-up NMOS transistor NM4 connected between the inverting bit line / BL and the power supply voltage. And the bit line BL and the inverting bit line / BL by the memory cell 10 connected between the bit line BL and the inverting bit line / BL and the column signal COL applied to the gate. Selected NMOS transistors NM5 and NM6 for selection, respectively, are connected between the data bus line DBL and the inverted data bus line / DBL and are connected to each other by the sense enable signal SE of the memory cell 10. And a sense amplifier 20 for sensing and amplifying the data.

In addition, an SRAM of a general semiconductor memory device includes write NMOS transistors NM7 and NM8 for writing data for storing data in the memory cell 10 by a write signal WR applied to a gate, and an output terminal of the SRAM. A CMOS inverter 30 which is connected to the drain of the NMOS transistor NM8 for connection, and which has a PMOS transistor PM1 and an NMOS transistor NM9 connected in series between a power supply voltage and ground, and an output terminal of the NMOS transistor NM7 for a light. It is further provided with a CMOS inverter 40 connected to the drain, the input terminal is connected to the output terminal of the CMOS inverter 30, consisting of the PMOS transistor PM2 and the NMOS transistor NM10 connected in series between the power supply voltage and ground.

Meanwhile, the bit line BL is connected between the precharge NMOS transistor NM1 and the selection NMOS transistor NM5, and the inverting bit line / BL is the precharge NMOS transistor NM2 and the selection NMOS transistor. The data bus line DBL is connected between the selection NMOS transistor NM5 and the write NMOS transistor NM7, and the inversion data bus line / DBL is connected to the selection NMOS transistor NM6. ) And the write NMOS transistor NM8.

The memory cell 10 includes a PMOS transistor PM3, a storage node N1, and an NMOS transistor NM11 sequentially connected between a power supply voltage and ground, and a PMOS transistor PM4 sequentially connected between a power supply voltage and ground. , A storage node N2 and an NMOS transistor NM12, a word line WL connected to the gate, and a pass NMOS transistor NM13 connected between the storage node N1 and the bit line BL. A word line WL is connected to the gate, and a pass NMOS transistor NM14 is connected between the storage node N2 and the inverting bit line / BL.

The gates of the PMOS transistor PM3 and the NMOS transistor NM11 of the memory cell 10 are connected to the storage node N2, respectively, and the gates of the PMOS transistor PM4 and the NMOS transistor NM12 are respectively stored. It is connected to node N1.

Referring to the operation of the SRAM of the general semiconductor memory device having the above structure is as follows.

When the high state precharge signal PRE is applied, the precharge NMOS transistor NM1 applies a power supply voltage to precharge the bit line BL, and the precharge NMOS transistor NM2 supplies a power supply. A voltage is applied to precharge the inverting bit line / BL.

When the data of the memory cell 10 is read, the sensing amplifier 20 receives a sense enable signal of a high state and stores the node N1 of the memory cell 10 transferred through the bit line BL. And sense and amplify the data of the storage node N2 of the memory cell 10 transferred through the inversion bit line / BL and output the data through the output terminal DOUT.

In addition, when performing a write operation for storing data in the storage nodes N1 and N2 of the memory cell 10, the write NMOS turned on by the high-state write signal WR applied to the gate. Data output from the CMOS inverter 40 through the transistor NM7 is stored in the storage node N1 of the memory cell 10, and is also turned on by the high state light signal WR applied to the gate. Data output from the CMOS inverter 30 through the NMOS transistor NM8 is stored in the storage node N2 of the memory cell 10. At this time, data opposite to each other is stored in the storage node N1 and the storage node N2.

That is, when the low state data signal DIN is input to the CMOS inverter 30, the low state data is stored in the storage node N1, and the high state data is stored in the storage node N2. On the contrary, when the data signal DIN of the high state is input to the CMOS inverter 30, the high state data is stored in the storage node N1, and the low state data is stored in the storage node N2. .

Referring to FIG. 2, a conventional control circuit for controlling the write operation of the SRAM of the general semiconductor memory device as described above will be described.

Referring to FIG. 2, a control circuit of a conventional semiconductor memory device includes an address transition detector 50 for detecting a transition of an address signal input to an input terminal and outputting a precharge signal PRE, and an inverted light input from the outside. Inverter IV1 for inverting signal / WR to output write signal WR, precharge signal PRE output from address transition detection unit 50, and word line enable signal generator (shown in the drawing). Inputs the output signal of the dummy bit line 60 to one input terminal and inputs the output signal of the dummy bit line 60 to one input terminal. And a logic gate (NOR1) for inputting an output signal of the "

In addition, the control circuit of the conventional semiconductor memory device inputs the output signal of the address transition detection unit 50, the output signal of the inverter IV1, and the output signal of the NOA gate NOR1 to the first to third input terminals, respectively, to form a logic nore. N-gate (NOR2) for outputting a logic-n-decoded X-decoder (not shown) disable signal (XDEC_ENB) through the buffering unit 70, and NOR2 transferred through the buffering 70 Inverter IV2 for outputting a sense enable signal SE for enabling the sense amplifier 20 of FIG. 1 by inverting the output signal.

The buffering unit 70 is composed of even-numbered inverters IV3 and IV4.

In the word line enable signal WLEN applied to the word line WL and the dummy bit line 60 of FIG. 1, the word line enable signal generator not shown in the figure disables the address signal AD and the X-decoder. This is a logical combination of the signal XDEC_ENB. At this time, when the X-decoder disable signal XDEC_ENB is low, only one bit of the word bit enable signal WLEN of the plurality of bits is high and other bits are low. In contrast, when the X-decoder disable signal XDEC_ENB is high, all the bits of the word line enable signal WLEN go low.

The operation of the control circuit of the conventional semiconductor memory device having the structure as described above is as follows.

If any one of the plurality of bits of the address signal AD changes from high to low or from low to high, the address transition detector 50 outputs the precharge signal PRE in a high state, When it passes, it outputs a low precharge signal PRE. The address transition detection unit 50 continues to output the precharge signal PRE in a low state until the address signal AD transitions again.

The dummy bit line 60 outputs a high signal to the NOR gate NOR1 when any one of the plurality of bits of the word line enable signal WLEN is high.

When the high state signal is output from the address transition detector 50, the dummy bit line 60 outputs a low signal to the NOR gate NOR1, and the NOR gate NOR2 outputs a low signal to the NOR gate NOR1. Then, the NOR gate NOR1 outputs a high signal.

The operation at the time of writing of the control circuit of the conventional semiconductor memory element is as follows.

When the inverted write signal / WR in the low state is input from the outside, the inverter IV1 outputs the write signal WR in the high state and the X-decoder disable signal (in the low state) through the buffering unit 70. XDEC_ENB is output, and inverter IV2 outputs a sense enable signal SE in a high state.

Referring to Fig. 3, the read operation of the control circuit of the conventional semiconductor memory device will be described.

Referring to FIG. 3, (a) is an inverted write signal (/ WR), (b) is an address signal (AD), (c) is a precharge signal (PRE), and (d) is an X-decoder disable signal. (XDEC_ENB) and (e) are sense enable signals SE, (f) are word line enable signals WLEN, and (g) are output signals of the dummy bit line 60.

When the address signal of (b) is transferred, the precharge signal PRE of (c) output from the address transition detection unit 50 goes from low to high state and then goes back to low state. In addition, while the precharge signal PRE of (c) is in a high state, the X-decoder disable signal XDEC_ENB of (d), which is output from the buffering unit 70, goes from high to low, and the inverter ( The sense enable signal SE of (e) output from IV2) becomes low in high state.

Subsequently, while the X-decoder disable signal XDEC_ENB of (d) is low, the word line enable signal WLEN of (f) goes from high to low, and is output from the dummy bit line 60 ( The signal of g) also goes from low to high. When this signal (g) becomes high, the signal of (d) is made high and the signals of (e), (f) and (g) are sequentially made low.

However, the control circuit of the conventional semiconductor memory device as described above has a problem that it is difficult to use in small products such as portable products due to the large current consumption.

Accordingly, the present invention is to solve the above problems, to provide a control circuit of a semiconductor memory device that can be used for portable products that consume a small current by reducing the current consumption during the write operation by using a pulse. There is a purpose.

1 is a circuit diagram of an SRAM of a general semiconductor memory device.

2 is a control circuit diagram of a conventional semiconductor memory device.

3 is a characteristic diagram of a control circuit of a conventional semiconductor memory element.

4 is a control circuit diagram of a semiconductor memory device according to an embodiment of the present invention.

5 is a characteristic diagram of a control circuit of a semiconductor memory device according to an embodiment of the present invention.

6 is a control circuit diagram of a semiconductor memory device according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100: address transition detection unit 200: dummy bit line

300: pulse generator 400; Sense enable signal generating means

500: write signal generating means 600: enable signal generating means

700: delay

The control circuit of the semiconductor memory device of the present invention for achieving the above object includes an address transition detection unit for detecting the transition of the address signal input from the outside to output a precharge signal; A dummy bit line for inputting the precharge signal and a word line enable signal; Logic means for inputting the precharge signal and the write signal; A pulse generator for inputting a signal output from the logic means to generate a pulse signal; Sense enable generating means for inputting an output signal of the dummy bit line, the precharge signal and the pulse signal to output a sense enable signal; Write signal generation means for inputting a signal transmitted from said sense enable generation means, a signal output from said logic means, and said pulse signal to output a write signal; And an enable signal generating means for inputting the precharge signal, the sense enable signal and the pulse signal to output an X-decoder enable signal.

A control circuit of a semiconductor memory device according to an exemplary embodiment of the present invention includes a first NMOS transistor for precharge, in which a power voltage is applied to a gate sequentially connected between an output terminal of a dummy bit line and a ground, and a precharge signal is applied to a gate. A second NMOS transistor for charge and a third NMOS transistor for precharge to which a power supply voltage is applied to the gate; A delay unit for delaying the sense enable signal; And an inverter for inverting the sense enable signal.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 5.

Referring to FIG. 4, the control circuit of the semiconductor memory device of the present invention detects a transition of an address signal input from the outside and outputs a precharge signal PRE, and a precharge signal ( A dummy bit line 200 for inputting and outputting the word line enable signal WLEN and an externally transmitted word line enable signal WLEN, and an inverted pre outputted from the address transition detection unit 100 and input to one input terminal through the inverter IV100. NAND gate (NAND) for inputting the charge signal (/ PRE) and the inverted write signal (/ WR) transmitted from the outside to the type force stage through the inverter IV200, and then outputting the logic NAND value, and the NAND gate. The output signal of the pulse generator 300 generating the pulse signal PLS by inputting the signal output from the NAND and the dummy bit line 200 inverted through the inverter IV300 and the precharge signal PRE. ) And pulse signal (PLS) The sense enable generating means 400 for outputting the sense enable signal SE, the signal transmitted from the sense enable generating means 400, the signal output from the NAND gate NAND, and the pulse signal PLS. A write signal generation means 500 for inputting and outputting the write signal WR, a precharge signal PRE, a sense enable signal SE, and a pulse signal PLS to receive an X-decoder enable signal ( Enable signal generating means 600 for outputting XDEC_EN).

A control circuit of a semiconductor memory device according to an embodiment of the present invention may include a pre-charge first NMOS transistor NM100 and a gate to which a power voltage is applied to a gate sequentially connected between an output terminal of the dummy bit line 200 and a ground in series. A precharge second NMOS transistor NM200 to which the write signal WR is applied and a precharge third NMOS transistor NM300 to which a power supply voltage is applied to the gate; A delay unit 700 for delaying the sense enable signal SE1 and outputting a sense enable signal SE2; And an inverter IV400 for inverting the sense enable signal SE1.

The pulse generator 300 includes a delay unit 310 for delaying a signal output from the NAND gate, a signal transmitted by being delayed through the delay unit 310, and a signal directly transmitted from the NAND gate NAND. And a pulse generating means 320 for generating a pulse signal PLS.

The delay means 310 of the pulse generator 300 includes inverters IV310, IV320, and IV330 sequentially connected in series between an output terminal of the NAND gate NAND and the pulse generator 320.

The pulse generating unit 320 of the pulse generating unit 300 is provided with a NOR gate NOR 310 having one input terminal connected to an output terminal of the delay unit 310 and a type force terminal connected to an output terminal of the NAND gate NAND.

The sense enable signal generating means 400 includes a noar gate NOR410 having one input terminal connected to an output terminal of the inverter 300 and a type force terminal connected to an output terminal of the NOR gate NOR420, and a first input terminal having a noar gate NOR410. Is connected to an output terminal of the NAR420, and a second input terminal is connected to an output terminal of the address transition detection unit 100, and a third input terminal is connected to an output terminal of the pulse generator 300, and an input terminal is a NOR gate NOR420. Inverter IV410 is connected to the output terminal of the.

The write signal generating means 500 may include a noar gate NOR510 having one input terminal connected to an output terminal of the NOR gate NOR420 of the sense enable signal generating unit 400 and a type force terminal connected to an output terminal of the NAND gate NAND; One input terminal is connected to the output terminal of the pulse generator 300, the type force terminal is connected to the output terminal of the NOR gate (NOR510) (NOR520), and the input terminal is connected to the output terminal of the NOR gate (NOR520) has an inverter (IV510) do.

The enable signal generating means 600 has a first input terminal connected to the output terminal of the address transition detection unit 100, a second input terminal connected to the output terminal of the sense enable signal generating unit 400, and a third input terminal generating a pulse. The NOA gate NOR610 connected to the output terminal of the unit 300 and the inverter IV610 connected to the output terminal of the NOA gate NOR610 are configured.

The delay unit 700 is composed of a plurality of inverters IV710 and IV720 connected in series.

Referring to the write operation of the control circuit of the semiconductor memory device of the present invention having the above structure is as follows.

When the address signal AD is changed and an inverted write signal / WR in a low state is input from the outside, the address transition detection unit 100 detects this and outputs a high precharge signal PRE in a predetermined state. After the time, the low precharge signal PRE is output again.

When the inverted write signal / WR is kept low and the precharge signal PRE transitions from high to low, the pulse generator 300 outputs a high pulse signal PLS and then outputs a constant pulse. After the time, the pulse signal PLS in the low state is output again.

While the pulse signal PLS is in the high state, the sense enable generating means 400 outputs the sense enable signal SE1 in the high state, and then the enable signal generating means 600 is the X-decoder in the high state. The output of the NOA gate NOR420 goes low while the enable signal XDEC-EN is output and the sense enable signal SE1 of the high state is output. The write signal WR is output.

Since the word line enable signal WLEN is made by combining the X-decoder enable signal XDEC-EN and the address signal AD, one bit of the word line enable signal WLEN becomes high. Subsequently, the dummy bit line 200 outputs a low state signal by the word line enable signal WLEN and the high state write signal WR.

Here, the dummy bit line 200 outputs a phase opposite to the dummy bit line 60 of FIG. 2. That is, the dummy bit line 60 of FIG. 2 includes the inverter IV300 at the output terminal of the dummy bit line 200 of FIG. 4.

As such, when the low state signal is output from the dummy bit line 200, the NOR gate NOR410 of the sense enable generating unit 400 outputs a low state signal, and the NOR gate NOR420 is a high state signal. As a result, the sense enable signal generating means 400 outputs the sense enable signal SE1 in a low state, and then the sense enable signal SE2 delayed through the delay unit 700 is low. State, the enable generation means 600 outputs the low-definition X-decoder enable signal XDEC-EN, and the write signal generation means 500 outputs the low state write signal WR. .

In the conventional control circuit, since only the inverted light signal / WR applied from the outside is affected, when the low state of the inverted light signal / WR is long, the high state of the write signal WR is also long. As described above, the write signal WR generated by the control circuit of the present invention automatically transitions the write signal WR from high to low after the cell is written even if the low state of the inverted write signal / WR is long. Therefore, when DIN in FIG. 1 is low, the precharge NMOS transistors NM1 and NM3 pass through the NMOS transistor NM10, or when DIN is high, the precharge NMOS transistors NM2 and NM4 pass through the NMOS transistor ( The loss of current through NM9) does not exist after the cell has been written.

In addition, in the control circuit of the present invention, since the sense enable signal SE2 is low after the cell is written, the sense amplifier is not operated in all sections in which the inverted light signal / WR is low unlike the conventional art. There is no current loss after writing.

Therefore, the control circuit of the present invention can minimize the loss of current by adjusting the write signal by sensing whether the cell is written even when writing data to the cell.

5, a description will be given of an operation during writing of the control circuit of the semiconductor memory device of the present invention.

Referring to FIG. 5, (a) represents an address signal AD, (b) represents an inverted write signal / WR, (c) represents a precharge signal PRE, and (d) represents a pulse signal PLS, (e) is the sense enable signal SE1, (f) is the sense enable signal SE2, (g) is the X-decoder enable signal XDEC_EN, and (h) is the word line enable signal WLEN. , (i) is the write signal WR, (j) is the output signal of the inverter IV300.

When the address signal of (a) is transferred, the precharge signal PRE of (c) goes from low to high state and then goes back to low state, and then the inverted write signal (WR) of (b) becomes high. When the transition to low and the precharge signal PRE of (c) transitions from high to low, the pulse signal PLS of (d) goes from low to high.

When the pulse signal PRE of (d) transitions from low to high, the sense enable signal SE1 of (e) transitions from low to high, followed by the sense enable signal SE2 of (f), The X-decoder enable signal XDEC_EN of (g) and the write signal WR of (i) are transitioned from low to high, respectively.

Thus, when the X-decoder enable signal XDEC_EN of (g) transitions from low to high, the word line enable signal WLEN of (h) transitions from low to high, and the dummy bit line of (j) The output signal of the inverter IV300 at the rear stage is transitioned from low to high.

As such, when the output signal of the dummy bit line 200 of (j) transitions from low to high, the sense enable signal SE1 of (e) goes from high to low, followed by the sense enable of (f). The signal SE2, the X-decoder enable signal XDEC_EN of (g), the write signal WR of (i), and the like transition from high to low, respectively.

As described above, when the X-decoder enable signal XDEC_EN of (g) transitions from high to low, the word line enable signal WLEN of (h) transitions from high to low, and also of (j) The output signal of the inverter IV300 behind the dummy bit line 200 transitions from high to low.

Fig. 6 shows the control circuit of the present invention for use in a small capacity SRAM in accordance with an embodiment of the present invention.

Referring to FIG. 6, the control circuit of the present invention for use in a small capacity SRAM, as in FIG. 4, includes an address transition detection unit 100, a dummy bit line 200, a NAND gate, and a pulse. And a generation unit 300, a sense enable generation unit 400, a write signal generation unit 500, a precharge signal PRE, and an enable signal generation unit 600.

The control circuit of the present invention having the above structure is the same as that described in FIG.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope of the present invention without departing from the technical idea. It will be evident to those who have knowledge of.

As described above, the control circuit of the semiconductor memory device of the present invention uses self-generated pulses, and when the data is written to the cell, it automatically detects whether the cell is written and adjusts the write signal to adjust the write signal. The loss can be minimized, thus providing an excellent effect for use in portable products requiring low current.

Claims (11)

An address transition detector for detecting a transition of an address signal input from the outside and outputting a precharge signal; A dummy bit line for inputting the precharge signal and a word line enable signal; Logic means for inputting the precharge signal and the write signal; A pulse generator for inputting a signal output from the logic means to generate a pulse signal; Sense enable generating means for inputting an output signal of the dummy bit line, the precharge signal and the pulse signal to output a sense enable signal; Write signal generation means for inputting a signal transmitted from said sense enable generation means, a signal output from said logic means, and said pulse signal to output a write signal; And And an enable signal generating means for inputting the precharge signal, the sense enable signal, and the pulse signal to output an X-decoder enable signal. The method of claim 1, wherein the pulse generator Delay means for delaying the signal output from the NAND gate; And And a pulse generating means for generating the pulse signal by inputting a signal transmitted by being delayed through the delay means and a signal directly transmitted from the NAND gate. The method of claim 2, wherein the delay means And a plurality of inverters sequentially connected in series between the output terminal of the NAND gate and the pulse generation number. The method of claim 2, wherein the pulse generating means And a noah gate having one input terminal connected to an output terminal of the delay means and a type force terminal connected to an output terminal of the NAND gate. The method of claim 1, wherein the sense enable signal generating means A first NOR gate having one input terminal connected to an output terminal of the third inverter and a type force terminal connected to an output terminal of the second NOR gate; A second NOR gate having a first input terminal connected to an output terminal of the first NOR gate, a second input terminal connected to an output terminal of the address transition detector, and a third input terminal connected to an output terminal of the pulse generator; And And a fourth inverter having an input terminal connected to an output terminal of the second NOR gate. The method of claim 1, wherein the write signal generating means A first NOR gate having one input terminal connected to the sense enable signal generating means and a type force terminal connected to an output terminal of the NAND gate; A second NOR gate having one input terminal connected to an output terminal of the pulse generator and a type force terminal connected to an output terminal of the first NOR gate; And And a fourth inverter having an input terminal connected to an output terminal of the second NOR gate. The method of claim 1, wherein the enable signal generating means A noah gate having a first input terminal connected to an output terminal of the address transition detection unit, a second input terminal connected to an output terminal of a sense enable signal generating unit, and a third input terminal connected to an output terminal of a pulse generating unit; And a fourth inverter having an input terminal connected to an output terminal of the noble gate. The method of claim 1, wherein the delay unit A control circuit for a semiconductor memory device comprising a plurality of inverters connected in series. The method of claim 1, A first NMOS transistor for precharge, to which a power supply voltage is applied to a gate, and a second pre-charge NMOS transistor to which a write signal is applied to a gate, and a power supply to a gate, sequentially connected between an output terminal of the dummy bit line and ground A third NMOS transistor for precharge to which a voltage is applied; A delay unit delaying the sense enable signal; And And a fourth inverter for inverting the sense enable signal. The method of claim 1, When the light signal is transitioned from low to high, one edge of the output pulse signal of the pulse generator, that is, an edge at which the pulse signal transitions from low to high, is used. And a signal outputted from the sense enable signal generating means and outputted from the sense bit signal generator without using the other edge of the generator. The method of claim 1, And the pulse width of the pulse generator does not affect the pulse width of the write signal.

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