KR20000044569A - Local input/output driver of semiconductor device - Google Patents

Abstract

PURPOSE: A semiconductor device is provided to improve reliability on the device by stably sensing data stored in a memory cell. CONSTITUTION: A write driver contains a third input NAND gate(133) for receiving a control signal(STB) as well as nodes(N10,N11). The control signal is inputted in a reading operation not to operate a precharge instrument(74) in the reading operation. In the reading operation, PMOS transistors(P14,P16,P17) in the precharge instrument are turned off without the control signal with low level. Thus, a local I/O line voltage is not increased. Moreover, the control signal contains the same timing with a column address not to require a separate signal generating instrument.

Description

Local I / O Driver of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to a driver for driving a local input / output (I / O) bus line during a read operation.

In general, data stored in a cell of a memory semiconductor device is amplified by a sense amplifier and transferred through a data bus line. This sense amplification is amplified by one or more sense amplifiers in each data transfer process. In particular, the data stored in the cell is provided with a first sense amplifier which is connected to the bit line and bit bar line of each cell to amplify the voltage difference. It is passed through the line to the final output stage.

Typically, because data buslines have a fairly long length, data transfer is achieved by adding additional sense amplifiers on the data buslines. Moreover, sensing operations on such data buslines require a precharge circuit, which is provided to prevent data collisions in sensing operations. However, as the degree of integration of the device increases and the length of the line increases, the driving force of the sense amplifier decreases and the load increases.

Fig. 1 is a block diagram showing a conventional local I / O driver circuit, showing a sense amplifier 1 and a local I / O driver 2 for amplifying cell data. Also, prior to passing data to the global buslines GRIO and GRIOZ, the local I / O driver 2 writes with an I / O sense amplifier 4 that amplifies the cell data input through the local I / O line. In operation, a write driving circuit 3 is provided to provide a voltage to a local I / O line (or bit line LIO and LIOZ) connected to a cell.

FIG. 2 shows a conventional write driver circuit formed in the local I / O driver circuit of FIG. 1, in which the write enable signal WE, the read control signal WDQN and the write data GWIO are respectively input. Data is loaded on local I / O lines (LIO and LIOZ). In the read operation, block 74 precharges the local I / O lines LIO and LIOZ to the power supply voltage Vdd. That is, in the read operation, the node N1 is in the low state, and the PMOS transistor P56 is turned on to turn on the PMOS transistors P14, P16, and P17 of the block 74 to thereby turn on the voltages of the local I / O lines LIO and LIOZ. Precharge the level to Vdd. Meanwhile, the write circuit 75 including three PMOS transistors P43 to P45 boosts the voltage of the local I / O lines LIO and LIOZ to Vdd under the control of the write enable signal WE.

As such, since the write driver precharges the local I / O line (or bit line) during a read operation, the amplified cell data may be changed slightly to generate an error. Is a timing diagram showing. In FIG. 3, even though the sense amplifier enable signal SEA and the column address CY0 are input and the data sensing operation is performed, if a slight malfunction occurs, the local I / O lines LIO and LIOZ and the global bus There will be little voltage difference on the lines (GRIO and GRIOZ). Other detailed operations of FIG. 2 will be referred to in the description of FIG. 7 of the present invention.

5 is a waveform diagram of each signal when a normal sensing operation occurs, and although a voltage difference occurs in the bit line during a read operation, it can be seen that the difference is very weak. This minute change occurs because the precharge means 74 of FIG. 2 continues to precharge the bit line even when cell data is loaded on the local I / O line in synchronization with the column address CY0 signal.

Therefore, such minute voltage difference not only requires a sense amplifier having a plurality of sensing stages on the data bus line, but also poses a problem of not being reliable for the data stored in the memory device.

5 shows a sense amplifier located on a data bus line, in which a current mirror type sense amplifier 50 and a cross coupled sense amplifier 51 are used to sense amplify the voltage difference on the local I / O lines LIO and LIOZ. A conventional two stage sense amplifier is shown. As described above, this structure occurs because the voltage difference between the local I / O lines LIO and LIOZ is not sufficient, resulting in an increase in the degree of integration of the device.

Disclosure of Invention The present invention devised to solve the above problems is to provide a semiconductor memory device capable of securing reliability by stably sensing data stored in a memory cell.

In addition, an object of the present invention is to provide a semiconductor device capable of increasing the integration of the device by simplifying the configuration of the sense amplifier formed on the data bus line through the stable sensing of data stored in the memory cell.

1 is a block diagram showing a conventional local I / O driver circuit;

2 is a block diagram showing a conventional write driver circuit;

3 is a characteristic graph of a conventional local I / O driver showing distortion of cell data;

4 is a characteristic graph of a conventional local I / O driver;

5 is a circuit diagram of a conventional data bus line sense amplifier;

6 is a block diagram showing a local I / O driver circuit in accordance with the present invention;

7 is a block diagram showing a write driver circuit according to the present invention;

8 is a circuit diagram of an input / output sense amplifier according to the present invention;

9 is a characteristic graph of a local I / O driver according to the present invention;

* Explanation of symbols for the main parts of the drawings

70, 71: latch circuit 72, 73: inverter

74: precharge means 75: voltage raising means

77: 3-input NAND gate

In order to achieve the above object, the present invention provides a write driver circuit of a semiconductor memory device, comprising: a pair of bit lines connected to a cell; Data transfer means for transferring data to the bit line pair in a write operation; Precharge means for precharging the pair of bit lines; Voltage raising means for supplying a power supply voltage to the pair of bit lines during a write operation; And precharge voltage blocking means for cutting off the voltage from said precharge means during a read operation.

The present invention also provides a semiconductor memory device including a write driver coupled to a pair of bit lines, the write driver comprising: precharge means for precharging the pair of bit lines; And a precharge voltage cut-off that senses that a read operation is performed by receiving a control signal having the same timing as the voltage level and the column address provided by the write enable and cuts off the voltage supply from the precharge means to the pair of bit lines. It comprises a means.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

First, FIG. 6 schematically illustrates data sensing of a memory device according to the present invention, in which reference numeral 51 denotes a sense amplifier for sensing and amplifying cell data, 53 denotes a write driver, and 54 denotes a data busline sense amplifier. have.

As shown in FIG. 6, the local I / O driver 52 having the write driver 53 and the data busline sense amplifier 54 is different from the conventional local I / O driver shown in FIG. It can be seen that one control signal STB is additionally input. The control signal STB is input to the write driver 53 to block the Vdd voltage provided from the write driver during a read operation.

The function of the control signal STB will now be described in detail with reference to FIG. 7 illustrating a write driver according to the present invention. First, while the write operation is performed, the write enable signal WE transitions high to turn off the PMOS transistors P56 and P65 (the NNOS transistors N55 and N64 are turned on), and the write control signal in the low state. (WDQM) is input to turn on the NMOS transistors N58 and N63. In this state, when the data GWIO is input to the NMOS transistors N59 and N62 from the outside, pulse data is generated in the local I / O line LIO according to the input data state. Meanwhile, data inverted by the inverter 178 is input to the local I / O line LIO, and data is input through the two inverters 178 and 180 in the local I / O line LIOZ. The / O line always has the opposite phase when entering data.

As a result, the voltage of the node N10 is stored in the latch circuit 70 composed of two inverters 129 and 152 and inverted by the inverting means 72, so that the local I / O line LIO is in accordance with the input value. ) Will be loaded into the data. On the other hand, the inverting means 72 is a conventional CMOS inverter consisting of a PMOS transistor P5 and an NMOS transistor N42 connected in series, the NMOS transistor N42 receives the output of the latch circuit 70, The PMOS transistor P5 is configured to receive an output of the latch circuit 71 including two inverters 17 and 160 on the local I / O line LIOZ. Similarly, the inverting means 73 on the local I / O line LIOZ composed of the PMOS transistor P11 and the NMOS transistor N33 is also configured such that the output of the latch circuit 70 is input to the NMOS transistor N33. .

On the other hand, when the read operation is performed in the conventional write driver shown in Fig. 2, since the PMOS transistors P65 and P56 are turned on and the NMOS transistors N63 and P58 are turned off, the node N10 and the node N11 are turned off. Each has a high level (not a write operation), so that the NAND gate 133 goes low. As a result, the conventional write driver precharges two local I / O lines (LIO and LIOZ) to Vdd even when read.

In contrast, the write driver according to the present invention has a three-input NAND gate 133 and is configured to receive not only the voltage levels of the nodes N10 and N11 but also the control signal STB described with reference to FIG. 6. have. That is, the control signal STB is a control signal input during the read operation, and serves to prevent the precharge means 74 from operating during the read operation.

For example, assuming that a read operation is performed, although the node N10 and the node N11 of FIG. 7 maintain the high level, the precharge means 74 does not receive the low level control signal STB. The PMOS transistors P14, 16, and 17 are turned off to prevent the local I / O line LIO and LIOZ voltages from increasing. Moreover, the control signal STB does not require a separate signal generating means by having the same timing as the column address.

On the other hand, the voltage raising means 75 for driving the local I / O lines LIO and LIOZ to the Vdd voltage level during the write operation is driven by the write enable signal.

The sense amplifier formed on the data bus line of the memory semiconductor of the present invention having the write driver as shown in FIG. 7 can ensure accuracy of data transmission even if only one cross coupled amplifier is configured as shown in FIG. This is because there is already enough sense amplifier in the bitline during the read operation.

9 is a timing diagram of each signal according to the write and read operation according to the present invention. As shown in FIG. 9, it can be seen that the voltage difference on the local I / O lines LIO and LIOZ during the read operation according to the present invention is significantly increased than the voltage difference in FIG.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

According to the present invention as described above, by simply adding a control signal of the hina to prevent the precharge voltage of the write driver transferred to the bit line during the read operation, the sensing margin can be secured to ensure the reliability of data sensing. By securing the sensing margin of the bit line, the structure of the sense amplifier located on the data bus line can be simplified.

Claims (3)

In a write driver circuit of a semiconductor memory device, Data transfer means for transferring data to the bit line pair in a write operation; Precharge means for precharging the pair of bit lines; Voltage raising means for supplying a power supply voltage to the pair of bit lines during a write operation; And And a precharge voltage blocking means for cutting off the voltage from said precharge means during a read operation. The method of claim 1, The precharge voltage blocking means, A control signal having a timing equal to the voltage level and the column address provided by the write enable is sensed to sense that a read operation is in progress, and the voltage supply to the bit line pair is cut off from the precharge means. driver. A semiconductor memory device comprising a write driver connected to a bit line pair, the semiconductor memory device comprising: The write driver includes precharge means for precharging the pair of bit lines; And Pre-charge voltage blocking means for detecting a voltage from the pre-charge means to the bit line pair by detecting a read operation by receiving a control signal having the same timing as the voltage level and the column address provided by the write enable. Write driver, characterized in that consisting of.