KR20010004712A - Method of forming a matal wiring in a semiconductor - Google Patents
Method of forming a matal wiring in a semiconductor Download PDFInfo
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- KR20010004712A KR20010004712A KR1019990025426A KR19990025426A KR20010004712A KR 20010004712 A KR20010004712 A KR 20010004712A KR 1019990025426 A KR1019990025426 A KR 1019990025426A KR 19990025426 A KR19990025426 A KR 19990025426A KR 20010004712 A KR20010004712 A KR 20010004712A
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 9
- 238000005240 physical vapour deposition Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims description 8
- 229910018182 Al—Cu Inorganic materials 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 5
- 229910002065 alloy metal Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 150000004678 hydrides Chemical class 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000010949 copper Substances 0.000 abstract description 25
- 239000010410 layer Substances 0.000 abstract description 23
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052802 copper Inorganic materials 0.000 abstract description 7
- 229910045601 alloy Inorganic materials 0.000 abstract description 6
- 239000000956 alloy Substances 0.000 abstract description 6
- 229910052782 aluminium Inorganic materials 0.000 abstract description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 5
- 239000011229 interlayer Substances 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 230000009977 dual effect Effects 0.000 abstract description 2
- 238000001465 metallisation Methods 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000010936 titanium Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53219—Aluminium alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53233—Copper alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 금속 배선 형성방법에 관한 것으로 특히, Al-Cu 합금을 이용한 반도체 소자의 금속 배선 형성방법에 관한것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices using Al—Cu alloy.
일반적으로 반도체 소자에서 금속 배선은 기판 상에 형성된 각 단위 소자들에 대한 전력의 입/출력 및 정보의 교환 역할을 수행한다. 따라서, 반도체 소자의 금속 배선의 저항은 소자의 속도를 결정하는 중요한 요소이므로 저항이 낮은 금속을 배선 재료로 하는 것은 중요한다.In general, metal wirings in semiconductor devices play a role of input / output and information exchange of power for each unit device formed on a substrate. Therefore, since the resistance of the metal wiring of the semiconductor element is an important factor for determining the speed of the element, it is important to use a metal having a low resistance as the wiring material.
종래 반도체 소자의 금속 재료로 대표적인 것이 알루미늄(Al)이다. Al 증착은 물리적 기상증착(Physical Vapor Deposition)방법인 스퍼터링으로 형성한다.A typical metal material of a semiconductor device is aluminum (Al). Al deposition is formed by sputtering, which is a physical vapor deposition method.
Al의 용융점이 660℃로 다른 금속에 비해 비교적 낮다. 따라서, Al 배선 형성 공정은 스퍼터링시 반도체 기판의 온도를 400 내지 500℃ 로 올려 흐름성을 증가 시켜 콘택을 매립한다.The melting point of Al is 660 ° C., which is relatively low compared to other metals. Therefore, in the Al wiring forming process, the temperature of the semiconductor substrate is increased to 400 to 500 ° C. during sputtering to increase the flowability to fill the contact.
Al 배선의 콘택 매립을 더욱 증가 시키기 위하여 상온에서 Al을 얇게 도포한 후 400 내지 500℃에서 다시 Al을 증착하는 2 차 증착법을 이용한다. 이때, Al의 흐름을 개선하기 위하여 웨팅층(Wetting layer)으로 타이타늄(Ti)을 사용한다. 그러나, 상기 방법은 종횡비가 2 이상일 경우에는 콘택 홀의 성공적인 매립이 불가능하다.In order to further increase the contact filling of the Al wiring, a second deposition method is used in which Al is thinly coated at room temperature and then Al is deposited again at 400 to 500 ° C. At this time, in order to improve Al flow, titanium (Ti) is used as a wetting layer. However, this method does not allow successful filling of contact holes when the aspect ratio is two or more.
또한, 화학 기상증착 방법으로 매립하는 Al 금속은 종횡비가 2 이상일 경우에도 콘택 홀을 매립 할 수 있으나, 화학적 기상증착 방법의 특성상 구리(Cu)를 합금 원소로 첨가하기 어려운 단점이 있다. 즉, Al 소오스 가스 및 Cu 소오스 가스의 혼합을 사용하는 공정은 두 기체의 반응성의 차이와 같은 여러 문제점으로 인하여 안정적인 금속 배선을 형성하기 어려운 문제점이 있다.In addition, the Al metal buried by the chemical vapor deposition method may be buried contact hole even when the aspect ratio is 2 or more, but due to the characteristics of the chemical vapor deposition method it is difficult to add copper (Cu) as an alloying element. That is, the process using a mixture of Al source gas and Cu source gas has a problem that it is difficult to form a stable metal wiring due to various problems such as the difference in reactivity of the two gases.
상기한 문제점이 해소 되도록 본 발명은 화학 기상 증착 방법을 이용한 Al 배선 형성시 물리적 기상증착 방법에 의해 증착된 Cu 의 확산을 이용하여 합금화 하는 반도체 소자의 금속 배선 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems, an object of the present invention is to provide a method for forming metal wirings of a semiconductor device alloyed using diffusion of Cu deposited by physical vapor deposition in forming Al wirings using a chemical vapor deposition method.
상기한 목적을 달성하기 위한 본 발명은 반도체 소자를 구성하기 위한 여러 요소가 구비된 반도체 기판 상에 금속 라인이 노출 되도록 콘택 홀을 형성하는 단계와, 상기 금속 라인과 접촉되도록 제 1 Cu막, Al층 및 제 2 Cu막을 순차적으로 형성하여 콘택 홀을 매립하는 단계와, 상기 제 1 및 2 Cu막이 Al층으로 확산 되도록 열공정을 실시한 후 평탄화 공정을 실시하여 Al-Cu 합금 금속 배선을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention for achieving the above object is to form a contact hole to expose a metal line on a semiconductor substrate having a number of elements for constituting a semiconductor device, the first Cu film, Al to be in contact with the metal line Forming a layer and a second Cu film sequentially to fill a contact hole, and performing a thermal process to diffuse the first and second Cu films into the Al layer, and then performing a planarization process to form an Al-Cu alloy metal wiring. Characterized in that it comprises a.
도 1a 내지 도 1f는 본 발명에 따른 반도체 소자의 금속 배선 형성방법을 설명하기 위한 소자의 단면도.1A to 1F are cross-sectional views of a device for explaining a method for forming metal wirings of a semiconductor device according to the present invention.
〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>
11 : 실리콘기판 12 : 층간절연막11 silicon substrate 12 interlayer insulating film
13 : 금속 라인 14 : 제 1 산화막13: metal line 14: first oxide film
15 : Si3N4막 16 : 제 2 산화막15 Si 3 N 4 film 16 Second oxide film
17 : 감광막 패턴 18 : 제 1 Cu막17 photosensitive film pattern 18 first Cu film
19 : Al층 20 : 제 2 Cu막19: Al layer 20: 2nd Cu film
21 : Al-Cu합금층21: Al-Cu alloy layer
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1f는 본 발명에 따른 반도체 소자의 금속 배선 형성방법을 설명하기 위한 소자의 단면도이다.1A to 1F are cross-sectional views of devices for explaining a method for forming metal wirings of a semiconductor device according to the present invention.
도 1a를 참조하면, 실리콘기판(11) 상에 층간 절연막(12)을 형성한 후 금속 라인(Line;13), 제 1 산화막(14), Si3N4막(15) 및 제 2 산화막(16)을 순차적으로 형성한다. 그후 전체 상부면에 Al-Cu 금속배선이 형성 될 위치에 감광막 패턴(17)을 형성한다.Referring to FIG. 1A, after forming the interlayer insulating film 12 on the silicon substrate 11, the metal line 13, the first oxide film 14, the Si 3 N 4 film 15, and the second oxide film ( 16) are formed sequentially. Thereafter, the photoresist pattern 17 is formed at a position where the Al-Cu metal wiring is to be formed on the entire upper surface.
도 1b는 감광막 패턴(17)을 마스크로 이용하여 2중 데머신(Dual Damscene) 법으로 식각공정을 실시하여 층모양으로 금속 라인(13)을 노출 시킨 후 감광막 패턴(17)을 제거한 상태의 단면도이다.FIG. 1B is a cross-sectional view of the photoresist pattern 17 having the photoresist pattern 17 removed by performing an etching process using a dual damscene method using the photoresist pattern 17 as a mask to expose the metal line 13 in a layer shape. to be.
도 1c는 전체 상부면에 이온화 금속 물리 기상증착 방법 또는 화학 기상증착 방법으로 제 1 Cu막(18)을 형성한 상태의 단면도이다. 이때, 이온화 금속 물리 기상증착 방법으로 제 1 Cu막(18)을 형성할 경우 타겟 전력을 1 내지 3 kW, 고주파 코일 전력을 1 내지 3kW, 압력을 10 내지 30 mTorr, 증착 온도를 100 내지 300℃ 에서 50 내지 200Å 두께로 형성한다.FIG. 1C is a cross-sectional view of the first Cu film 18 formed on the entire upper surface by an ionized metal physical vapor deposition method or a chemical vapor deposition method. At this time, when the first Cu film 18 is formed by the ionized metal physical vapor deposition method, the target power is 1 to 3 kW, the high frequency coil power is 1 to 3 kW, the pressure is 10 to 30 mTorr, and the deposition temperature is 100 to 300 ° C. At 50 to 200 mm thick.
또한, 화학 기상 증착 방법으로 제 1 Cu막(18)을 형성할 경우 50 내지 200℃의 온도에서 10 내지 30 mTorr의 압력과 0.25 내지 0.5 Å/sec 의 증착 속도로 50 내지 200Å 두께로 형성한다.In addition, when the first Cu film 18 is formed by a chemical vapor deposition method, the first Cu film 18 is formed to a thickness of 50 to 200 kPa at a pressure of 10 to 30 mTorr and a deposition rate of 0.25 to 0.5 kPa / sec at a temperature of 50 to 200 ° C.
또한, 제 1 Cu막(18)을 형성하기 전에 Cu 확산을 방지하고 표면 성질을 개선 하기 위하여 천이계열 금속 또는 금속의 질화물을 라이너(Liner)로 이용할 수 있다. 상기 라이너는 Ti, Ta, TiN, TaN 등을 500 내지 1000Å 두께로 형성한다.In addition, a transition-based metal or a nitride of a metal may be used as a liner to prevent Cu diffusion and improve surface properties before forming the first Cu film 18. The liner forms Ti, Ta, TiN, TaN, or the like to a thickness of 500 to 1000 mm 3.
도 1d는 DMAH(Dimethlyaluminum hydride)를 소오스 가스로 하고 50 내지 200℃ 의 온도 및 1 내지 5 torr 압력 하에서 Al층(19)을 증착한 후 제 2 Cu막(20)을 형성한 상태의 단면도이다.FIG. 1D is a cross-sectional view of a state in which a second Cu film 20 is formed after depositing an Al layer 19 using DMAH (Dimethlyaluminum hydride) as a source gas and at a temperature of 50 to 200 ° C. and a pressure of 1 to 5 torr.
도 1e는 제 1 및 2 Cu막(18 및 20)을 Al층(19)으로 확산하기 위하여 노(Furnace)에서 300 내지 500℃의 온도에서 열처리하여 Al-Cu 합금층(21)을 형성한 상태의 단면도이다.FIG. 1E shows a state in which the Al-Cu alloy layer 21 is formed by heat-treating the first and second Cu films 18 and 20 at a temperature of 300 to 500 ° C. in a furnace in order to diffuse the first and second Cu films 18 and 20 into the Al layer 19. It is a cross section of.
도 1f는 화학적 기계적 연마공정으로 제 2 산화막(16) 과 동일 높이가 되도록 평탄화 공정을 실시한 상태의 단면도이다.FIG. 1F is a cross-sectional view of the state where the planarization process is performed so as to be the same height as the second oxide film 16 by the chemical mechanical polishing process.
상술한 바와같이 본 발명에 따른 금속 배선 형성방법은 화학적 기상증착 방법으로 Al 배선 형성시 Cu를 합금화하므로 금속배선의 일렉트로 마이그레이션 (Electromigration) 현상이 저하되어 소자의 신뢰성 및 안정성이 향상되는 효과가 있다.As described above, the metal wiring forming method according to the present invention has an effect of improving the reliability and stability of the device by reducing the electromigration phenomenon of the metal wiring since Cu is alloyed when the Al wiring is formed by a chemical vapor deposition method.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990025426A KR20010004712A (en) | 1999-06-29 | 1999-06-29 | Method of forming a matal wiring in a semiconductor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990025426A KR20010004712A (en) | 1999-06-29 | 1999-06-29 | Method of forming a matal wiring in a semiconductor |
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| Publication Number | Publication Date |
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| KR20010004712A true KR20010004712A (en) | 2001-01-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019990025426A KR20010004712A (en) | 1999-06-29 | 1999-06-29 | Method of forming a matal wiring in a semiconductor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100900227B1 (en) * | 2006-12-07 | 2009-05-29 | 주식회사 하이닉스반도체 | Method for forming metal interconnection layer of semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03255632A (en) * | 1990-03-05 | 1991-11-14 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPH0669205A (en) * | 1992-04-27 | 1994-03-11 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH07273109A (en) * | 1994-03-30 | 1995-10-20 | Toshiba Corp | Semiconductor device |
| KR100219511B1 (en) * | 1996-12-31 | 1999-09-01 | 윤종용 | A metal line having an uniform diffusion distribution of copper & a method for forming the same |
-
1999
- 1999-06-29 KR KR1019990025426A patent/KR20010004712A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03255632A (en) * | 1990-03-05 | 1991-11-14 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPH0669205A (en) * | 1992-04-27 | 1994-03-11 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH07273109A (en) * | 1994-03-30 | 1995-10-20 | Toshiba Corp | Semiconductor device |
| KR100219511B1 (en) * | 1996-12-31 | 1999-09-01 | 윤종용 | A metal line having an uniform diffusion distribution of copper & a method for forming the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100900227B1 (en) * | 2006-12-07 | 2009-05-29 | 주식회사 하이닉스반도체 | Method for forming metal interconnection layer of semiconductor device |
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