KR0185299B1 - Forming method of metal wiring - Google Patents
Forming method of metal wiring Download PDFInfo
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- KR0185299B1 KR0185299B1 KR1019950069501A KR19950069501A KR0185299B1 KR 0185299 B1 KR0185299 B1 KR 0185299B1 KR 1019950069501 A KR1019950069501 A KR 1019950069501A KR 19950069501 A KR19950069501 A KR 19950069501A KR 0185299 B1 KR0185299 B1 KR 0185299B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
본 발명은 반도체 소자의 비아홀에서의 2차 금속배선 형성시, 층간 절연막의 구성요소인 평탄화를 위한 SOG막의 외부 확산을 방지하는 반도체 소자의 비아홀 매립 금속배선 형성방법을 제공하기 위한 것이다.The present invention provides a method for forming a via hole-embedded metal wiring in a semiconductor device which prevents external diffusion of an SOG film for planarization, which is a component of an interlayer insulating layer, when forming secondary metal wiring in a via hole of a semiconductor device.
이와 같은 본 발명의 금속배선 형성방법은 반도체 기판 상부의 제1산화막 위의 소정 부위에 형성된 제1금속배선 위에 제2 SOG막, 제3산화막을 순차적으로 적층하는 단계; 제3산화막의 소정 부위에 비아홀 형성을 위한 감광막 마스크를 형성하는 단계; 감광막 마스크를 식각장벽으로 하여 제1금속배선의 표면을 노출시키는 비아홀을 형성한 다음 감광막을 제거하는 단계; 스퍼터링 장치내에서 개스를 탈화시키기 위한 열처리를 소정온도에서 소정시간동안 실시하는 단계; 노출된 제1금속배선막의 표면에 생성된 물질을 탈화온도보다 낮은 소정조건에서 식각하는 단계; 전면에 비아홀을 매립할 정도의 두께로 금속배선막을 식각단계보다 낮은 온도에서 증착하는 단계를 포함하는 것을 특징으로 한다.The metal wiring forming method of the present invention comprises the steps of sequentially stacking the second SOG film, the third oxide film on the first metal wiring formed on a predetermined portion on the first oxide film on the semiconductor substrate; Forming a photoresist mask for forming a via hole in a predetermined portion of the third oxide film; Forming a via hole exposing the surface of the first metal interconnection using the photoresist mask as an etch barrier and then removing the photoresist; Performing a heat treatment for degassing the gas in the sputtering apparatus at a predetermined temperature for a predetermined time; Etching the material generated on the exposed surface of the first metal wiring film under a predetermined condition lower than the deoxidation temperature; And depositing a metal wiring film at a temperature lower than that of the etching step to a thickness sufficient to fill a via hole on the front surface.
Description
첨부한 도면은 본 발명의 실시예에 따른 반도체 소자의 비아홀 매립 금속배선을 형성하기 위한 공정 흐름도.The accompanying drawings are a process flow diagram for forming a via-hole buried metal wiring of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 제1산화막1: semiconductor substrate 2: first oxide film
3 : 제1금속배선막 4 : 고융점 금속막3: first metal wiring film 4: high melting point metal film
5 : 제2산화막 6 : SOG막5: second oxide film 6: SOG film
7 : 제3산화막 8 : 장벽 금속막7: third oxide film 8: barrier metal film
9 : 제2금속배선막 10 : 반사방지막9 second metal wiring film 10 antireflection film
20 : 감광막 마스크 30 : 비아홀20: photosensitive film mask 30: via hole
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 특히 비아홀이 형성되는 SOG막으로부터 비아홀 매립 금속막으로의 외부 확산을 방지하는 비아홀 매립 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a via hole-embedded metal wiring to prevent external diffusion from an SOG film in which via holes are formed to a via-hole buried metal film.
일반적으로 막의 증착에 사용되는 증착공정이라 함은 기상의 소스로부터 특정 원자나 분자를 고상화 시켜 필요로 하는 박막을 얻어 내는 일종의 물질 합성과정을 통칭한다. 반도체 소자의 제조에는 다결정 실리콘, 산화막, 질화막, 여러 종류의 금속 혹은 실리사이드 박막이 필요하며 이와 같은 박막들은 모두 증착공정에 의해서 형성된다.In general, the deposition process used for the deposition of a film refers to a kind of material synthesis process for obtaining a thin film required by solidifying specific atoms or molecules from a gaseous source. The manufacture of a semiconductor device requires a polycrystalline silicon, an oxide film, a nitride film, various metals or silicide thin films, all of which are formed by a deposition process.
증착공정은 박막 형성법(Thin Film Process)이라고 말할 수 있으며, 이는 크게 물리 증착법(Physical Vapor Deposition : PVD)과 화학 증착법(Chemical Vapor Deposition)으로 대별된다. 물리 증착은 소스로부터 임의 다른 성분이 더해지거나 감해지지 않고 상의 변환 과정만을 통하여 증착되는 것이다. 반면에 화학증착은 반응을 수반하기 때문에 소스와 증착 산물간에 물리화학적 구조의 차이가 있다.The deposition process may be referred to as a thin film process, which is roughly divided into physical vapor deposition (PVD) and chemical vapor deposition (Chemical Vapor Deposition). Physical deposition is the deposition through phase transformation only, without any other components being added or subtracted from the source. On the other hand, because chemical vaporization involves reaction, there is a difference in physicochemical structure between the source and the deposition product.
이러한 증착공정을 이용하여 반도체 소자에 사용되는 구성막으로는 크게 절연막과 도전막으로 구성되고, 절연막으로는 SiO2, PSG, BPSG와 같은 산화막과 SI3N4와 같은 질화막이 있으며, 물리증착법중의 일종인 회전 도포법(Spin Coating)의 원리를 이용한 SOG(Spin On Glass)와 PIQ(Polymide)가 있는데, SOG는 무기계의 실리사이드 SOG와 유기계의 실록산 SOG가 있다. 이러한 SOG는 주로 금속간 절연체(Intermetal Dielectric)용으로 적용된다. 한편, 폴리이미드는 평탄화 능력이 우수한 다층배선 층간절연막으로서, 두꺼운 막이 가능해서 알파선 저지막으로도 쓰인다.By using the deposition process, the constituent film used in the semiconductor device is largely composed of an insulating film and a conductive film. The insulating film includes an oxide film such as SiO2, PSG, BPSG, and a nitride film such as SI3N4. There are SOG (Spin On Glass) and PIQ (Polymide) using the principle of spin coating, and SOG includes inorganic silicide SOG and organic siloxane SOG. Such SOG is mainly applied for Intermetal Dielectric. On the other hand, polyimide is a multi-layered wiring interlayer insulating film having excellent planarization capability, and can be used as an alpha line blocking film because a thick film is possible.
이러한 막들이 적층되는 반도체 소자에서 전위를 인가해야 하는 활성영역이나 다층배선의 연결부에는 콘택홀(Contact Hole)이나 비아홀(Via Hole)과 같으 구멍들이 전기적인 연결을 위하여 뚫혀진다.In the semiconductor device in which the films are stacked, holes such as contact holes or via holes are drilled for electrical connection in the connection region of the active region or the multilayer wiring to which the potential is to be applied.
2층 이상의 다층금속배선을 위한 비아홀의 형성시, 비아홀이 형성되는 금속간 산화막 중의 하나로서 평탄화 막인 SOG(Spin On Glass)막은 그 특성상 금속배선 상부에서는 두께가 얇게 증착되고, 글로벌 단차 영역에서는 두껍게 증착되어 산화막의 평탄화에 많이 이용된다. 이러한 SOG공정의 사용시, 전면 식각 공정을 진행하지 않을 경우에는 비아 부위에 SOG산화막이 노출되는데, 후속공정에서 온도가 높을 경우에는 SOG물질이 비아 내부로 외부 확산(out diffusion)되어 비아 페일(fail)을 유발하는 문제저이 발생한다.When forming via holes for two or more layers of metallization, a SOG (Spin On Glass) film, which is a planarization film, is one of the intermetallic oxide films in which via holes are formed. It is used a lot in planarization of an oxide film. When using the SOG process, if the entire etching process is not performed, the SOG oxide film is exposed to the via site. If the temperature is high in the subsequent process, the SOG material is diffused out into the via and the via fails. There is a problem that causes.
따라서, 본 발명의 목적은 비아홀에서의 2차 금속배선 형성을 위한 금속박막의 증착시 개스의 탈화, 식각, 금속증착 등의 공정순서에서 처리온도를 점차적으로 낮추어주므로써, SOG막의 외부 확산을 최소화 할 수 있는 반도체 소자의 비아홀 매립 금속배선 형성방법을 제공하기 위한 것이다.Accordingly, an object of the present invention is to minimize the external diffusion of the SOG film by gradually lowering the processing temperature in the process sequence such as degassing, etching, and metal deposition during the deposition of the metal thin film for forming the secondary metal wiring in the via hole. The present invention provides a method for forming a via hole-filled metal wiring in a semiconductor device.
이와 같은 목적을 달성하기 위한 본 발명의 비아홀 매립 금속배선 형성방법은 반도체 기판 상부의 제1산화막 위의 소정 부위에 형성된 제1금속배선 위에 제2산화막, SOG막, 제3산화막을 순차적으로 적층하는 단계; 제3산화막의 소정 부위에 비아홀 형성을 위한 감광막 마스크를 형성하는 단계; 감광막 마스크를 식각장벽으로 하여 제1금속배선의 표면을 노출시키는 비아홀을 형성한 다음 감광막을 제거하는 단계; 스퍼터링 장치내에서 개스를 탈화시키기 위한 열처리를 소정온도에서 소정시간동안 실시하는 단계; 노출된 제1금속배선막의 표면에 생성된 물질을 탈화온도보다 낮은 소정조건에서 식각하는 단계; 전면에 비아홀을 매립할 정도의 두께로 금속배선막을 식각단계보다 낮은 온도에서 증착하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the method of forming a via hole-filled metal wiring according to the present invention comprises sequentially stacking a second oxide film, an SOG film, and a third oxide film on a first metal wiring formed on a predetermined portion on a first oxide film on a semiconductor substrate. step; Forming a photoresist mask for forming a via hole in a predetermined portion of the third oxide film; Forming a via hole exposing the surface of the first metal interconnection using the photoresist mask as an etch barrier and then removing the photoresist; Performing a heat treatment for degassing the gas in the sputtering apparatus at a predetermined temperature for a predetermined time; Etching the material generated on the exposed surface of the first metal wiring film under a predetermined condition lower than the deoxidation temperature; And depositing a metal wiring film at a temperature lower than that of the etching step to a thickness sufficient to fill a via hole on the front surface.
이하, 첨부된 도면을 참조하여 본 발명의 실시예에 따른 비아홀 매립 금속배선 형성방법을 설명하면 다음과 같다.Hereinafter, a method of forming a via hole buried metal wiring according to an embodiment of the present invention will be described with reference to the accompanying drawings.
첨부한 도면은 본 발명의 실시예에 따른 비아홀 매립 금속배선 형성방법을 설명하는 공정 흐름도이다.The accompanying drawings are process flow diagrams illustrating a method for forming a via hole buried metal wiring according to an embodiment of the present invention.
먼저, (a)에 도시한 바와 같이, 반도체 기판(1) 상부의 제1산화막(2) 위의 소정 부위에 형성된 제1금속배선(3)의 전면에 제2산화막(5)을 소정 두께만큼 증착한 다음, 상기 제2산화막(5) 위에 평탄화를 위한 SOG(Spin On Glass)막(6)을 소정 두께만큼 형성시킨다. 이 후, 상기 SOG막(6) 위에 제3산화막(7)을 소정 두께만큼 증착한 다음, 상기 제3산화막(7) 위으 소정 부분에 비아홀을 형성하기 위한 감광막 마스크(20)를 소정 두께로 도포한다. 상기 SOG막(7)의 증착후에는 필요에 따라 열처리 하는 단계르르 추가하는 것도 가능하다. 아울러, 여기서, 상기 제1금속배선은 알루미늄 합금막이나 구리막(3)만의 단층금속으로 되어 있거나, 알루미늄 합금막(3) 위에 반사 방지막(4)이 적층된 구조가 가능하나, 여기에서는 설명의 편의를 위하여 반사 방지막이 적층된 구조의 경우를 예를 들어 설명한다.First, as shown in (a), the second oxide film 5 is formed by a predetermined thickness on the entire surface of the first metal wiring 3 formed on the predetermined portion on the first oxide film 2 above the semiconductor substrate 1. After deposition, a spin on glass (SOG) film 6 for planarization is formed on the second oxide film 5 by a predetermined thickness. Thereafter, a third oxide film 7 is deposited on the SOG film 6 by a predetermined thickness, and then a photoresist mask 20 for forming a via hole is formed on the third oxide film 7 to a predetermined thickness. do. After the deposition of the SOG film 7, it is also possible to add a step of heat treatment as necessary. In addition, the first metal wiring may be made of a single layer metal of only an aluminum alloy film or a copper film 3, or may have a structure in which an anti-reflection film 4 is stacked on the aluminum alloy film 3. For convenience, the case of the structure in which the antireflection film is laminated is described as an example.
이 후, 상기 감광막 마스크(20)를 식각장벽으로 하여 금속박막(3)의 표면을 노출시키는 비아홀(30)을 비등방성 식각법에 의하여 형성한다. 상기 비아홀(30)의 형성후, 노출된 제1금속배선막(3) 표면에는 자연산화막(40)이 필연적으로 형성된다.Thereafter, via holes 30 exposing the surface of the metal thin film 3 using the photoresist mask 20 as an etch barrier are formed by an anisotropic etching method. After the via hole 30 is formed, a native oxide film 40 is inevitably formed on the exposed surface of the first metal wiring film 3.
다음으로, 스퍼터링 장치내에서 진공을 유지하면서 상기 자연산화막을 식각하고, 금속배선막을 증착하는 공정을 진행한다.Next, the natural oxide film is etched while the vacuum is maintained in the sputtering apparatus, and the metal wiring film is deposited.
먼저, 개스의 탈화(De-gassing)공정을 실시하는데, 이는 300 내지 500℃의 온도범위에서 1분이상 실시한다.First, a gas de-gassing process is performed, which is performed for at least 1 minute in a temperature range of 300 to 500 ° C.
다음으로, 상기 제1금속배선에서 생성된 자연산화막의 식각을 위하여 아르곤(Ar)을 공급개스, 10mTorr이하의 압력, 200 내지 400℃의 온도범위에서 30초 이상의 시간동안 식각을 행한다. 이 때의 식각을 위한 공정조건에서 식각시간은 형성된 물질을 완전히 제거할 때까지의 시간으로 결정하는 것이 바람직하다.Next, for etching the natural oxide film produced by the first metal wire, argon (Ar) is etched for 30 seconds or more in a supply gas, a pressure of 10 mTorr or less, and a temperature range of 200 to 400 ° C. In this case, the etching time is preferably determined by the time required to completely remove the formed material.
이 후, SOG막(6)의 비아홀 매립 금속층으로의 외부확산(out diffusion)을 방지하기 위한 장벽 금속막을 1,000Å 미만의 두께로 증착하는데, 상기 장벽 금속막은 Ti, Co, Ta, TiN의 고융점 금속에서 한 가지 이상을 선택적으로 형성하는 것이 바람직하다.Thereafter, a barrier metal film for preventing out diffusion into the via hole buried metal layer of the SOG film 6 is deposited to a thickness of less than 1,000 GPa, and the barrier metal film is formed of high melting points of Ti, Co, Ta, and TiN. It is desirable to selectively form one or more of the metals.
다음으로, 상기 장벽 금속막의 전면에 비아홀을 충분히 매립할 정도의 두께로 알루미늄 합금이나 구리금속막을 25 내지 200℃의 온도범위에서 증착한다. 이 후, 상기 알루미늄 합금이나 구리금속박막(9)의 전면에 반사방지막(10)을 400℃ 미만의 온도에서 1,000Å 미만의 두께로 증착한 다음, 감광막 마스크를 사진식각법에 의하여 형성한 다음, 식각공정에 의하여 금속배선 패턴을 형성한다.Next, an aluminum alloy or a copper metal film is deposited at a temperature in the range of 25 to 200 ° C. to a thickness sufficient to fill a via hole in the entire surface of the barrier metal film. Thereafter, the anti-reflection film 10 is deposited on the entire surface of the aluminum alloy or copper metal thin film 9 to a thickness of less than 1,000 Pa at a temperature of less than 400 ° C, and then a photoresist mask is formed by photolithography. The metallization pattern is formed by an etching process.
이상에서 설명한 바와 같이, 본 발명의 금속배선 형성방법은 비아홀을 매립하는 금속배선막의 형성전에 노출된 제1금속배선막의 표면에 형성된 자연산화막을 식각하여 제거해주고, 이 후의 매립을 위한 증착공정을 단계별로 온도를 낮추어 진행하므로써, 비아에서의 SOG막의 외부 확산을 방지할 수 있으며, 비아의 페일을 방지하여 소자의 신뢰성 및 수율을 증가시키는 효과를 제공한다.As described above, the metallization method of the present invention etches and removes the natural oxide film formed on the surface of the first metallization layer exposed before the formation of the metallization layer to fill the via hole, and then the deposition process for subsequent embedding. By proceeding by lowering the furnace temperature, it is possible to prevent the external diffusion of the SOG film in the via, and to prevent the via from failing, thereby providing an effect of increasing the reliability and yield of the device.
여기에서는 본 발명의 특정 실시예에 대해서 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Although specific embodiments of the present invention have been described and illustrated herein, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
Claims (13)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950069501A KR0185299B1 (en) | 1995-12-30 | 1995-12-30 | Forming method of metal wiring |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950069501A KR0185299B1 (en) | 1995-12-30 | 1995-12-30 | Forming method of metal wiring |
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| KR970052503A KR970052503A (en) | 1997-07-29 |
| KR0185299B1 true KR0185299B1 (en) | 1999-04-15 |
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