KR20010004308A - Method for forming feram - Google Patents
Method for forming feram Download PDFInfo
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- KR20010004308A KR20010004308A KR1019990024932A KR19990024932A KR20010004308A KR 20010004308 A KR20010004308 A KR 20010004308A KR 1019990024932 A KR1019990024932 A KR 1019990024932A KR 19990024932 A KR19990024932 A KR 19990024932A KR 20010004308 A KR20010004308 A KR 20010004308A
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- ferroelectric
- memory device
- upper electrode
- forming
- capacitor
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- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000003990 capacitor Substances 0.000 claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 claims abstract description 19
- 239000010410 layer Substances 0.000 claims abstract description 18
- 239000007789 gas Substances 0.000 claims abstract description 14
- 239000011229 interlayer Substances 0.000 claims abstract description 12
- -1 hydrogen ions Chemical class 0.000 claims abstract description 11
- 238000004140 cleaning Methods 0.000 claims abstract description 10
- 239000001301 oxygen Substances 0.000 claims abstract description 10
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000001257 hydrogen Substances 0.000 claims abstract description 9
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000001020 plasma etching Methods 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims description 9
- 229910002091 carbon monoxide Inorganic materials 0.000 claims description 4
- 230000001052 transient effect Effects 0.000 claims 1
- 238000003860 storage Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 25
- 230000035515 penetration Effects 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 230000010287 polarization Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005040 ion trap Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000011232 storage material Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/57—Capacitors with a dielectric comprising a perovskite structure material comprising a barrier layer to prevent diffusion of hydrogen or oxygen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체 메모리 소자 제조 방법에 관한 것으로, 특히 강유전체 메모리 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly to a method of manufacturing a ferroelectric memory device.
반도체 소자에서 강유전체(ferroelectric) 재료를 캐패시터에 사용함으로써 기존 DRAM 소자에서 필요한 리프레쉬(refresh)의 한계를 극복하고 대용량의 메모리를 이용할 수 있는 소자의 개발이 진행되어왔다.By using ferroelectric materials in capacitors in semiconductor devices, the development of devices capable of using a large-capacity memory while overcoming the limitation of refresh required in conventional DRAM devices has been in progress.
FeRAM(ferroelectric random access memory) 소자는 비휘발성 기억 소자의 일종으로 전원이 끊어진 상태에서도 저장 정보를 기억하는 장점이 있을 뿐만 아니라 동작 속도도 기존의 DRAM(dynamic random access memory)에 필적하여 차세대 기억소자로 각광받고 있다.A ferroelectric random access memory (FeRAM) device is a nonvolatile memory device that has the advantage of storing stored information even when the power supply is turned off, and its operation speed is comparable to that of a conventional dynamic random access memory (DRAM). Be in the spotlight.
SrBi2Ta2O9와 같은 강유전체는 상온에서 유전상수가 수백에서 수천에 이르며 두 개의 안정한 잔류분극(remnant polarization) 상태를 갖고 있어 이를 박막화하여 비휘발성(nonvolatile) 메모리 소자로의 응용이 실현되고 있다. 강유전체 박막을 비휘발성 메모리 소자로 사용하는 경우 가해주는 전기장의 방향으로 분극의 방향을 조절하여 신호를 입력하고 전기장을 제거하였을 때 남아있는 잔류분극의 방향에 의해 디지털 신호 1과 0을 저장하게 되는 원리를 이용하는 것이다.Ferroelectrics, such as SrBi 2 Ta 2 O 9 , have dielectric constants ranging from hundreds to thousands at room temperature, and have two stable remnant polarization states, making them thin and thin. . When ferroelectric thin film is used as a nonvolatile memory device, the signal is input by adjusting the direction of polarization in the direction of the electric field applied and the digital signals 1 and 0 are stored by the remaining polarization direction when the electric field is removed. To use.
FeRAM 소자의 축전물질로는 SrBi2Ta2O9(이하 SBT)와 Pb(Zr,Ti)O3(이하 PZT) 박막이 주로 사용된다. 상기와 같은 강유전체막의 우수한 강유전 특성을 얻기 위해서는 상하부 전극물질의 선택과 적절한 공정의 제어가 필수적이다.As the storage material of the FeRAM device, SrBi 2 Ta 2 O 9 (hereinafter referred to as SBT) and Pb (Zr, Ti) O 3 (hereinafter referred to as PZT) thin films are mainly used. In order to obtain the excellent ferroelectric properties of the ferroelectric film as described above, it is necessary to select the upper and lower electrode materials and control the appropriate process.
FeRAM 소자 제조 공정은 DRAM 제조 공정을 기초로하여 발전하였기 때문에 강유전체의 특성을 효과적으로 얻기가 어렵다.Since the FeRAM device manufacturing process has been developed based on the DRAM manufacturing process, it is difficult to effectively obtain the characteristics of the ferroelectric.
일예로 DRAM 제조 공정에서 캐패시터와 금속 배선(metal line) 연결을 위한 콘택홀 형성 공정(이하, 캐패시터 콘택홀 형성 공정이라 함)은 하층(sub layer)에 대한 식각 선택비를 개선하는 방향으로 개발되어 왔는데, 이러한 방법을 FeRAM 소자 제조에 바로 적용할 경우 캐패시터 콘택홀 형성 공정 이후에 실시되는 세정(cleaning) 공정에서 SBT 등과 같은 강유전체 내에 침투한 수소 이온이 강유전체의 산소 이온과 결합하여 강유전체 특성을 열화시키는 문제점이 있다.For example, in the DRAM manufacturing process, a contact hole forming process (hereinafter, referred to as a capacitor contact hole forming process) for connecting a capacitor and a metal line is developed to improve an etching selectivity for a sub layer. When the method is directly applied to the fabrication of FeRAM devices, hydrogen ions penetrated into ferroelectrics such as SBT are combined with oxygen ions of the ferroelectric to deteriorate ferroelectric properties in the cleaning process performed after the capacitor contact hole forming process. There is a problem.
도1은 종래 FeRAM 소자 제조 공정 단면도로서, 하부전극(12), 강유전체막(13), 상부전극(14)으로 이루어지는 캐패시터 형성이 완료된 기판(10) 상부에 절연을 위한 산화막(15)을 형성하고, 산화막(15)을 선택적으로 식각하여 상부전극(14)을 노출시키는 콘택홀(C1)을 형성한 상태를 보이고 있다. 도면부호 '11'은 층간절연막을 나타낸다.1 is a cross-sectional view of a conventional FeRAM device fabrication process, in which an oxide film 15 for insulation is formed on a substrate 10 on which a capacitor formed of a lower electrode 12, a ferroelectric film 13, and an upper electrode 14 is completed. In addition, the oxide layer 15 is selectively etched to form a contact hole C1 exposing the upper electrode 14. Reference numeral 11 denotes an interlayer insulating film.
FeRAM의 캐패시터 콘택홀 형성 과정은 DRAM 소자 제조 공정과 유사하게 캐패시터 상에 형성된 산화막을 C-F 계열의 가스를 이용하여 식각해서 콘택홀을 형성한다. DRAM에서는 캐패시터의 상부전극이 주로 폴리실리콘막으로 이루어지기 때문에 산화막 과도 식각시 산화막 하부층인 폴리실리층에 대한 선택비를 고려하여 식각제(etchant) 가스로 C-F 계열의 가스를 이용한다.In the process of forming a capacitor contact hole of FeRAM, an oxide film formed on a capacitor is etched using C-F-based gas to form a contact hole, similar to a DRAM device manufacturing process. In DRAM, since the upper electrode of the capacitor is mainly composed of a polysilicon film, C-F-based gas is used as an etchant gas in consideration of the selectivity to the polysilicon layer, which is the lower oxide layer, when the oxide film is excessively etched.
FeRAM 소자의 캐패시터의 상, 하부전극으로 주로 이용되는 백금(Pt)은 콘택홀 형성을 위한 산화막 식각시 산화막에 대한 선택비가 우수하므로, 식각 공정시 하층의 손상 보다는 수소 이온의 침투에 의한 강유전체의 특성 열화를 방지할 수 있어야 한다.Platinum (Pt), which is mainly used as the upper and lower electrodes of the capacitor of the FeRAM device, has a high selectivity to the oxide film during the etching of the oxide film for forming the contact hole. Therefore, the ferroelectric property due to the penetration of hydrogen ions rather than the damage of the lower layer during the etching process is excellent. It should be possible to prevent deterioration.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은, 캐패시터 콘택홀 형성 공정 후 실시되는 세정공정에서 수소 이온의 침투를 효과적으로 억제할 수 있는 강유전체 메모리 소자 제조 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a method of manufacturing a ferroelectric memory device that can effectively inhibit the penetration of hydrogen ions in the cleaning step performed after the capacitor contact hole forming step.
도1은 종래 기술에 따른 FeRAM 소자 제조 공정 단면도,1 is a cross-sectional view of the FeRAM device manufacturing process according to the prior art,
도2는 본 발명의 일실시예에 따른 FeRAM 소자 제조 공정 단면도.Figure 2 is a cross-sectional view of the FeRAM device manufacturing process according to an embodiment of the present invention.
*도면의 주요부분에 대한 도면 부호의 설명** Description of reference numerals for the main parts of the drawings *
22: 하부전극 23: 강유전체막22: lower electrode 23: ferroelectric film
24: 상부전극 C: 콘택홀24: upper electrode C: contact hole
상기와 같은 목적을 달성하기 위한 본 발명은 기판 상부에 하부전극, 강유전체막 및 상부전극으로 이루어지는 캐패시터를 형성하는 제1 단계; 상기 제1 단계가 완료된 전체 구조 상에 층간절연막을 형성하는 제2 단계; 및 산소계 가스를 이용한 플라즈마 식각으로 상기 층간절연막을 선택적으로 제거하여 상기 상부전극을 노출시키는 콘택홀을 형성하면서, 상기 상부전극 상에 산화막을 형성하는 제3 단계를 포함하는 강유전체 메모리 소자 제조 방법을 제공한다.The present invention for achieving the above object is a first step of forming a capacitor consisting of a lower electrode, a ferroelectric film and an upper electrode on the substrate; A second step of forming an interlayer insulating film on the entire structure of which the first step is completed; And forming a contact hole exposing the upper electrode by selectively removing the interlayer insulating layer by plasma etching using an oxygen-based gas, and forming an oxide layer on the upper electrode. do.
또한, 상기 제3 단계 후 세정 공정을 실시하면서 세정 공정 중 발생하는 수소 이온을 상기 산화막 내에 가두는 제4 단계를 더 포함하는 강유전체 메모리 소자 제조 방법을 제공한다.A method of manufacturing a ferroelectric memory device, the method may further include a fourth step of confining hydrogen ions generated during the cleaning process in the oxide film while performing the cleaning process after the third step.
본 발명은 캐패시터 콘택홀 형성 공정에서 산소계의 가스를 식각 가스로 사용하는데 특징이 있다. 이와 같이 산소계 가스를 이용한 식각으로 캐패시터 상부층을 식각하여 콘택홀 형성하면 상부전극 위에 100 Å 미만의 얇은 산화막이 생성되어 수소 이온 트랩층으로서 역할한다. 따라서, 이후 실시되는 세정 공정시에 발생할 수 있는 수소 이온의 침투를 최소화시킬 수 있다. 트랩층으로서 역할을 하는 산화막의 두께가 100 Å 미만이므로 콘택시 저항 상승은 미미하다.The present invention is characterized in that an oxygen-based gas is used as an etching gas in a capacitor contact hole forming process. As such, when the upper layer of the capacitor is etched by etching with oxygen-based gas to form a contact hole, a thin oxide film of less than 100 GPa is formed on the upper electrode to serve as a hydrogen ion trap layer. Therefore, it is possible to minimize the penetration of hydrogen ions that may occur in the cleaning process to be performed later. Since the thickness of the oxide film serving as the trap layer is less than 100 GPa, the increase in contact resistance is insignificant.
이하, 도2를 참조하여 본 발명의 일실시예에 따른 FeRAM 캐패시터 콘택홀 형성 방법을 상세하게 설명한다.Hereinafter, a method of forming a FeRAM capacitor contact hole according to an embodiment of the present invention will be described in detail with reference to FIG. 2.
도2에 도시한 바와 같이 트랜지스터 등의 형성이 완료된 전체 구조 상에 층간절연막(21)을 형성하고, 층간절연막(21) 상에 하부전극(22), 강유전체막(23), 상부전극(24)으로 이루어지는 캐패시터를 형성한다. 이때, 캐패시터의 상부전극은 Pt막 등으로 형성한다.As shown in FIG. 2, an interlayer insulating film 21 is formed on the entire structure of the transistor, etc., and the lower electrode 22, the ferroelectric film 23, and the upper electrode 24 are formed on the interlayer insulating film 21. As shown in FIG. A capacitor is formed. At this time, the upper electrode of the capacitor is formed of a Pt film or the like.
이어서, 캐패시터 형성이 완료된 기판(20) 상부에 산화막 등으로 층간절연막(25)을 형성하고, 산소계 가스를 이용한 플라즈마 식각 공정으로 층간절연막(25)을 선택적으로 제거하여 상부전극(24)을 노출시키는 콘택홀(C1)을 형성한다. 이러한 식각 과정에서 상부전극(24) 상에 100 Å 미만의 두께를 갖는 산화막(26)이 형성된다.Subsequently, an interlayer insulating film 25 is formed on the substrate 20 on which the capacitor formation is completed, using an oxide film or the like, and the upper electrode 24 is exposed by selectively removing the interlayer insulating film 25 by a plasma etching process using an oxygen-based gas. The contact hole C1 is formed. In this etching process, an oxide layer 26 having a thickness of less than 100 μs is formed on the upper electrode 24.
상기 식각 과정의 주식각 단계에서 O2, O3, CO, CO2등의 산소계 가스를 이용하고, 전체 가스에 대한 산소계 가스의 비율은 5 % 내지 50 %가 되도록 한다. 상기 산화막(26)은 과도 식각이 이루어지는 시점 즉, 상부전극(24)이 노출되는 시점부터 형성된다.Oxygen gas such as O 2 , O 3 , CO, CO 2 in the stock each step of the etching process, the ratio of the oxygen-based gas to the total gas is 5% to 50%. The oxide layer 26 is formed from the point where the excessive etching is performed, that is, when the upper electrode 24 is exposed.
이후, 세정 공정을 실시한다. 이때, 상부전극(24) 상에 형성된 산화막(26)이 세정 공정시 발생하는 수소 이온을 가두는 트랩층으로서 역할하기 때문에 강유전체막(23)의 특성 저하가 방지된다.Thereafter, a washing process is performed. At this time, since the oxide film 26 formed on the upper electrode 24 serves as a trap layer for trapping hydrogen ions generated during the cleaning process, deterioration of the characteristics of the ferroelectric film 23 is prevented.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 캐패시터 상부전극을 노출시키는 콘택홀 형성 후 세정 공정에서 발생할 수 있는 수소 이온이 강유전체막으로 침투하는 것을 방지하여 FeRAM의 특성이 열화되는 것을 억제함으로써 소자의 동작 특성을 향상시키고 제품에 대한 신뢰성을 높일 수 있다.The present invention made as described above improves the operation characteristics of the device by preventing the deterioration of the characteristics of the FeRAM by preventing the penetration of hydrogen ions that may occur in the cleaning process after forming the contact hole exposing the capacitor upper electrode to the ferroelectric film. It can increase the reliability of the product.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990024932A KR20010004308A (en) | 1999-06-28 | 1999-06-28 | Method for forming feram |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990024932A KR20010004308A (en) | 1999-06-28 | 1999-06-28 | Method for forming feram |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20010004308A true KR20010004308A (en) | 2001-01-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990024932A KR20010004308A (en) | 1999-06-28 | 1999-06-28 | Method for forming feram |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20010004308A (en) |
-
1999
- 1999-06-28 KR KR1019990024932A patent/KR20010004308A/en not_active Application Discontinuation
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