KR20010004303A - Method for forming feram - Google Patents

Abstract

PURPOSE: A method for manufacturing a ferroelectric memory device is provided to reduce the number of manufacturing steps, by forming a capacitor barrier layer without an additional processes for exposure, development and cleaning. CONSTITUTION: The second interlayer dielectric is formed on the entire structure having a transistor and the first interlayer dielectric covering the transistor. The second interlayer dielectric is selectively etched to form the first contact hole exposing a plate electrode of a capacitor. A barrier layer is formed on the entire structure. The barrier layer, the second interlayer dielectric and the first interlayer dielectric are selectively etched to form the second contact hole exposing an active region of the transistor. A metal layer is formed on the entire structure. The metal layer and barrier layer are patterned to form an interconnection wherein the barrier layer and the metal layer are stacked in the first contact hole and the metal layer is stacked in the second contact hole.

Description

Ferroelectric memory device manufacturing method {METHOD FOR FORMING FERAM}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly to a method of manufacturing a ferroelectric memory device.

By using a ferroelectric material in a capacitor in a semiconductor memory device, development of a device capable of using a large-capacity memory while overcoming the limitation of refresh required in a conventional dynamic random access memory (DRAM) device has been in progress. A ferroelectric random access memory (FeRAM) device is a nonvolatile memory device that not only stores stored information even when a power supply is cut off, but also has an operation speed comparable to that of a conventional DRAM.

SrBi ₂ Ta ₂ O ₉ (hereinafter referred to as SBT) and Pb (Zr, Ti) O ₃ (hereinafter referred to as PZT) thin films are mainly used as storage materials for ferroelectric memory devices. Ferroelectrics have dielectric constants ranging from hundreds to thousands at room temperature, and have two stable remnant polarization states, making them thinner and enabling their application to nonvolatile memory devices. Nonvolatile memory devices using a ferroelectric thin film use the principle of inputting a signal by adjusting the direction of polarization in the direction of an applied electric field and storing digital signals 1 and 0 by the direction of residual polarization remaining when the electric field is removed. .

As the ferroelectric material of the capacitor in the FeRAM element _{PZT, SBT, Sr x Bi y} (Ta i Nb j) 2 O 9 in the conventional case of using a ferroelectric having a perovskite (perovskite) structure, such as (the SBTN) Pt, Ir The upper electrode is formed of a metal such as Ru, Pt alloy, or the like.

Ferroelectric memory devices, such as DRAM, have a structure using polysilicon as a storage node, that is, a structure in which a ferroelectric film is formed on polysilicon. This is because the polysilicon is oxidized by the subsequent high temperature thermal process while forming the ferroelectric film and thus does not serve as an electrode.

Therefore, in the conventional ferroelectric memory device, as shown in FIG. 1, the aluminum wiring 21 is formed of the first metal wiring layer for connecting the MOSFET storage transistor 18 and the MOSFET transistor. In FIG. 1, reference numeral '10' denotes a silicon substrate, '11' denotes a field oxide film, '12' denotes a gate electrode, '13' denotes an insulating film spacer, '14' denotes a source drain, '15', and '22'. Is a first interlayer insulating film, '16' is a lower electrode, '17' is a ferroelectric film, '19' is a capacitor protective film, and '23' is a second metal wiring.

A method of manufacturing a ferroelectric memory device having a ferroelectric capacitor structure as shown in FIG. 1 will be described with reference to FIGS. 2A through 2E.

First, as shown in FIG. 2A, the upper portion of the silicon substrate 10 on which the field oxide film 11, the gate electrode 12, the insulating film spacer 13, the source drain 14, and the first interlayer insulating film 15 are formed. The capacitor and the capacitor protective film 19 which consist of the platinum lower electrode 16, the ferroelectric film 17, and the platinum upper electrode 18 are formed in this.

Next, as shown in FIG. 2B, the second interlayer insulating film 20 is formed on the entire structure, and the second interlayer insulating film 20 and the capacitor protective film 19 are selectively etched to expose the upper electrode 18. The TiN capacitor barrier layer 24 on the platinum upper electrode 18 so as to form a storage node contact hole C1 to suppress the reaction between Ti, Al and the platinum upper electrode of the first metal interconnection. To form. The TiN capacitor barrier layer 24 can prevent deterioration of ferroelectric properties that occur as Ti constituting the primary metal wiring is diffused into the ferroelectric capacitor.

Next, as shown in FIG. 2C, the second interlayer insulating film 20 and the first interlayer insulating film 15 are selectively etched to expose the active region of the transistor, that is, the active contact hole C2 exposing the source and drain 14. ). Subsequently, a wet etching process is performed. At this time, as the etching proceeds in the state in which the TiN capacitor barrier layer 24 is exposed, structural defects may occur due to adhesion and stress.

Next, as shown in FIG. 2D, a first metal wiring layer 21 for connecting the storage node 18 of the capacitor and the MOSFET transistor is formed. The first metal wiring layer 21 has a stacked structure of a Ti film and an Al film.

Next, as shown in FIG. 2D, a second interlayer insulating film 22 is formed over the entire structure, and a second metal wiring 23 is formed.

In the conventional ferroelectric memory device manufacturing process as described above, there is a step between the storage node contact hole C1 and the active contact hole C2, and the upper electrode is formed when the storage node contact hole C1 is formed. In order to prevent contamination of the equipment and deterioration of ferroelectric elements caused by the etching process, different materials such as the source and silicon of the source and drain are exposed in the active contact hole C2 formation. The process of forming C1 and the active contact hole C2 is divided to form a storage node contact hole having a relatively low depth, and then an active contact hole is formed.

In addition, as a TiN capacitor barrier layer 24 is formed on the platinum upper electrode 18 to suppress the reaction between Ti, Al and the platinum upper electrode of the first metal wiring, deposition, exposure, etching, cleaning processes, and the like. To be added, the TiN capacitor barrier film 24 is exposed in various cleaning processes, resulting in structural defects depending on the degree of adhesion and stress with the surrounding thin film.

The present invention has been made in order to solve the above problems is to provide a method for manufacturing a ferroelectric memory device that can easily form a capacitor barrier film for preventing the reaction between the metal wiring and the capacitor upper electrode without the addition of a process. .

1 is a cross-sectional view showing a structure of a conventional ferroelectric memory device;

2A to 2E are cross-sectional views of a ferroelectric memory device manufacturing process according to the prior art;

3A to 3F are cross-sectional views of a ferroelectric memory device fabrication process in accordance with one embodiment of the present invention.

* Description of reference numerals for the main parts of the drawings *

36: platinum lower electrode 37: ferroelectric film

38: upper electrode 41: TiN film

42: first metal wiring layer

The present invention for achieving the above object is a first step of forming a second interlayer insulating film on the transistor and the entire structure of the first interlayer insulating film covering the transistor is completed; Selectively etching the second interlayer insulating layer to form a first contact hole exposing an upper electrode of the capacitor; A third step of forming a barrier film on the entire structure of which the second step is completed; Selectively etching the barrier layer, the second interlayer dielectric layer, and the first interlayer dielectric layer to form a second contact hole exposing an active region of the transistor; A fifth step of forming a metal film on the entire structure in which the fourth step is completed; And a sixth step of patterning the metal layer and the barrier layer to form a connection wiring in which the barrier layer and the metal layer are stacked in the first contact hole and the metal layer is stacked in the second contact hole. Provided is a device manufacturing method.

After forming the storage node contact hole while the ferroelectric capacitor is covered with the insulating film, the TiN film for forming the capacitor barrier film is formed on the entire structure, and the TiN film and the lower insulating film are continuously etched to form an active contact hole. By depositing a first metal wiring layer having a Ti / TiN / Al stacked structure and simultaneously etching the first metal wiring layer and the capacitor barrier film, the TiN film capacitor barrier film is left in the storage node contact hole without the need for a separate exposure process and etching process. The other part is characterized in that it forms a connection wiring having a stacked structure of TiN / Ti / TiN / Al.

A method of fabricating a ferroelectric memory device according to an embodiment of the present invention will be described with reference to FIGS. 3A to 3F.

First, as shown in FIG. 3A, the upper portion of the silicon substrate 30 on which the field oxide film 31, the gate electrode 32, the insulating film spacer 33, the source drain 34, and the first interlayer insulating film 35 are formed. The capacitor and the capacitor protective film 39 which consist of the platinum lower electrode 36, the ferroelectric film 37, and the platinum upper electrode 38 are formed in this.

Next, as shown in FIG. 3B, a second interlayer insulating film 40 is formed on the entire structure, and the second upper interlayer insulating film 20 and the capacitor protective film 39 are selectively etched to expose the platinum upper electrode 38. A storage node contact hole C1 is formed, and a TiN film 41 is formed on the entire structure in order to suppress reaction between Ti and Al of the first metal wiring formed thereafter and the platinum upper electrode 38. . The TiN film 41 prevents deterioration of ferroelectric properties generated as Ti, which forms the primary metal wiring, is diffused into the ferroelectric capacitor.

Next, as illustrated in FIG. 3C, the TiN film 41, the second interlayer insulating film 40, and the first interlayer insulating film 35 are selectively etched to expose the active region of the transistor, that is, the source and drain 34. The active contact hole C2 is formed.

Next, as shown in FIG. 3D, the oxide film remaining on the bottom of the active contact hole C2 is etched by back sputtering in the metal film forming chamber to reduce the resistance of the active contact, and then the overall structure is reduced. The first metal wiring layer 42 for connecting the upper electrode 38 of the capacitor and the MOSFET transistor is formed on the substrate. The first metal wiring layer 42 has a stacked structure of a Ti film / TiN / Al film.

Next, as illustrated in FIG. 3E, the first metal wiring layer 42 and the TiN film 41 are selectively etched to stack the TiN film 41 and the first metal wiring layer 42 on the storage node contact C1. The first metal wiring is formed of a first metal wiring layer in the active contact (C2).

Next, as shown in Fig. 3F, a third interlayer insulating film 43 is formed over the entire structure, and a second metal wiring 44 is formed.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

The present invention made as described above has the effect of reducing the process step by forming a capacitor barrier film without a separate exposure, development and cleaning process.

Claims (3)

In the ferroelectric memory device manufacturing method, A first step of forming a second interlayer insulating film on the transistor and the entire structure in which the first interlayer insulating film covering the transistor is completed; Selectively etching the second interlayer insulating layer to form a first contact hole exposing an upper electrode of the capacitor; A third step of forming a barrier film on the entire structure of which the second step is completed; Selectively etching the barrier layer, the second interlayer dielectric layer, and the first interlayer dielectric layer to form a second contact hole exposing an active region of the transistor; A fifth step of forming a metal film on the entire structure in which the fourth step is completed; And Patterning the metal layer and the barrier layer to form a connection wiring in which the barrier layer and the metal layer are stacked in the first contact hole and the metal layer is stacked in the second contact hole. Ferroelectric memory device manufacturing method comprising a. The method of claim 1, The barrier film is formed of a TiN film, The metal film is a ferroelectric memory device manufacturing method, characterized in that formed in a stacked structure of Ti / TiN / Al film. The method according to claim 1 or 2, After the fourth step, And performing a back-sputtering in the same chamber as the metal film forming chamber to remove an oxide film on the bottom surface of the second contact hole.