KR20010004181A - Method for forming metal electrode in memory device - Google Patents
Method for forming metal electrode in memory device Download PDFInfo
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- KR20010004181A KR20010004181A KR1019990024801A KR19990024801A KR20010004181A KR 20010004181 A KR20010004181 A KR 20010004181A KR 1019990024801 A KR1019990024801 A KR 1019990024801A KR 19990024801 A KR19990024801 A KR 19990024801A KR 20010004181 A KR20010004181 A KR 20010004181A
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- oxidation
- memory device
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 title claims description 36
- 239000002184 metal Substances 0.000 title claims description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 15
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims abstract description 12
- 238000009792 diffusion process Methods 0.000 claims abstract description 10
- 239000010937 tungsten Substances 0.000 claims abstract description 10
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 9
- 230000003064 anti-oxidating effect Effects 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 150000004767 nitrides Chemical class 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910019001 CoSi Inorganic materials 0.000 claims description 3
- 229910008484 TiSi Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 229910010421 TiNx Inorganic materials 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 1
- 230000001052 transient effect Effects 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract description 10
- 238000007254 oxidation reaction Methods 0.000 abstract description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 4
- 239000001301 oxygen Substances 0.000 abstract description 4
- 229910052760 oxygen Inorganic materials 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- -1 Tungsten nitride Chemical class 0.000 abstract description 2
- 238000001465 metallisation Methods 0.000 abstract 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract 1
- 239000010408 film Substances 0.000 description 20
- 239000003963 antioxidant agent Substances 0.000 description 4
- 230000003078 antioxidant effect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910018999 CoSi2 Inorganic materials 0.000 description 1
- 229910008479 TiSi2 Inorganic materials 0.000 description 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/28141—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 고집적 메모리소자 제조방법에 관한 것으로, 특히 메탈(metal) 게이트전극(메모리소자의 워드라인) 또는 메탈 비트라인을 갖는 1Gb(giga bit)급 이상의 다이나믹램(DRAM : Dynamic Random access memory)과 같은 초고집적 메모리소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a highly integrated memory device, and more particularly, to 1Gb (giga bit) or more of dynamic random access memory (DRAM) having a metal gate electrode (word line of a memory device) or a metal bit line. The present invention relates to a method of manufacturing the same highly integrated memory device.
고집적화의 진전으로 3년에 메모리의 용량이 4배씩 증가되어 이미 1Gb(giga bit) DRAM의 개발이 이루어졌고 그 이상의 초고집적 DRAM에 대한 연구가 진행되고 있다. 이와 같이 DRAM의 집적도가 높아질수록 전기 신호를 읽고 기록하는 역할을 하는 셀의 면적은 1Gb의 경우 대략 0.08㎛2이다. 따라서, 이에 상응하는 워드라인 또는/및 비트라인의 요구선폭도 매우 감소하게 되었고, 그 결과 기존의 폴리실리콘 또는 단순한 실리사이드와 같은 워드라인 또는/및 비트라인(이하 워드라인 또는/및 비트라인을 전극이라 칭한다) 물질로는 1Gb급 이상의 DRAM에서 요구되는 미세선폭으로 낮은 저항값을 구현할 수 없게 되었다. 따라서, 아래 표1에 나타난 바와 같이 면저항(Rs)이 아주 적은 TiSi2, CoSi2, W, Mo, Al, Cu 등의 메탈로 전극을 형성하려는 연구가 꾸준히 진행되고 있다. 한편, 메탈 전극은 통상 폴리실리콘막과 메탈층 및 이 두 층 간의 확산 혹은 반응을 방지하기 위한 얇은 베리어메탈층의 3개층으로 구성되는바, 이들 종래에는 이들 박막들을 적층한 다음 마스크 및 식각 공정으로 적층된 박막들을 식각하므로써 패터닝하는 방법을 사용하고 있다.With the progress of high integration, memory capacity has increased by 4 times in 3 years, and 1Gb (giga bit) DRAM has already been developed, and further research on ultra-high density DRAM is being conducted. As the integration density of DRAM increases, an area of a cell that reads and writes an electrical signal is about 0.08 μm 2 for 1Gb. Accordingly, the required line widths of the corresponding word lines and / or bit lines are also greatly reduced, resulting in word lines or / and bit lines such as conventional polysilicon or simple silicides (hereinafter referred to as word lines or / and bit lines). With this material, it is impossible to realize low resistance due to the fine line width required in DRAMs of 1Gb or more. Therefore, as shown in Table 1 below, studies are being made to form electrodes with metals such as TiSi 2, CoSi 2, W, Mo, Al, and Cu having very low sheet resistance (Rs). Meanwhile, the metal electrode is generally composed of three layers of a polysilicon film, a metal layer, and a thin barrier metal layer for preventing diffusion or reaction between the two layers. In the related art, these thin films are stacked and then masked and etched. Patterning is performed by etching the stacked thin films.
그러나, 상술한 바와 같은 종래기술에서는 후속 산화 공정 진행시 배선 패턴으로 식각된 메탈측면에서 산화가 일어나서 후속 공정을 불가능하게 하는 요인이 되고 있다. 도1 및 도2는 W/WNx/Poly-Si 게이트를 0.2㎛ 및 1.0㎛ 디자인룰에 따라 형성한 상태에서 게이트 식각후 및 산화공정후의 각 사진을 나타낸 것이다.However, in the prior art as described above, the oxidation occurs on the metal side etched by the wiring pattern during the subsequent oxidation process, which makes the subsequent process impossible. 1 and 2 show the photographs after the gate etching and the oxidation process in the state where the W / WNx / Poly-Si gate is formed according to the 0.2 μm and 1.0 μm design rules.
또한, 이론적으로는 폴리실리콘막과 메탈중의 하나인 텅스텐(W)과의 산화되는 온도가 상이하여 선택적인 산화가 일정 영역에서 발생하는 것으로 되어 있으나, 공정을 위해 투여되는 반응개스의 미세 유량으로 인해 공정 진행시 조절이 거의 불가능하며, 재현성 역시 확보하지 못하고 있다.In addition, theoretically, since the oxidation temperature of the polysilicon film and tungsten (W), which is one of the metals, is different, selective oxidation occurs in a certain region, but at a minute flow rate of the reaction gas administered for the process. As a result, it is almost impossible to control the process, and reproducibility is not obtained.
본 발명은 상술한 바와 같은 종래기술의 문제점을 해결하기 위하여 안출된 것으로서, 메탈 전극(워드라인 또는/및 비트라인)의 산화방지를 위한 반도체메모리소자 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and an object thereof is to provide a method of manufacturing a semiconductor memory device for preventing oxidation of a metal electrode (word line or / and bit line).
도1 및 도2는 종래기술의 문제점을 보여주는 사진.1 and 2 are photographs showing the problems of the prior art.
도3a 내지 도3c는 본 발명의 일실시예에 따른 메탈 게이트전극 형성을 나타낸 공정 단면도.3A to 3C are cross-sectional views illustrating metal gate electrode formation in accordance with an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘기판; 2 : 게이트산화막1: silicon substrate; 2: gate oxide film
3 : 포리실리콘막 4 : 확산베리어메탈층3: polysilicon film 4: diffusion barrier metal layer
5 : 텅스텐막 6 : 마스크패턴5: tungsten film 6: mask pattern
7 : 산화방지층7: antioxidant layer
상기 목적을 달성하기 위하여 본 발명은 반도체메모리소자의 메탈 배선 형성방법에 있어서, 소정공정이 완료된 기판 상에 폴리실리콘막과 확산베리어메탈 및 배선용 메탈을 차례로 적층하는 제1단계: 상기 메탈 상에 마스크패턴을 형성하는 제2단계; 노출된 상기 메탈 및 상기 베리어메탈을 식각하는 제3단계; 상기 제3단계가 완료된 결과물의 전면에 산화방지층을 형성하고 비등방성 전면식각하는 제4단계; 및 노출된 상기 폴리실리콘막을 식각하는 제5단계를 포함하여 이루어진다.In order to achieve the above object, the present invention provides a method of forming a metal wiring of a semiconductor memory device, the first step of sequentially stacking a polysilicon film, a diffusion barrier metal and a metal for wiring on a substrate having a predetermined process: a mask on the metal Forming a pattern; A third step of etching the exposed metal and the barrier metal; A fourth step of forming an anti-oxidation layer on the entire surface of the resultant product of which the third step is completed and anisotropic full surface etching; And a fifth step of etching the exposed polysilicon film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도3a 내지 도3c는 본 발명의 일실시예에 따른 메탈 게이트전극 형성을 나타내는 공정 단면도이다. 본 실시예에서는 게이트전극 형성에 대해 설며하고 있지만 비트라인 공정에도 본 발명은 적용될 수 있으며, 또한 본 실시예에서는 전극으로 텅스텐 물질로서 적용하고 있지만, 이외의 TiSi2, CoSi2, W, Mo, Al, Cu 등의 메탈로 게이트전극을 형성할 경우에도 본 실시예는 적용될 수 있다.3A to 3C are cross-sectional views illustrating a metal gate electrode formation according to an embodiment of the present invention. In the present embodiment, the gate electrode formation is described, but the present invention can be applied to the bit line process, and in this embodiment, the electrode is applied as a tungsten material, but other TiSi2, CoSi2, W, Mo, Al, Cu The present embodiment can also be applied to the case of forming a gate electrode from a metal such as the like.
먼저, 도3a는 통상의 방법으로 실리콘기판(1) 상에 게이트산화막(2)과 폴리실리콘막(3), 예컨대 WNx 및 TiNx와 같은 확산베리어메탈층(4) 및 텅스텐막(5)을 차례로 적층 형성하고, 마스크패턴을 형성한 상태이다. 마스크패턴은 바로 포토리소그래피 공정을 적용하여 형성된 포토레지스트패턴이 될 수도 있고, 하드마스크 절연막이 될 수도 있다. 이후의 공정은 하드마스크 절연막일 때로 가정하여 계속 설명된다.First, FIG. 3A sequentially turns the gate oxide film 2, the polysilicon film 3, for example, a diffusion barrier metal layer 4 such as WNx and TiNx, and a tungsten film 5 onto the silicon substrate 1 in a conventional manner. It is a state which laminated | stacked and formed the mask pattern. The mask pattern may be a photoresist pattern formed by applying a photolithography process or may be a hard mask insulating film. Subsequent processes will be explained on the assumption that they are hard mask insulating films.
이어서, 도3b와 같이, 폴리실리콘층이 드러나도록 노출된 텅스텐막(5)과 그 하부의 확산베리어메탈층(4)을 식각한다. 이때 과도식각을 실시하지 않아도 무방하지만 도면에 도시된 바와같이 과도식각을 실시하여 폴리실리콘막(3)의 일부두께가 식각하는 것이 바람직하다. 이는 산소 침투를 방지하는데 더 효과적이기 때문이다. 계속해서, 산소침투에 의해 텅스텐막(5)이 산화되는 것을 방지하기 위한 산화방지층(7)을 형성한다. 산화방지층(7)은 산화막 또는 질화막 또는 메탈계절연막이 적용될 수 있다.Subsequently, as shown in FIG. 3B, the tungsten film 5 exposed to expose the polysilicon layer and the diffusion barrier metal layer 4 thereunder are etched. At this time, it is not necessary to perform the excessive etching, but as shown in the drawing, it is preferable that the partial thickness of the polysilicon film 3 is etched by performing the excessive etching. This is because it is more effective in preventing oxygen penetration. Subsequently, an antioxidant layer 7 for preventing the tungsten film 5 from being oxidized by oxygen infiltration is formed. The antioxidant layer 7 may be an oxide film, a nitride film, or a metal-based insulating film.
이어서, 도3c와 같이, 비등방성 전면 식각에 의해 산화방지층(7)을 식각하고 계속해서 드러난 폴리실리콘막(3)을 식각한다.Subsequently, as shown in FIG. 3C, the anti-oxidation layer 7 is etched by anisotropic front etching, and the polysilicon film 3 subsequently exposed is etched.
이후, 후속 공정으로 산화공정이 실시되는데, 텅스텐막(5)은 산화방지층으로 완벽히 가려져 있기 때문에 산소침투가 방지되어 산화되지 않는다.Subsequently, an oxidation process is performed in a subsequent process. Since the tungsten film 5 is completely covered by the antioxidant layer, oxygen penetration is prevented and does not oxidize.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
소자가 고집적화되어 가면서 메탈 게이트전극의 적용은 필수적으로 필요한바, 본 발명은 메탈 게이트 적용시 필연적으로 두따르는 메탈 산화문제를 방지하여 고집적 소자의 신뢰성을 향상시키는 효과가 있다.As the device is highly integrated, the application of the metal gate electrode is indispensable. The present invention has an effect of improving the reliability of the highly integrated device by preventing a metal oxidation problem that inevitably occurs when applying the metal gate.
Claims (7)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100780778B1 (en) * | 2006-12-28 | 2007-11-30 | 주식회사 하이닉스반도체 | Method of fabricating matal gate in semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100780778B1 (en) * | 2006-12-28 | 2007-11-30 | 주식회사 하이닉스반도체 | Method of fabricating matal gate in semiconductor device |
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