JP2002261256A - Semiconductor device and manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce resistances of word lines, to suppress junction leakage, to reduce the contact resistance and dimensions of a DRAM cell by increasing contact areas between diffused layers and drawing-out electrodes, to secure withstand voltage between the word lines and the drawing-out electrodes, and to suppress a short channel effect by extending an effective channel length in a DRAM, and to stabilize transistor characteristics. SOLUTION: This semiconductor device has word lines 16, which are embedded via gate insulating films 15 in grooves 14 formed in a semiconductor substrate 11 and in element isolation regions 12 formed in the semiconductor substrate 11, first diffused layers 13 formed on the semiconductor substrate 11 surface side of the sidewalls of the grooves 14, silicide layers 18 formed on the upper layers of the word lines 16, and drawing-out electrodes 21 which are connected with the first diffused layers 13, while overlapping the word lines 16 via first insulating films 19. The word lines 16 are formed in the grooves 14, and the impurity concentrations of the first diffused layers 13 are reduced gradually in the depth directions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a DRAM (Dynamic Rand).
om Access Memory).

[0002]

2. Description of the Related Art With the competition for miniaturization accelerated year by year, a composite device having a large capacity DRAM and a high-speed logic element mounted on one chip has been developed. That DR
As an example of the AM configuration, a memory cell gate of a DRAM is stacked on a substrate, and a so-called self-aligned contact is used to take out a diffusion layer of a memory cell transistor.

[0003]

However, various problems have also become apparent in stacked DRAMs.

In order to maintain transistor performance, DRA
As the M memory cell shrinks, the substrate concentration becomes higher and the junction leakage in the DRAM region is approaching a severe state. For this reason, it has become difficult to suppress junction leakage in megabit DRAMs. That is, it has become difficult to maintain the data retention characteristics of the DRAM, which was conventionally controllable with a margin. In this situation, there is no effective means other than increasing the capacitor capacity for each generation.

[0005] Further, with the shrinking of DRAM cells,
The contact area between the diffusion layer and the extraction electrode is reduced, and the contact resistance is increased twice as much in each generation. In the generations after 0.1 μm, the contact resistance is expected to be several kilo-ohms, which is expected to be comparable to the on-resistance of the word transistor of the memory cell. Therefore, not only the cell transistor but also the variation in the contact resistance severely affects the operation of the DRAM, and a higher precision is required in manufacturing.

Further, with the reduction in the size of DRAM cells,
The interlayer insulation distance between a word line and a contact for taking out a diffusion layer formed beside the word line is approaching with each generation. In manufacturing a megabit DRAM, the critical distance is said to be 20 nm to 30 nm in order to ensure this withstand voltage. Therefore, in a DRAM of a generation of 0.1 μm or less, it is necessary to form a contact for taking out the diffusion layer at a distance equal to or less than the withstand voltage limit distance.

Conventionally, tungsten silicide (WSi
₂ ) The word line of the DRAM, which has been suppressed in delay by adopting the polycide structure of doped polysilicon, has become stricter in aspect ratio with recent miniaturization, and has a sufficiently low resistance to suppress the word line delay. Has become difficult to obtain. Stacked DR that requires especially high-speed operation
In AM and the like, this word line delay becomes a serious problem affecting the access time of the DRAM. As a technique for reducing the resistance of the gate, reduction in the resistance of the wiring by salicide has been put to practical use. However, in order to apply to the gate of the DRAM memory cell, salicide is not formed in the diffusion layer of the DRAM in order to obstruct the reduction of the DRAM memory cell due to the inability to use the offset silicon oxide film and to maintain the data retention characteristics. It cannot usually be adopted due to difficulties such as requiring a process.

[0008] As described above, in the present 0.18 µm generation, even if the technology is somehow acceptable, it will be required in the future to achieve a 0.1 µm size.
For the 1 μm generation and beyond, some countermeasures are required, and in order to maintain the chip performance trend, a stacked D
It is expected that a drastic improvement in the RAM structure will be required.

[0009]

SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device and a method of manufacturing the same to solve the above-mentioned problems.

A semiconductor device according to the present invention includes a semiconductor substrate and a word line buried in a trench formed in an element isolation region formed in the semiconductor substrate via a gate insulating film, and the semiconductor on a sidewall of the trench. A semiconductor device having a diffusion layer formed on a substrate surface side, wherein the silicide layer formed on an upper layer of the word line and the diffusion layer overlapped with the word line via an insulating film on the word line. And an extraction electrode connected to the Also,
The diffusion layer is formed so that the impurity concentration decreases in the depth direction.

In a semiconductor device in which a memory element and a logic element are formed on the same semiconductor substrate, the transistor of the memory element is formed in a groove formed in a semiconductor substrate and an element isolation region formed in the semiconductor substrate. A word line buried via a gate insulating film, and a diffusion layer formed on the side of the trench on the surface of the semiconductor substrate, and a silicide layer formed on the word line;
An extraction electrode connected to the diffusion layer so as to overlap the word line via an insulating film on the word line, wherein a transistor of the logic element is formed on a diffusion layer of the transistor of the logic element. It has a silicide layer.

In the above semiconductor device, since the silicide layer is formed on the word line, the resistance of the word line is reduced, and the problem of delay is avoided. Further, since the silicide layer is formed on the diffusion layer of the logic element, the contact resistance to this diffusion layer is reduced.

In addition, since an extraction electrode is provided on a word line embedded in a semiconductor substrate via a gate insulating film and connected to a diffusion layer in a state of overlapping with the word line via an insulating film, a word electrode is provided. 20 insulating films on the wire
It is possible to secure a sufficient film thickness of nm to 30 nm or more, whereby the withstand voltage between the word line and the extraction electrode connected to the diffusion layer is secured.

Since the word line is buried in the semiconductor substrate via the gate insulating film and the diffusion layer is formed on the surface of the semiconductor substrate, the channel is formed on the semiconductor substrate on the bottom side of the groove where the word line is formed. Is formed so as to go around. Therefore, a sufficient effective channel length is ensured, so that a back bias is applied to stabilize transistor characteristics of a memory element (for example, a DRAM) having a severe short channel effect. Furthermore, the extraction electrode can be connected to the entire region of the diffusion layer on the surface side of the semiconductor substrate, and the contact resistance can be reduced.

Further, since the impurity concentration of the diffusion layer in the DRAM region decreases in the depth direction, the electric field at the junction can be alleviated, and the performance of the data retention characteristics is maintained.

According to a method of manufacturing a semiconductor device of the present invention, after forming an element isolation region in a semiconductor substrate, a diffusion layer is formed on the surface of the semiconductor substrate, and a diffusion layer is formed at a predetermined position in the semiconductor substrate and the element isolation region. Forming a trench, forming a gate insulating film in the trench, forming a word line so as to fill the trench while leaving an upper portion of the trench, and forming the trench on the word line. Forming a sidewall insulating film on a side wall, forming a silicide layer on the word line, forming an insulating film so as to fill an upper portion of the groove, and forming the insulating film on the word line via the insulating film. Forming a connection hole reaching the diffusion layer in a state of overlapping with the word line, and forming an extraction electrode in the connection hole. Further, the diffusion layer is formed so that the impurity concentration is reduced in the depth direction.

Further, in a method of manufacturing a semiconductor device in which a memory element and a logic element are formed on the same semiconductor substrate, an element isolation region is formed in the semiconductor substrate, and then a first element is formed on the semiconductor element surface side of the memory element region. Forming a diffusion layer;
Forming a groove at a predetermined position in the semiconductor substrate and the element isolation region in the memory element region, forming a gate insulating film in the groove and on the surface of the semiconductor substrate; Forming a word line so as to fill the trench, forming a gate electrode on the semiconductor substrate in the logic element region via the gate insulating film, and forming a gate electrode on both sides of the gate electrode. Forming a second diffusion layer, forming a sidewall insulating film on the trench side wall on the word line, forming a silicide layer on the word line layer and the second diffusion layer. Forming an insulating film filling the upper part of the groove, and reaching the first diffusion layer on the word line in a state of overlapping with the word line via the insulating film. It includes a step of forming a connection hole, and forming an electrode extraction into the connection hole.

In the method of manufacturing a semiconductor device, since the silicide layer is formed on the word line, the resistance of the word line is reduced, and the problem of delay is avoided. Further, since the silicide layer is formed on the diffusion layer of the logic element, the contact resistance to this diffusion layer is reduced.

A word line is buried in a groove formed in the semiconductor substrate through a gate insulating film, leaving an upper part of the groove, and a diffusion layer is formed on a side wall of the groove on the surface of the semiconductor substrate. Forming an insulating film so as to bury the upper portion of the groove, and forming a connection hole reaching the diffusion layer in a state of overlapping with the word line via the insulating film on the word line, so that the connection hole is formed in the connection hole. The formed extraction electrode and the word line are separated by an insulating film, and the insulating film can have a sufficient thickness of, for example, 20 nm to 30 nm or more. Therefore, it is possible to ensure the withstand voltage between the word line and the extraction electrode connected to the diffusion layer.

Since a word line (gate electrode) is buried in a groove formed in the semiconductor substrate via a gate insulating film and a diffusion layer is formed on the surface of the semiconductor substrate, the channel is formed by the word line (gate electrode). It is formed so as to go around the formed semiconductor substrate on the bottom side of the groove. Therefore, since the effective channel length is sufficiently ensured, the back bias is applied to the memory element (D
The transistor characteristics of the (RAM) section are stabilized. Furthermore, the extraction electrode can be connected to the entire region of the diffusion layer on the surface side of the semiconductor substrate, and the contact resistance can be reduced.

Further, since the diffusion layer in the memory element (DRAM) portion is formed so that the impurity concentration decreases in the depth direction, the electric field at the junction can be reduced, and the DRA can be reduced.
The performance of the data retention characteristic, which becomes more severe with the reduction in the cell size in the M region, is maintained.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor device according to the present invention will be described with reference to the schematic sectional view of FIG. In this embodiment, an example of a memory element (DRAM) which is mounted together with a logic element will be described as an example.

As shown in FIG. 1, a semiconductor substrate 11 has
An element isolation region 12 for isolating a memory element region (hereinafter referred to as a DRAM and referred to as a DRAM region in the drawing), a standard voltage logic region, a high voltage logic region, and the like is formed. This element isolation region 12 is formed, for example, by STI (Shal
low Trench Isolation) technology, for example, 0.1
It is formed at a depth of about μm to 0.2 μm. In the DRAM region on the semiconductor substrate 11, a buffer layer 72 is formed of, for example, a silicon oxide film to a thickness of 20 nm to 30 nm.

In the upper layer of the semiconductor substrate 11, a DRAM
A first diffusion layer (diffusion layer) 13 serving as a source / drain of the memory cell transistor is formed. This first
The diffusion layer 13 is formed by, for example, ion implantation using phosphorus as an impurity, setting the dose to 1 × 10 ¹³ / cm ^{2 to} 5 × 10 ¹³ / cm ² and the acceleration voltage to 10 keV to 40 keV.

In the buffer layer 72, the semiconductor substrate 11, and the element isolation region 12, a groove 14 has a thickness of, for example, 50 nm.
It is formed to a depth of about 100 nm. This groove 14
Is formed in a so-called round shape. A word line (including a gate electrode) 16 is formed in the groove 14 with a gate insulating film 15 interposed therebetween. The word line 16 has a lower layer formed of a polysilicon layer,
The upper layer is formed of a silicide (for example, salicide) layer 18. The distance at which the breakdown voltage with respect to the extraction electrode 21 described later is ensured is at least 30 nm or more from the surface of the semiconductor substrate 11 above the groove 14.
0 nm or less, preferably 40 nm or more and 50 nm or less, is formed in a lowered state. In this embodiment, for example, it is formed in a state of being lowered by about 50 nm. Note that there is no problem even if a slight difference occurs between the depth of the groove 14 formed in the semiconductor substrate 11 and the depth of the groove 14 formed in the element isolation region 12.

Further, a sidewall insulating film 17 is formed of, for example, a silicon nitride film on the side wall of the trench 14 on the polysilicon layer of the word line 16. Further, the silicide layer 18 is formed above the polysilicon layer 16p. As the silicide layer 18, for example, cobalt silicide (CoSi ₂ ), titanium silicide (TiSi ₂ ), nickel silicide (NiSi ₂ ), or the like can be used. Note that the depth of the groove 14 formed in the semiconductor substrate 11 and the depth of the groove 14
There is no problem even if there is some difference in the depth.

Further, the semiconductor at the bottom of the groove 14
A channel diffusion layer (not shown) is formed on the substrate 11.
I have. The channel diffusion layer has a high concentration (for example, 1.0 ×
10 ¹⁸/ Cm^Three~ 1.0 × 10¹⁹/ Cm^Three)
The bottom of the groove 14 in which the semiconductor substrate 11 is dug down
Formed in the portion of the semiconductor substrate 11 of FIG.
The side wall and upper part of 14 may have almost the same substrate concentration.
The region has a very low density (eg, 1.0 × 10¹⁶/ Cm^Three~
1.0 × 10¹⁸/ Cm^Three).

The gate insulating film 15 has a slightly larger film thickness than a state-of-the-art logic transistor, and has a slightly longer gate length. A membrane application is possible.
Therefore, the gate insulating film 15 in the DRAM region is
For example, it is formed of a silicon oxide film having a thickness of about 1.5 nm to 2 nm.

Therefore, the first diffusion layer 13 in the DRAM region is formed on the surface of the semiconductor substrate 11 above the side wall of the groove 14. The concentration of the bottom of the first diffusion layer 13 is set to be as low as possible.
It is desirable to alleviate the electric field between them. Originally, the semiconductor substrate 11 side is set to have a low concentration at the junction of the first diffusion layer 13, so that together with the first diffusion layer 13,
A low electric field strength junction is formed. This junction maintains the DRAM data retention characteristics.

As described above, the word line (gate electrode) 16 is embedded in the semiconductor substrate 11 via the gate insulating film 15 and the first diffusion layer 13 is formed on the surface of the semiconductor substrate 11. The channel is formed so as to go around the semiconductor substrate 11 on the bottom side of the groove 14 where the word line (gate electrode) 16 is formed. Therefore, an effective channel length can be ensured, and a transistor characteristic of a DRAM cell having a severe short channel effect can be stabilized by applying a back bias.

On the other hand, standard voltage logic transistors are formed in the standard voltage logic area. That is, the gate electrode 51 is formed on the semiconductor substrate 11 with the gate insulating film 15 interposed therebetween. Side walls 54 are formed on the side walls of the gate electrode 51, and low concentration diffusion layers 52, 52 are formed in the semiconductor substrate 11 below the side walls 54.
Second diffusion layers 55, 55 are formed on the semiconductor substrate 11 on both sides of the gate electrode 51 via the second diffusion layer 52. This second
A silicide layer 58 is formed above the diffusion layers 55 and 55. The silicide layer 58 is formed, for example, simultaneously with the silicide layer 18. A gate electrode (gate wiring) 51 having the same structure as the gate electrode 51 is formed on the element isolation region 12 in the logic region.

In the high voltage logic area, a high voltage logic transistor is formed. That is, the gate electrode 61 is formed on the semiconductor substrate 11 with the gate insulating film 15 interposed therebetween. Side walls 64 are formed on the side walls of the gate electrode 61, and low concentration diffusion layers 62, 62 are formed in the semiconductor substrate 11 below the side walls 64, and the low concentration diffusion layers 62, 62 The semiconductor substrate 11 on both sides of the gate electrode 61 has a third
Are formed. A silicide layer 68 is formed on the third diffusion layers 65 and 65. The silicide layer 68 is formed, for example, simultaneously with the silicide layer 18.

A first insulating film (insulating film) 19 is formed on the entire surface of the semiconductor substrate 11. The surface of the first insulating film 19 is flattened. The first insulating film 1
A connection hole 20 reaching the first diffusion layer 13 in the DRAM region is formed on 9. The connection hole 20 is desirably formed as large as possible in diameter so that the extraction electrode can be brought into contact with the entire surface of the first diffusion layer 13. Thereby, the contact resistance is reduced. Also, in the drawings, a state where the alignment is slightly misaligned is intentionally described. However, unless excessive overetching is performed when the connection hole is opened, a physical distance of the word line extraction electrode formed in the connection hole 20 is secured. It is possible to do. In the projection design viewed from above, the connection hole 20 completely overlaps the word line (gate electrode) 16. An extraction electrode 21 made of, for example, phosphorus-doped polysilicon is formed in the connection hole 20.

Further, on the first insulating film 19, a second insulating film 22 covering the extraction electrode 21 is formed. Bit contact holes 23 are formed in the second insulating film 22. A bit line 24 is formed on the second insulating film 22, and a part of the bit line 24 is connected to the extraction electrode 21 through the bit contact hole 23. The bit line 24 is formed by a metal wiring, an adhesive layer 24a is formed below the bit line 24, and an offset insulating film 25 is formed above the bit line 24.

On the second insulating film 22, an etching stopper layer 26 covering the bit line 24 and a third insulating film 27 are formed. The surface of the third insulating film 27 is flattened. A connection hole 28 is formed in the third insulating film 27 so as to connect to the extraction electrode 21, and a side wall insulating film 29 is formed in the connection hole 28 to insulate the bit line 24 from the connection hole 28. . Further, a plug 30 is formed in the connection hole 28.

A fourth insulating film 31 is formed on the third insulating film 27. In the fourth insulating film 31, a recess 32 in which a capacitor is formed is formed at the bottom so that the upper surface of the plug 30 is exposed. In the concave portion 32, an MIM (Metal / insulator /
Metal) capacitor 33 is formed. MI
The M-structure capacitor 33 is expected to be indispensable for DRAMs of 0.1 μm or less. At present, for example, ruthenium (Ru) and ruthenium oxide (RuO) -based materials are used for electrodes, and BST (BST) is used for dielectric films. BaTiO ₃ and S
A film of a mixed crystal with rTiO ₃ ) is employed.

On the fourth insulating film 31, the MIM
A fifth insulating film 34 covering the capacitor 33 having the structure is formed. The surface of the fifth insulating film 34 is flattened. The fifth insulating film 34 to the first insulating film 19 include a capacitor lead electrode, a word line lead electrode,
Connection holes 35, 36, 37, 101, 102, and 10 for forming bit line extraction electrodes, diffusion layer extraction electrodes in the logic region, gate extraction electrodes in the logic region, and the like.
3, 104, 105, etc. are formed, and each connection hole 35, 3
6, 37, 101, 102, 103, 104, 105, etc., a capacitor lead electrode 38, a word line lead electrode 39, a bit line lead electrode 40, a diffusion layer lead electrode 105, 106, 107, 108 in a logic area, a logic. A gate extraction electrode 109 and the like in the region are formed.

Further, a sixth insulating film 41 is formed on the fifth insulating film 34. In the sixth insulating film 41, a wiring groove 42 reaching each of the electrodes 38 to 40, 105 to 109, and the like is formed, and a first wiring 43 is formed in each of the wiring grooves 42. The first wiring 43 is made of, for example, a copper wiring. Although not shown, an upper layer wiring is further formed as necessary. The electrodes 38 to 40, 105 to 10
A well-known adhesion layer and barrier layer are formed on the wiring 9 and the wiring 42 depending on the material of the electrode, the wiring, and the insulating film.

Although the semiconductor device 1 includes a DRAM, a standard voltage logic element, and a high voltage logic element, the semiconductor device 1 may include only the DRAM.

In the semiconductor device 1, the first diffusion layer 13
Since the impurity concentration decreases in the depth direction, the electric field at the junction can be reduced, and the performance of data retention characteristics is maintained.

In the semiconductor device 1, the word line (gate electrode) 16 is formed on the semiconductor substrate 11 via the gate insulating film 15.
Is embedded and the first diffusion layer 13 is formed on the surface side of the semiconductor substrate 11, so that the channel goes around the semiconductor substrate 11 on the bottom side of the groove 14 in which the word line (gate electrode) 16 is formed. Is formed. for that reason,
Since a sufficient effective channel length is ensured, the transistor characteristics of a DRAM having a severe short channel effect are stabilized by applying a back bias.

In the semiconductor device 1, the extraction electrode 21
Can be connected to the entire surface of the first diffusion layer 13 on the surface of the semiconductor substrate 11, and the contact resistance of the diffusion layer can be suppressed to the lowest resistance achievable by the cell design.
Further, since the entire diffusion layer in the DRAM region is used as a contact, the effective area can be used effectively. Therefore, the cell area can be reduced.

In the semiconductor device 1, the gate insulating film 15
The word line 1 is embedded on the word line 16 embedded in the semiconductor substrate 11 through the first insulating film (insulating film) 19.
6, the first insulating film 19 on the word line 16 has a sufficient thickness of 20 nm to 30 nm or more because the extraction electrode 21 connected to the first diffusion layer 13 is provided so as to overlap the first diffusion layer 13. Accordingly, the withstand voltage between the word line 16 and the extraction electrode 21 connected to the first diffusion layer 13 can be ensured.

Since the semiconductor device 1 employs a salicide structure for the word line 16 of the DRAM, the resistance of the word line 16 can be reduced, and the problem of the delay of the word line 16 which is a problem in miniaturization can be avoided. can do. In addition, a third diffusion layer 65 above the second diffusion layer 55 in the logic region.
Since the silicide layers 58 and 68 are formed in the upper layer, the contact resistance to the second diffusion layer 55 and the third diffusion layer 65 is reduced.

Next, an example of an embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to the schematic sectional views of FIGS. In this embodiment, an example of a DRAM mixed with a logic element is described as an example. FIG.
16 to 16, the same reference numerals are given to the same components as those described with reference to FIG.

As shown in FIG. 2A, for example, STI
(Shallow Trench Isolation) technology, an element isolation region 1 for isolating a memory element region (hereinafter, referred to as a DRAM and referred to as a DRAM region), a standard voltage logic region, a high voltage logic region, and the like on a semiconductor substrate 11.
Form 2

After the formation of the resist film 91, the resist film 91 on the DRAM region is removed by using a lithography technique while leaving the resist film 91 on the logic region. Although the drawing shows the semiconductor substrate 11 on which the buffer layer 71 made of silicon oxide is formed, the buffer layer 71 is not required in some cases. The element isolation region 12 is formed at a depth of about 0.1 μm to 0.2 μm.

Thereafter, ion implantation for forming a source / drain is performed on the semiconductor substrate 11 in the DRAM region using the resist film 91 as a mask, thereby forming a first diffusion layer 13. As an example of the ion implantation conditions,
Phosphorus is used as an impurity to be ion-implanted, and a dose amount is 1 × 1.
0 ¹³ / cm ^{2 to} 5 × 10 ¹³ / cm ² , acceleration voltage 10 k
Set to eV to 40 keV. After that, the resist film 91 is removed. In this ion implantation, ion implantation is performed slightly shallower in consideration of diffusion due to heat treatment for forming a gate in the DRAM region later. However, since the gate of the DRAM is of a substrate-embedded type, the channel of the DRAM region has a buried gate. There is no problem because it is formed at the bottom of the groove to be formed. In addition, since activation is performed by a subsequent heat treatment, there is no need to perform a heat treatment at this stage.

Next, as shown in FIG. 3B, a buffer layer 72 is formed on the semiconductor substrate 11 by using, for example, a silicon oxide film to a thickness of 20 nm to 30 nm. Subsequently, after a resist film 93 is formed, the resist film 92 is removed using a lithography technique on the standard voltage logic region and the high voltage logic region while leaving the resist film 92 on the DRAM region. Thereafter, the buffer layer 72 is etched using the resist film 92 as an etching mask. That is, the buffer layer 72 on the standard voltage logic region and the high voltage logic region is removed by etching while leaving the buffer layer 72 on the DRAM region. This etching process can be performed by any of the well-known dry etching or wet etching for etching a silicon oxide film. After that, the resist film 92 is removed. In the above process, D
The buffer layer 72 left on the RAM area is
When forming a salicide on the word line in the region, the DRA
It has a function of protecting the diffusion layer in the M region from this salicide formation.

Further, as shown in FIG. 4C, after forming a resist film 93 used for the lithography technique,
An opening 94 is formed in the resist film 93 on a region to be a word line (gate electrode) in the DRAM region.

Next, as shown in FIG. 5D, the buffer layer 72, the element isolation region 12, and the semiconductor substrate 11 are etched (for example, continuously etched) using the resist film 93 as an etching mask. A DRAM is provided in the element isolation region 12 (field) and the semiconductor substrate 11.
Trench 14 in which the word line (including the gate electrode) of the region is formed
To form The depth of the groove 14 is, for example, 50 nm to 1
Groove 1 formed in the semiconductor substrate 11
4 may be slightly different from the depth of the groove 14 formed in the element isolation region 12. This groove 14 is DR
Since it is formed only in the AM region, it is desirable that the edge portion at the bottom of the groove is formed in a so-called round shape in order to avoid the electric field concentration of the cell transistor. In addition,
The buffer layer 72 formed in the DRAM region is simultaneously etched when the element isolation region 12 is etched. Thereafter, the resist film 93 is removed by a normal removal technique.

The voltages assumed in this generation are 0.5 V to 1.2 V in the standard logic region, 1.5 V to 2.5 V in the high voltage logic region, and 1.times. 5V to 2.5V.

Next, although not shown, a well channel dose in the DRAM region and the logic region is performed by an ion implantation method using, for example, a resist mask to form a channel diffusion layer, a well region, and the like on the semiconductor substrate 11.

As the channel diffusion layer of the word transistor in the DRAM region, a high concentration (for example, 1.0 × 10 ¹⁸⁾
/ Cm ^{3 to} 1.0 × 10 ¹⁹ / cm ³ ) is the semiconductor substrate portion at the bottom of the groove 14 where the semiconductor substrate 11 is dug down. There is almost no need to perform ion implantation as a concentration. Therefore, the diffusion layer 13 described later
(See FIG. 7) The lower semiconductor substrate portion has an extremely low concentration (for example, 1.0 × 10 ¹⁷ / cm ^{3 to} 1.0 × 10 ¹⁸ / c).
m ³ ).

Thereafter, as shown in FIG. 6 (5), the inner surface of the groove 14, the semiconductor substrate 11 and the element isolation region 12 are formed.
A gate insulating film 15 such as a DRAM region, a standard voltage logic region (a sense amplifier and other peripheral circuits), a high voltage logic region (eg, a word line booster) is formed thereon.
In this generation, it is general that the gate insulating film is formed separately according to the film thickness, and the gate insulating film is formed separately using a resist process. Silicon oxide or silicon nitride is used for the gate insulating film. However, in the case of a low-cost general-purpose DRAM, it is not always necessary to separately manufacture them.

Further, as shown in FIG.
4 so that the semiconductor substrate 11 and the element isolation region 1 are embedded.
A gate electrode forming film 73, for example, a polysilicon layer 74 and a metal electrode forming layer 75,
And formed. The thickness of the polysilicon layer 74 is 70 n.
m to 200 nm, preferably about 100 nm. Next, as the metal electrode formation layer 75, for example, a tungsten nitride film and a tungsten film are stacked. Since this material is for suppressing the gate delay of the peripheral circuit portion, a conventionally used tungsten silicide can also be used.

Alternatively, the gate structure may be a simple polysilicon gate, and a salicide process may be performed later to reduce the resistance of the word line of the DRAM. Can be used as a salicide to reduce the resistance. In addition, general-purpose DR
If high integration of the peripheral circuit portion is not required for AM, a conventional n ⁺ gate electrode can also be used for the p-channel transistor. In this case, it is possible to use phosphorus-doped polysilicon in advance as the gate polysilicon and to reduce the impurity doping step for the gate electrode. Further, a silicon oxide film, for example, is formed as the buffer layer 76 on the gate electrode formation film 73 (metal electrode formation layer 75).

In the above-described forming process, the first diffusion layer 13 in the DRAM region formed first by ion implantation
Thermal diffusion of phosphorus progresses, and the bottom of the first diffusion layer 13
The concentration is reduced, and the electric field with the semiconductor substrate 11 can be reduced. Originally, the semiconductor substrate 11 side is set to have a low concentration at the junction of the first diffusion layer 13, so that a junction with a low electric field strength is formed together with the first diffusion layer 13. This junction maintains the tendency of the DRAM data retention characteristics.

Next, after forming a resist film on the entire surface, the resist film is processed by lithography to form a resist pattern 95 for forming a gate electrode in a logic region.

Next, as shown in FIG. 8 (7), the buffer layer 76 and the gate electrode forming film 73 are etched using the resist pattern 95 as a mask.
Gate electrode (including gate wiring) in standard voltage logic area
At the same time, a gate electrode (not shown, including a gate wiring) 61 is formed in the high-voltage logic region.
The buffer layer 76 is deposited in order to prevent salicide from being formed in the tungsten layer on the gate electrodes 51 and 61 when salicide is formed later. Not required. Although not shown, it is unnecessary when a salicide structure is used for the gate electrode of the peripheral circuit portion.

In the trench 14 in the DRAM region, a word line (a part of which becomes a gate electrode) 16 is formed so as to leave the polysilicon layer 74 of the gate electrode forming film 73. At this time, the etch-back for forming the word line 16 in the DRAM region is, for example, 50 n
m so as to secure a withstand voltage distance with respect to a diffusion layer extraction electrode to be formed later. In this etching, only the doped polysilicon film remains in the DRAM region. After that, the resist pattern 95 is removed.

As described above, the cell transistor in the DRAM region forms a channel so as to round the semiconductor substrate 11 around the groove 14. An effective channel length can be ensured, and a back bias can be applied to stabilize the transistor characteristics of a DRAM cell having a severe short channel effect.

Next, as shown in FIG. 9 (8), a resist film (not shown) having an opening on the n-channel transistor formation region in the standard voltage logic region is formed, and then the resist film is used as a mask. Then, ions are implanted into the semiconductor substrate 11 to form low-concentration diffusion layers 52 of an n-channel transistor. After that, the resist film is removed. Similarly, a resist film (not shown) having an opening on the p-channel transistor formation region in the standard voltage logic region is formed, and subsequently, ion implantation is performed on the semiconductor substrate 11 using the resist film as a mask. A low concentration diffusion layer (not shown) of a channel transistor is formed. After that, the resist film is removed.

Further, in the same manner, a resist film (not shown) having an opening on the n-channel transistor formation region in the high-voltage logic region is formed, and then the resist film is used as a mask to form an ion on the semiconductor substrate 11. Make an injection, n
The low concentration diffusion layers 62 of the channel transistor are formed. After that, the resist film is removed. Similarly, a resist film (not shown) having an opening on the formation region of the p-channel transistor in the high-voltage logic region is formed,
Subsequently, the semiconductor substrate 11 is formed using the resist film as a mask.
To form a low concentration diffusion layer (not shown) of the p-channel transistor. After that, the resist film is removed.

Next, a protective film 78 for protecting the gate in the DRAM region is formed of, for example, a thin silicon nitride film (for example, having a thickness of 10 nm to 50 nm). Further, the sidewall forming film 79 is formed of, for example, a silicon oxide film. As described above, it is preferable that the sidewall forming film 79 is formed of silicon oxide having a lower stress than silicon nitride and having good removability by wet processing. Alternatively, it can be formed using a stacked film of a silicon oxide film and a silicon nitride film or a silicon oxynitride film. The protective film 78 serves as an etching stopper when the sidewall forming film 79 of the transistor for a peripheral circuit is removed later in the DRAM, and the word line 1 in the DRAM region is later formed.
The side wall is formed on the side wall of the groove 14 above the groove 6 and contributes to securing the withstand voltage of the side wall of the word line 16 when the salicide layer is formed.

Thereafter, as shown in FIG. 10 (9), a resist film 96 is formed on the entire surface, and the resist film 96 on the standard voltage logic region and the high voltage logic region is removed by, for example, lithography technology, and the DRAM region is removed. The resist film 96 is left so as to cover. Then, the sidewall forming film 79 is etched back, and the sidewall insulating films 54 and 6 are formed on the respective sidewalls of the gate electrode 51 in the standard voltage logic region and the gate electrode 61 in the high voltage logic region.
4 is formed. After that, the resist film 96 is removed.

Next, as shown in FIG. 11 (10),
A resist film (not shown) having an opening on the n-channel transistor formation region of the standard voltage logic region is formed, and then the semiconductor film 11 is ion-implanted using the resist film as a mask. Low concentration diffusion layer 5
2 through the second diffusion layer 5 of the n-channel transistor
5, 55 are formed. After that, the resist film is removed. Similarly, a resist film (not shown) having an opening on the p-channel transistor formation region in the standard voltage logic region is formed, and subsequently, ion implantation is performed on the semiconductor substrate 11 using the resist film as a mask. A diffusion layer (not shown) of a channel transistor is formed. After that, the resist film is removed.

Further, in the same manner, a resist film (not shown) having an opening on the formation region of the n-channel transistor in the high-voltage logic region is formed, and then the resist film is used as a mask to form an ion on the semiconductor substrate 11. Implantation is performed, and third diffusion layers 65, 65 of the n-channel transistor are formed on the gate electrode 61 side via the low concentration diffusion layer 62. After that, the resist film is removed. Similarly, a resist film (not shown) having an opening on the p-channel transistor formation region in the high-voltage logic region is formed, and then the resist film is used as a mask to ion-implant the semiconductor substrate 11 to form a gate. A diffusion layer (not shown) of a p-channel transistor is formed on the electrode side via a low concentration diffusion layer. After that, the resist film is removed.

Next, after a resist film 97 is formed on the entire surface, the resist film 97 in the DRAM region is removed by lithography, and patterning is performed so that the resist film 97 covers the logic region. Next, using the resist film 97 as a mask, the sidewall forming film 79 made of silicon oxide in the DRAM region is etched back by, for example, a wet process. In this etching, the protective film 78 made of silicon nitride (see FIG. 9) formed immediately above the word line 16 of the previously formed DRAM serves as an etching stopper.

The protective film 7 made of a silicon nitride film in the DRAM region is utilized by using the resist film 97 as it is.
8 is etched by, for example, reactive ion etching (RIE) to expose the word lines 16 in the DRAM area. At this time, a sidewall 17 is formed on the side wall of the groove 14 on the word line 16. The side wall 17 has the groove 1
In addition to the function of protecting the side wall 4, it has the function of ensuring the withstand voltage between the silicide layer formed later and the first diffusion layer 13.
In the above reactive ion etching, it is important that the first diffusion layer 13 in the DRAM region is not exposed. After that, the resist film 91 is removed.

Further, as shown in FIG. 12 (11),
By using a normal silicidation technique, a selection is made on the word line (gate electrode) 16 in the DRAM area, on the second diffusion layer 55 in the standard voltage logic area, and on the third diffusion layer 65 in the high voltage logic area. Then, silicide (for example, salicide) layers 18, 58, and 68 are formed. At this time, since the buffer layer 76 made of a silicon oxide film and the sidewalls 54 and 64 are formed on the gate electrodes 51 and 61 in each logic region, no silicide layer is formed. In this manner, silicide layers 58, 68, and 18 are selectively formed on the second diffusion layers 55 and 65 in the logic area where low resistance needs to be realized and on the word lines 16 in the DRAM area.

As the silicide layers 18, 58, 68, for example, cobalt silicide (CoSi ₂ ), titanium silicide (TiSi ₂ ), nickel silicide (NiS
i ₂ ) can be used. Note that, as described above, a silicide layer may be formed also on the gate electrode of the transistor in the peripheral circuit portion to form a salicide structure so as to reduce the resistance of the gate electrode. Thereafter, a cap insulating film 80 is formed on the entire surface by, for example, a silicon nitride film. Although the cap insulating film 80 is effective in suppressing the junction leak at the salicide formation portion, it is not necessary to form the cap insulating film if the junction leak can be suppressed without the cap insulating film 80.

Next, as shown in FIG. 13 (12),
After forming a first insulating film (insulating film) 19 on the entire surface, the CM
The surface of the first insulating film 19 is planarized by P. The method for planarizing the surface of the first insulating film 19 is not limited to CMP as long as planarization can be realized, and for example, an etch-back method can be used. Then, after forming a resist film 93 on the first insulating film 19, a connection hole pattern 100 for contacting a diffusion layer in the DRAM region is formed in the resist film 99 by lithography.

Next, as shown in FIG. 14 (13),
Using the resist film (see FIG. 13) as an etching mask, the first insulating film 19 penetrates the first region of the DRAM region.
A connection hole 20 reaching the diffusion layer 13 is formed. At this time, the word line (gate electrode) 16 in the DRAM region is more in contact with the semiconductor substrate 1 than the first diffusion layer 13 to be contacted.
Since it is arranged under one surface, it is not necessary to use a special technique such as a self-aligned contact. Also DRAM
It is desirable to form the connection hole 20 as large as possible so that the entire surface of the first diffusion layer 13 can contact the extraction electrode. Thereby, the contact resistance is reduced. In the drawings, a state in which the alignment is slightly misaligned is intentionally described. However, unless excessive overetching is performed at the time of opening the connection hole, the physical properties of the word line extraction electrode formed in the connection hole 20 in a later step will be described. It is possible to secure a long distance. In the projection design viewed from above, the connection hole 20 completely overlaps the word line (gate electrode) 16.

Next, an extraction electrode forming film 81 is formed on the first insulating film 19 so as to fill the connection holes 20. This take-out electrode forming film 81 can be
It is desirable that phosphorus-doped polysilicon be selected in the DRAM region in consideration of reduction of junction leakage. afterwards,
A heat treatment for activating the phosphorus-doped polysilicon is performed. As this heat treatment, a rapid heating treatment of about 900 ° C. (hereinafter referred to as RTA, RTA is a rapid thermal annealing)
g). After that, since it is a step of forming the gate electrode in the logic region, it is necessary to avoid performing any high-temperature heat treatment.

Thereafter, as shown in FIG. 15 (14),
Excessive extraction electrode forming film 81 (phosphorus-doped polysilicon) on first insulating film 19 is removed by, for example, CMP to form extraction electrode 21 made of extraction electrode forming film 81 in connection hole 20. The first insulating film 19 is polished to flatten its surface.

Next, as shown in (15) of FIG.
It goes through a normal DRAM process. That is, after the second insulating film 22 is formed, the bit contact holes 23 are formed.
To form Next, a bit line 24 made of a metal electrode is formed. This bit line 23 has an adhesive layer 24a
And an offset insulating film 25 thereon.
Is formed. After that, an etching stopper layer 26 and a third insulating film 27 covering the bit line 24 are formed. Then, the surface of the third insulating film 27 is flattened. Next, a connection hole 28 connected to the extraction electrode 21 is formed in the third insulating film 27 by a technique for forming a self-aligned contact. In this connection hole 28, a side wall insulating film 29 is formed for insulation from the bit line 24. Further, a plug 30 is formed in the connection hole 28.
Thereafter, a fourth insulating film 31 is formed on the third insulating film 27.
To form

Next, a recess 32 in which a capacitor is formed is formed in the fourth insulating film 31 so that the upper surface of the plug 30 is exposed at the bottom. Thereafter, a capacitor 33 having an MIM (Metal / insulator / Metal) structure that does not require heat treatment is formed in the recess 32. MIM structure capacitor 3
3 is expected to be indispensable for DRAMs of 0.1 μm or later, and at present, as an example, a ruthenium (R
u), a ruthenium oxide (RuO) -based material is used, and a BST (mixed crystal of BaTiO ₃ and SrTiO ₃ ) -based film is used as the dielectric film.

Next, a fifth insulating film 34 covering the MIM structure capacitor 33 is formed on the fourth insulating film 31. Thereafter, the fifth insulating film 3 is formed by CMP.
4 Flatten the surface. Then, on the fifth insulating film 34 to the first insulating film 19, a capacitor lead electrode, a word line lead electrode, a bit line lead electrode, a diffusion layer lead electrode of a logic region, a gate lead electrode of a logic region, and the like are formed. Connection holes 35, 36, 37, 10
1, 102, 103, 104, 105, etc. are formed. Further, the connection holes 35, 36, 37, 101, 102, 103,
104, 105, etc., a capacitor lead electrode 38, a word line lead electrode 39, a bit line lead electrode 40,
Diffusion layer extraction electrodes 105, 106, 1 in the logic region
07, 108, gate extraction electrode 10 in logic area
9 and so on. Further, a sixth insulating film 41 is formed on the fifth insulating film. Next, the sixth insulating film 41
Then, the respective wiring grooves 42 reaching the respective electrodes 38 to 40, 105 to 109 and the like are formed, and the first wiring 43 is formed in the wiring grooves 42. The first wiring 43 is made of, for example, a copper wiring. Although not shown, an upper layer wiring is further formed as necessary.
In the electrodes 38 to 40, 105 to 109, and the wiring 42, an adhesion layer and a barrier layer which are generally known are formed depending on the material of the electrode, the wiring, and the insulating film.

The method of manufacturing the semiconductor device 1 is described in the following.
2, the standard voltage logic element 3 and the high voltage logic element 4 are formed, but a manufacturing method in which only the DRAM 2 is formed may be used. In that case, the standard voltage logic element 3,
The process of forming only each component of the high-voltage logic element 4 is omitted. Typically, the buffer layer 52, the gate electrode metal film 74, the buffer layer 75, the gate electrode 51,
61, low concentration diffusion layers 52, 62, second diffusion layers 55, 6
5, sidewall formation film 77, electrode 1 in logic region
This is a process for forming layers 05 to 109 and the like.

In the method of manufacturing the semiconductor device 1, the word line (gate electrode) 16 is buried in the groove 14 formed in the semiconductor substrate 11 via the gate insulating film 15 while leaving the upper part of the groove 14. Forming a first diffusion layer 13 on the surface of the semiconductor substrate 11 on the side wall of the groove 14;
Further, a first insulating film (insulating film) 19 is formed so as to fill the upper portion of the groove 14, and the word line (gate electrode) 16 is formed on the word line (gate electrode) 16 via the first insulating film 19.
Since the connection hole 20 reaching the first diffusion layer 13 is formed so as to overlap with the gate electrode 16, the extraction electrode 20 and the gate electrode 16 formed in the connection hole 20 are separated from the side wall 17 and the first insulating film 19. For example, a sufficient film thickness of, for example, 30 nm or more can be secured. Therefore, the gate electrode (word line 16
And the extraction electrode 20 connected to the first diffusion layer 13 withstand voltage.

The word line (gate electrode) 1 is formed in the groove 14 formed in the semiconductor substrate 11 via the gate insulating film 15.
6 is buried and the first diffusion layer 13 is formed on the surface side of the semiconductor substrate 11, so that the channel is formed on the semiconductor substrate 1 on the bottom side of the groove 14 where the word line (gate electrode) 16 is formed.
1 is formed. Therefore, since an effective channel length is sufficiently ensured, the transistor characteristics of the DRAM having a severe short channel effect are stabilized by applying a back bias. Further, the extraction electrode 21 can be connected to the entire surface of the first diffusion layer 13 on the surface side of the semiconductor substrate 11, so that the contact resistance can be reduced.

Further, since the first diffusion layer 13 is formed so that the impurity concentration decreases in the depth direction, the electric field at the junction can be reduced, and the performance of the data retention characteristics is maintained.

Further, since the silicide layer 18 is formed above the word line 16 of the DRAM, the resistance of the word line 16 can be reduced, and the problem of the delay of the word line 16 which is a problem in miniaturization can be avoided. In addition, a silicide layer 58 is formed above the second diffusion layer 55 and the third diffusion layer 65 in the logic region.
By forming 68, the contact resistance to the second diffusion layer 55 and the third diffusion layer 65 is reduced.

The technology used in the DRAM area is a general-purpose D
The present invention can be applied to the manufacture of a memory chip of a RAM.

[0086]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, the memory element (DRA)
M) The substrate concentration under the diffusion layer in the region does not need to be as high as required for the cell transistor, so that the electric field at the junction can be reduced, and the data retention that becomes more severe by reducing the cell size in the memory element region It is possible to maintain the performance of the characteristic.

Further, since the effective channel length of the cell transistor in the memory element region is extended, the short channel effect can be suppressed, and the transistor characteristics can be stabilized.

Further, since the entire surface of the diffusion layer in the memory element region is used for contact with the extraction electrode, the effective area can be used effectively. Therefore, the contact resistance of the diffusion layer can be reduced to the minimum that can be realized by the cell design. Can be suppressed.

Further, the extraction electrode of the diffusion layer in the memory element region and the word line (gate electrode) can overlap with each other in the upper projection design, and the cell can be miniaturized. In the current DRAM structure, it is necessary to secure a distance of about 20 nm to 30 nm between the word line and the extraction electrode.
In the M) structure, it is not necessary to secure this distance. Also,
It becomes easy to ensure the withstand voltage between the word line and the contact for taking out the diffusion layer, which has been a bottleneck in forming the memory cell of the DRAM.

Further, by forming a silicide layer above the word line of the memory element, the resistance of the word line can be reduced, and the problem of the word line delay, which is a problem in fine processing, can be avoided. .

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing an example of an embodiment of a semiconductor device of the present invention.

FIG. 2 is a schematic sectional view (1) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a schematic sectional view (2) showing an example of an embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a schematic cross-sectional view (3) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a schematic sectional view (4) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a schematic sectional view (5) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.

FIG. 7 is a schematic sectional view (6) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.

FIG. 8 is a schematic sectional view (7) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.

FIG. 9 is a schematic sectional view (8) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 10 is a schematic sectional view (9) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 11 is a schematic configuration sectional view (10) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 12 is a schematic sectional view (11) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 13 is a schematic sectional view (12) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 14 is a schematic sectional view (13) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 15 is a schematic sectional view (14) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 16 is a schematic sectional view (15) showing an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 11 ... Semiconductor substrate, 12 ... Element isolation region, 13 ... First diffusion layer, 14 ... Groove, 15 ... Gate insulating film, 16 ... Word line, 18 ... Silicide layer, 19 ... First
Insulating film, 21 ... take-out electrode

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 21/8234 H01L 27/10 671Z 27/088 681F F term (Reference) 4M104 BB01 BB20 BB21 BB25 BB40 CC05 DD06 EE09 FF14 FF18 GG16 HH15 HH16 5F033 JJ04 KK01 KK25 KK27 LL04 MM05 MM08 QQ09 QQ25 QQ31 QQ48 TT08 VV06 VV16 XX09 XX10 XX31 5F048 AB01 AC01 BA00 BB06 BB09 BC06 BD02 BF06 BF16 BG01 BG13 AD04 GA35 AD43 GA25 MA19 MA20 NA01 PR03 PR06 PR10 PR34 PR36 PR39 PR40 PR43 PR44 PR53 PR54 ZA05 ZA06 ZA07 ZA12

Claims (12)

[Claims] 1. A word line buried via a gate insulating film in a trench formed in a semiconductor substrate and an element isolation region formed in the semiconductor substrate, and formed on a side surface of the semiconductor substrate on a sidewall of the trench. A semiconductor device having a diffusion layer formed on the word line, and a lead connected to the diffusion layer in a state where the silicide layer overlaps the word line via an insulating film on the word line. A semiconductor device comprising: an electrode; 2. The semiconductor device according to claim 1, wherein the impurity concentration of the diffusion layer decreases in a depth direction. 3. The semiconductor device according to claim 1, wherein said word line includes a gate electrode. 4. A semiconductor device in which a memory element and a logic element are formed on the same semiconductor substrate, wherein the transistor of the memory element is formed in a groove formed in a semiconductor substrate and an element isolation region formed in the semiconductor substrate. A word line buried via a gate insulating film, and a diffusion layer formed on the side of the trench on the surface of the semiconductor substrate, wherein the silicide layer is formed on the word line, An extraction electrode connected to the diffusion layer so as to overlap the word line via an insulating film on a line, wherein the transistor of the logic element includes a silicide formed on the diffusion layer of the transistor of the logic element. A semiconductor device comprising a layer. 5. The semiconductor device according to claim 4, wherein the impurity concentration of the diffusion layer decreases in a depth direction. 6. The semiconductor device according to claim 4, wherein said word line includes a gate electrode. 7. After forming an element isolation region in the semiconductor substrate, forming a diffusion layer on the semiconductor substrate surface side, forming a groove in a predetermined position of the semiconductor substrate and the element isolation region, Forming a gate insulating film in the groove; forming a word line so as to fill the groove while leaving an upper portion of the groove; forming a sidewall insulating film on a side wall of the groove on the word line Forming a silicide layer on the word line, forming an insulating film so as to fill an upper portion of the groove, and overlapping the word line on the word line via the insulating film. A method for manufacturing a semiconductor device, comprising: a step of forming a connection hole reaching the diffusion layer in a state; and a step of forming an extraction electrode in the connection hole. 8. The method of manufacturing a semiconductor device according to claim 7, wherein said diffusion layer is formed so that an impurity concentration is reduced in a depth direction. 9. The method according to claim 7, wherein the word line includes a gate electrode. 10. A method of manufacturing a semiconductor device in which a memory element and a logic element are formed on the same semiconductor substrate, comprising: forming an element isolation region in the semiconductor substrate; Forming a diffusion layer; forming a groove at a predetermined position in the semiconductor substrate in the memory element region and the element isolation region; forming a gate insulating film in the groove and on the surface of the semiconductor substrate; Forming a word line so as to fill the trench while leaving the upper portion of the trench; forming a gate electrode on the semiconductor substrate in the logic element region via the gate insulating film; Forming a second diffusion layer in the semiconductor substrate on both sides of the electrode; forming a sidewall insulating film on the side wall of the groove on the word line; Forming a silicide layer on an upper layer of the gate line and the second diffusion layer; forming an insulating film filling the upper portion of the trench; and overlapping the word line on the word line via the insulating film. A method of forming a connection hole reaching the first diffusion layer in a state where the first diffusion layer is formed, and a step of forming an extraction electrode in the connection hole. 11. The method for manufacturing a semiconductor device according to claim 10, wherein said diffusion layer is formed so that an impurity concentration is reduced in a depth direction. 12. The method according to claim 10, wherein said word line includes a gate electrode.