JP4759821B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which a DRAM (Dynamic Random Access Memory) and a logic element are mixedly mounted and a manufacturing method thereof.
[0002]
[Prior art]
Due to the miniaturization competition accelerated year by year, a composite device in which a large-capacity DRAM and a high-speed logic element are mounted on one chip is being developed. As an example of the configuration, memory cell gates of DRAM are stacked on a substrate, and so-called self-aligned contacts are used for taking out the diffusion layers of the memory cell transistors, while logic elements are formed without using self-aligned contacts. It is a thing of the structure to do.
[0003]
[Problems to be solved by the invention]
However, various problems have also become apparent in stacked DRAMs.
[0004]
In order to maintain the transistor performance, the substrate concentration is increasing with the reduction of DRAM memory cells, and the junction leakage in the DRAM region is approaching a severe state. For this reason, it has become difficult to suppress junction leakage in a megabit class DRAM. That is, it has become difficult to maintain the data retention characteristics of a DRAM that could be controlled with a margin. If this is the case, the only effective means is to increase the capacitor capacity for each generation.
[0005]
In addition, with the reduction in the size of DRAM cells, the contact area between the diffusion layer and the extraction electrode is reduced, and the contact resistance is increased at twice the rate of generation. In the generation after 0.1 μm, this contact resistance is expected to be several kiloΩ, and is expected to be comparable to the on-resistance of the word transistor of the memory cell. Therefore, not only the cell transistor but also the variation in contact resistance severely affects the DRAM operation, and higher precision is required in manufacturing.
[0006]
Further, with the reduction in the size of DRAM cells, the interlayer insulation distance between the word line and the extraction contact of the diffusion layer formed on the side of the word line is getting closer to each generation. It is said that the limit distance is 20 nm to 30 nm in order to secure this withstand voltage when manufacturing a megabit class DRAM. For this reason, in the generation of DRAMs of 0.1 μm or later, it is necessary to form the extraction contact of the diffusion layer at a distance equal to or smaller than the withstand voltage limit distance.
[0007]
Conventionally, tungsten silicide (WSi) ₂ ) / The word line of DRAM that has suppressed the delay by adopting the polycide structure of doped polysilicon has become stricter in aspect ratio with the recent miniaturization, and has a sufficiently low resistance to suppress the delay of the word line. It has become difficult to obtain. In particular, in stacked DRAMs that require high-speed operation, this word line delay becomes a serious problem that affects the access time of the DRAM. As a technique for reducing the resistance of the gate, reducing the resistance of the wiring by salicide has been put into practical use. However, in order to apply to the gate of a DRAM memory cell, no salicide is formed in the diffusion layer of the DRAM in order to prevent the reduction of the DRAM memory cell due to the inability to use the offset silicon oxide film and maintain the data retention characteristics. It is usually not possible due to difficulties such as requiring a process.
[0008]
On the other hand, the transistor performance of the logic part has been remarkably improved, and in the generation of logic transistors of 0.1 μm and later, it is required to form an extremely thin film having a gate length of 50 nm to 70 nm and a gate insulating film of 1.5 nm or less. It is expected that From this thickness onwards, silicon oxide (SiO2), a high-quality insulating film conventionally used, is used. ₂ ) Is the limit, zirconium oxide, hafnium oxide, tantalum oxide, aluminum oxide, BST (BaTiO) _Three And SrTiO _Three Application of a new insulating film such as a mixed crystal) is expected to be indispensable.
[0009]
The gate insulating film made of an insulating material such as zirconium oxide, hafnium oxide, tantalum oxide, aluminum oxide, or BST avoids the heat treatment necessary for activating the diffusion layer and avoids plasma damage when forming the gate electrode. Therefore, a replacement gate electrode that replaces a dummy gate after forming a diffusion layer has been proposed. Even with this replacement gate electrode structure, it is expected that the above material having a relatively low heat resistance will be required to suppress depletion, which is a problem with the conventional polysilicon gate electrode.
[0010]
The replacement gate manufacturing process involves a step of exposing the dummy gate by chemical mechanical polishing (hereinafter referred to as CMP, CMP is chemical mechanical polishing). It does not have good consistency with the type DRAM cell, and it does not have good consistency with respect to the heat treatment required for activating the DRAM contact.
[0011]
Even in this generation, analog circuits, external high voltage interfaces (Vpp; 1.5V to 2.5V), word line boosting circuits necessary for DRAM operation, etc. are high in voltage due to the above new materials. Conventional silicon oxide-based logic circuits other than the dielectric gate insulating film must also be mounted on the same chip.
[0012]
In this way, even if the technology is acceptable in the current 0.18 μm generation, some countermeasures will be required in the future 0.1 μm generation and beyond, and in order to maintain the chip performance trend, it is accumulated. A drastic improvement in the type DRAM structure is expected.
[0013]
[Means for Solving the Problems]
The present invention provides a semiconductor device made to solve the above problems. Set It is a manufacturing method.
[0021]
According to another aspect of the present invention, there is provided a semiconductor device manufacturing method in which a memory element and a logic element are formed on the same semiconductor substrate. After forming an element isolation region in the semiconductor substrate, the memory element is formed on the semiconductor substrate surface side. Forming a diffusion layer in the region, forming a groove in a predetermined position of the memory element region and the first logic element region in the semiconductor substrate and the element isolation region, and forming a gate insulating film in the groove And forming a word line that fills the groove while leaving the upper portion of the groove in the memory element region, and forming a dummy gate on the semiconductor substrate in the second logic element region in the same layer as the word line And forming a gate electrode in the groove of the first logic element region, and forming a logic transistor on the semiconductor substrate in the first and second logic element regions. A step of forming a diffusion layer of the transistor, a step of forming a sidewall insulating film on the side wall of the groove on the word line, and a silicide layer on the upper layer of the word line and the upper diffusion layer of the first and second logic element regions Forming an insulating film so as to fill the upper portion of the groove and cover the dummy gate; From above the diffusion layer On the word line Over The diffusion layer in a state of overlapping with the word line through the insulating film The whole surface of Forming a connection hole reaching the end, and in the connection hole The entire surface of the diffusion layer is contacted with the word line overlapping with the insulating film. A step of forming the extraction electrode, a step of planarizing the surface of the insulating film and exposing the upper portion of the dummy gate, a step of performing a heat treatment for activating the extraction electrode, a gate groove by removing the dummy gate And a step of forming a gate electrode in the gate groove through a gate insulating film. The diffusion layer is formed so that the impurity concentration is reduced in the depth direction.
[0022]
In the manufacturing method of the semiconductor device, since the silicide layer is formed on the word line, the resistance of the word line is reduced and the problem of delay is avoided. Further, since the silicide layer is formed on the diffusion layer of the logic element, the contact resistance to the diffusion layer is reduced.
[0023]
In addition, since the diffusion layer of the memory element region is formed on the semiconductor substrate surface side and the word line is embedded in the semiconductor substrate via the gate insulating film, the word line (gate electrode) is formed in the channel. It is formed so as to go around the semiconductor substrate on the bottom side of the groove. Therefore, since an effective channel length is sufficiently ensured, a back bias is applied to stabilize the transistor characteristics of a memory element (eg, DRAM) having a severe short channel effect.
[0024]
In addition, it is connected to a diffusion layer formed on the surface of the semiconductor substrate on the word line buried in the groove formed in the semiconductor substrate via the gate insulating film, and overlapping with the word line via the insulating film. Therefore, the insulating film on the word line has a sufficient film thickness of 20 nm to 30 nm or more. Thereby, a withstand voltage with respect to the extraction electrode connected to the diffusion layer is ensured. Therefore, the entire surface on the diffusion layer of the memory element can be used for the contact, so that the effective area can be used effectively. Therefore, the lowest resistance value that can be realized by the cell design can be realized, and the contact resistance can be reduced.
[0025]
Further, since the diffusion layer in the memory element region is formed so that the impurity concentration decreases in the depth direction, the concentration of the semiconductor substrate below the diffusion layer in the memory element region is so high as required by the cell transistor. Therefore, the electric field at the junction is relaxed, and the performance of the data retention characteristic that becomes severe as the memory cell size is reduced is maintained.
[0026]
In addition, a logic transistor having a gate electrode formed by replacement for realizing a high driving force transistor in the logic region and a memory element can be realized in one chip. As a result, the gate in the logic region does not require care for heat treatment, a high dielectric constant material can be used for the gate insulating film, and the gate electrode can be formed of a polymetal structure or a metal material.
[0027]
In addition, the above manufacturing method makes it possible to mount a high voltage logic element that enables high voltage operation necessary for boosting the word line of an analog circuit, an external interface, and a memory element together with a standard voltage logic element on a single semiconductor substrate. Become.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment according to a semiconductor device of the present invention will be described with reference to a schematic sectional view of FIG.
[0029]
As shown in FIG. 1, the semiconductor substrate 11 has an element isolation region 12 for isolating a memory element region (hereinafter referred to as a DRAM region and referred to as a DRAM region in the drawing), a standard voltage logic region, a high voltage logic region, and the like. Is formed. The element isolation region 12 is formed to a depth of, for example, about 0.1 μm to 0.2 μm by, for example, STI (Shallow Trench Isolation) technology. In the DRAM region on the semiconductor substrate 11, a buffer layer 72 is formed with a thickness of 20 nm to 30 nm, for example, using a silicon oxide film.
[0030]
A first diffusion layer (diffusion layer) 13 serving as a source / drain of a DRAM memory cell transistor is formed on the semiconductor substrate 11. As an example, the diffusion layer 13 uses phosphorus as an impurity and has a dose amount of 1 × 10 6. ¹³ / Cm ² ~ 5x10 ¹³ / Cm ² , And formed by ion implantation with an acceleration voltage set to 10 keV to 40 keV.
[0031]
In the buffer layer 72, the semiconductor substrate 11, and the element isolation region 12, a groove 14 is formed to a depth of, for example, about 50 nm to 100 nm. A word line (including a gate electrode) 16 is formed in the trench 14 via a gate insulating film 15. The word line 16 is formed of a polysilicon layer as a lower layer and a silicide (for example, salicide) layer 18 as an upper layer. At least the distance with which the withstand voltage to be described later is ensured is formed such that the surface thereof is lowered by at least 30 nm to 50 nm, preferably 40 nm to 50 nm, from the surface of the semiconductor substrate 11 above the groove 14. Yes. In this embodiment, for example, it is formed in a state of being lowered by about 50 nm. Note that there may be a slight difference between the depth of the groove 14 formed in the semiconductor substrate 11 and the depth of the groove 14 formed in the element isolation region 12.
[0032]
Further, a sidewall insulating film 17 is formed of, for example, a silicon nitride film on the side wall of the groove 14 on the word line 16 (polysilicon layer). Further, the silicide layer 18 is formed on the polysilicon layer 16p. As the silicide layer 18, for example, cobalt silicide (CoSi) ₂ ), Titanium silicide (TiSi) ₂ Nickel silicide (NiSi) ₂ ) Etc. can be used. Note that there may be a slight difference between the depth of the groove 14 formed in the semiconductor substrate 11 and the depth of the groove 14 formed in the element isolation region 12.
[0033]
Further, a channel diffusion layer (not shown) is formed in the semiconductor substrate 11 at the bottom of the groove 14. The channel diffusion layer has a high concentration (for example, 1.0 × 10 ¹⁸ / Cm ^Three ~ 1.0 × 10 ¹⁹ / Cm ^Three However, it is formed in the semiconductor substrate 11 portion at the bottom of the groove 14 where the semiconductor substrate 11 is dug down, and the side wall and the upper portion of the groove 14 may be almost the substrate concentration, and the region has an extremely low concentration ( For example, 1.0 × 10 ¹⁶ / Cm ^Three ~ 1.0 × 10 ¹⁸ / Cm ^Three ).
[0034]
The gate insulating film 15 has a slightly thicker film thickness than a state-of-the-art logic transistor and has a slightly longer gate length. Therefore, even in this generation, application of a silicon oxide film by thermal oxidation is possible. Is possible. Therefore, the gate insulating film 15 in the DRAM region is formed of a silicon oxide film having a thickness of about 1.5 nm to 5 nm, for example.
[0035]
Therefore, a diffusion layer 13 in the DRAM region is formed on the surface side of the semiconductor substrate 11 above the side wall of the groove 14. It is desirable that the bottom of the diffusion layer 13 is set as thin as possible so as to relax the electric field with the semiconductor substrate 11. Since the semiconductor substrate 11 side is originally set to a low concentration at the junction of the diffusion layer 13, a junction having a low electric field strength is formed together with the diffusion layer 13. This junction maintains DRAM data retention characteristics.
[0036]
As described above, since the word line (gate electrode) 16 is embedded in the semiconductor substrate 11 via the gate insulating film 15 and the first diffusion layer 13 is formed on the surface side of the semiconductor substrate 11, the channel is It is formed so as to go around the semiconductor substrate 11 on the bottom side of the groove 14 where the word line (gate electrode) 16 is formed. Therefore, an effective channel length can be ensured, and a transistor characteristic of a DRAM cell having a severe short channel effect can be stabilized by applying a back bias.
[0037]
On the other hand, on the semiconductor substrate 11 in the standard voltage logic region, a gate electrode 51 formed by replacing a dummy gate having a sidewall 54 on the side wall is formed via a gate insulating film 82. Therefore, the side wall 54 is formed on the side wall of the gate electrode 51 via the gate insulating film 82. Low-concentration diffusion layers 52 and 52 are formed in the semiconductor substrate 11 below the sidewall 54, and diffusion layers 55 and 55 are formed on the semiconductor substrate 11 on both sides of the gate electrode 51 through the low-concentration diffusion layers 52 and 52. Is formed. Further, the silicide layer 58 is formed above the diffusion layers 55 and 55. As the silicide layer 58, for example, cobalt silicide (CoSi) ₂ ), Titanium silicide (TiSi) ₂ Nickel silicide (NiSi) ₂ ) Etc. can be used.
[0038]
A gate electrode (gate wiring) 51 having the same structure as the gate electrode 51 is formed on the element isolation region 12 in the logic region.
[0039]
Further, a trench 14 is formed in the semiconductor substrate 11 in the high voltage logic region as in the DRAM region, and a gate electrode 61 is formed in the trench 14 via a gate insulating film 15. The gate electrode 61 is made of, for example, the same layer as the word line 16 and has a surface at least 30 nm or more and 50 nm from the surface of the semiconductor substrate 11 above the trench 14 as a distance that ensures at least a withstand voltage with respect to an extraction electrode 126 described later. Hereinafter, it is preferably formed in a lowered state by 40 nm or more and 50 nm or less. In this embodiment, for example, it is formed in a state of being lowered by about 50 nm.
[0040]
A diffusion layer 65 is formed on the surface of the semiconductor substrate 11 on both sides of the gate electrode 61, and a low concentration diffusion layer 62 is formed below the diffusion layer 65. The silicide layer 58 is formed on the diffusion layer 65. As the silicide layer 58, for example, cobalt silicide (CoSi) ₂ ), Titanium silicide (TiSi) ₂ Nickel silicide (NiSi) ₂ ) Etc. can be used. A sidewall 64 made of silicon oxide is formed on the side wall of the groove 14 on the gate electrode 61. Further, for example, cobalt silicide (CoSi) is formed on the gate electrode 61. ₂ ) Is formed. The sidewall 64 has a function of ensuring a breakdown voltage between the silicide layer 69 and the diffusion layer 65.
[0041]
The entire surface of the semiconductor substrate 11 covers the transistor 2 in the DRAM region and the transistor 6 in the high voltage logic region, and the first insulating film (the top of the gate electrode 51 in the standard voltage logic region is exposed). Insulating film) 19 is formed. The surface of the first insulating film 19 is flattened. A connection hole 20 reaching the diffusion layer 13 in the DRAM region is formed in the first insulating film 19. In the connection hole 20, an extraction electrode 21 made of, for example, phosphorus-doped polysilicon is formed.
[0042]
The connection hole 20 is desirably formed as large as possible in the opening diameter of the connection hole 20 so that the extraction electrode can be brought into contact with the entire surface of the diffusion layer 13. Thereby, the contact resistance is reduced. In the drawing, the state where a slight misalignment is intentionally described is described. However, if excessive over-etching is not performed when the connection hole 20 is opened, the extraction electrode connected to the word line 16 formed in the connection hole 20 is used. It is possible to secure 21 physical distances. In the projection design seen from above, the connection hole 20 completely overlaps the word line (gate electrode) 16.
[0043]
Further, a second insulating film (cap insulating film) 22 is formed on the first insulating film 19 so as to cover the extraction electrode 21 in the DRAM region and the gate electrode 51 in the logic region.
[0044]
A bit contact hole 23 connected to the predetermined extraction electrode 21 is formed in the second insulating film 22. On the second insulating film 22, a bit line 24 connected to the extraction electrode 21 through the bit contact hole 23 is formed of, for example, a metal electrode. The bit line 24 has an adhesion layer formed in a lower portion thereof, and an offset insulating film 25 formed in an upper portion thereof.
[0045]
An etching stopper layer 26 and a third insulating film 27 are formed on the second insulating film 22 so as to cover the bit line 24. The surface of the third insulating film 27 is flattened. In the third insulating film 27, a connection hole 28 connected to the extraction electrode 21 is formed by a technique for forming a self-aligned contact. A sidewall insulating film 29 is formed in the connection hole 28 in order to insulate from the bit line 24.
[0046]
On the third insulating film 27, a capacitor 31 having an MIM (Metal / insulator / Metal) structure that does not require heat treatment is formed. The lower electrode 32 of the capacitor is connected to the extraction electrode 21 through the connection hole 28. The capacitor 31 having the MIM structure is expected to be indispensable for a DRAM of 0.1 μm or more. At present, as an example, the upper and lower electrodes 34 and 32 are made of ruthenium (Ru) or ruthenium oxide (RuO) based materials. The dielectric film 33 of BST (BaTiO _Three And SrTiO _Three A mixed crystal) film is used.
[0047]
A fourth insulating film 35 is formed on the third insulating film 27 to cover the MIM structure capacitor 31. The surface of the fourth insulating film 35 is flattened. The fourth insulating film 35 to the first insulating film 19 include a capacitor extraction electrode, a word line extraction electrode, a bit line extraction electrode, a diffusion layer extraction electrode in a standard voltage logic region, a gate extraction electrode in a logic region, and a high voltage. Connection holes 111, 112, 113, 114 a, 114 b, 115, 116 a, and 116 b are formed for forming a diffusion layer extraction electrode and the like in the logic region.
[0048]
Further, the connection holes 111 to 116b include a capacitor extraction electrode 121, a word line extraction electrode 122, a bit line extraction electrode 123, a diffusion layer extraction electrode 124 in the standard voltage logic region, a gate extraction electrode 125 in the logic region, and a high voltage logic. A diffusion layer extraction electrode 126 and the like in the region are formed. Further, a fifth insulating film 36 is formed on the fourth insulating film 35. In the fifth insulating film 36, each wiring groove 131 reaching each extraction electrode 121 to 126 is formed, and in the wiring groove 131, the first wiring 141 is formed by, for example, copper wiring. Although not shown, the first wiring 41 is formed with a barrier layer and an adhesion layer that prevent copper diffusion as required. Further, upper layer wiring is formed as necessary.
[0049]
The capacitor 31 is not limited to the MIM structure. For example, an HSG storage node electrode or a cylinder-shaped storage node electrode using polysilicon crystal grains can be applied. For example, a laminated film (ONO film) of a silicon oxide film, a silicon nitride film, and a silicon oxide film, a tantalum oxide film, an aluminum oxide film, or the like that has been conventionally used can be used.
[0050]
In the semiconductor device 1, the diffusion layer is overlapped on the gate electrode 15 via the first insulating film (insulating film) 18 on the gate electrode 16 embedded in the semiconductor substrate 11 via the gate insulating film 15. 17 is provided, the first insulating film 18 on the gate electrode 16 can have a sufficient film thickness of 20 nm to 30 nm or more, whereby the gate electrode The breakdown voltage between the (word line) 16 and the extraction electrode 20 connected to the diffusion layer 17 is ensured.
[0051]
Further, since the gate electrode 16 is embedded in the semiconductor substrate 11 via the gate insulating film 15 and the diffusion layer 17 is formed on the surface side of the semiconductor substrate 11, the channel is the bottom of the groove 13 in which the gate electrode 16 is formed. It is formed so as to go around the semiconductor substrate 11 on the side. Therefore, since an effective channel length is sufficiently secured, a back bias is applied to stabilize the transistor characteristics of a DRAM having a severe short channel effect. Further, the take-out electrode 20 can be connected to the entire surface of the diffusion layer 17 on the surface of the semiconductor substrate 11, and the contact resistance can be reduced.
[0052]
Further, since the word line 16 (16w) is formed so as to be connected to the gate electrode in the groove 13 formed in the semiconductor substrate 11 and the element isolation region 12, it can be simultaneously formed with the gate electrode 16. . Further, since the impurity concentration of the diffusion layer 17 is reduced in the depth direction, the electric field at the junction can be relaxed, and the performance of data retention characteristics is maintained.
[0053]
An example of an embodiment according to a method for manufacturing a semiconductor device of the present invention will be described with reference to schematic configuration cross-sectional views of FIGS. 2 to 22, the same components as those described with reference to FIG.
[0054]
As shown in FIG. 2 (1), for example, by STI (Shallow Trench Isolation) technology, a semiconductor device 11 is provided with a memory element region (hereinafter referred to as a DRAM region, referred to as a DRAM region in the drawing), a standard voltage logic region, An element isolation region 12 for isolating a high voltage logic region and the like is formed.
[0055]
Further, after forming a resist film 91 on the semiconductor substrate 11, the resist film 91 in the DRAM region is removed by using the lithography technique, and the resist film 91 is left on the logic region. Although the drawing shows the semiconductor substrate 11 on which the buffer layer 71 made of silicon oxide is formed, the buffer layer 71 is not necessary in some cases. The element isolation region 12 is formed to a depth of about 0.1 μm to 0.2 μm.
[0056]
Thereafter, using the resist film 91 as a mask, ion implantation is performed to form a source / drain in the semiconductor substrate 11 in the DRAM region, thereby forming the diffusion layer 13. As an example of the ion implantation conditions, phosphorus is used as an impurity for ion implantation, and the dose is 1 × 10. ¹³ / Cm ² ~ 5x10 ¹³ / Cm ² The acceleration voltage is set to 10 keV to 40 keV. Thereafter, the resist film 91 is removed. In this ion implantation, ion implantation is performed slightly shallower in consideration of diffusion due to heat treatment related to later gate formation in the DRAM region. However, since the DRAM gate is a substrate-embedded type, the channel in the DRAM region has a buried gate. Since it is formed at the bottom of the groove to be formed, there is no problem. Further, since it is activated by a subsequent heat treatment, it is not necessary to perform the heat treatment at this stage.
[0057]
Next, as shown in FIG. 3B, a buffer layer 72 is formed on the semiconductor substrate 11 with a thickness of 20 nm to 30 nm, for example, using a silicon oxide film. Subsequently, after forming a resist film 92, the resist film 92 is left on the DRAM region by using a lithography technique, and portions of the resist film 92 that become the standard voltage logic region and the high voltage logic region are removed.
[0058]
Thereafter, the buffer layer 72 is etched using the resist film 92 as an etching mask. That is, the buffer layer 72 is left on the DRAM region, and the buffer layer 72 on the standard voltage logic region and the high voltage logic region is removed by etching. This etching process can be performed by any known dry etching method or wet etching method for etching the silicon oxide film. Thereafter, the resist film 92 is removed.
[0059]
In the above process, the buffer layer 72 left on the DRAM region has a function of protecting the diffusion layer in the DRAM region from the formation of the salicide when the salicide is later formed on the word line in the DRAM region.
[0060]
Further, as shown in FIG. 4 (3), after a resist film 93 is formed on the semiconductor substrate 11, the gate electrode in the high voltage logic region and on the region to be a word line (gate electrode) in the DRAM region by lithography technology. An opening 94 is formed in the resist film 93 on the region to be.
[0061]
Next, as shown in FIG. 5 (4), using the resist film 93 as an etching mask, the buffer layer 72, the element isolation region 12 and the semiconductor substrate 11 are etched (for example, continuously etched) to form an element isolation region. 12 (field) and the semiconductor substrate 11 are formed with a trench 14 in which a word line (including a gate electrode) in the DRAM region and a gate electrode in the high voltage logic region are formed. The depth of the groove 14 is, for example, about 50 nm to 100 nm, and there may be a slight difference between the depth of the groove 14 formed in the semiconductor substrate 11 and the depth of the groove 14 formed in the element isolation region 12. . The buffer layer 72 formed in the DRAM region is etched at the same time as the element isolation region 12 is etched. Thereafter, the resist film 93 is removed by a normal removal technique.
[0062]
Since the word line and the gate electrode are embedded later in the groove 14 formed in the above process, a wide wiring such as a MOS capacitor for DRAM boost potential cannot be formed. When a MOS capacitor having a large effective area is required for boosting the DRAM, a comb-type MOS capacitor is installed. As for voltages assumed in this generation, the standard logic region is 0.5 V to 1.2 V, the high voltage logic region is 1.5 V to 2.5 V, and the DRAM cell word line boost is 1.5 V to 2 V. .5V.
[0063]
Next, although not shown, well channel doses in the DRAM region and the logic region are performed by ion implantation using a resist mask, for example, to form a channel diffusion layer, a well region, and the like in the semiconductor substrate 11.
[0064]
As the channel diffusion layer of the word transistor in the DRAM region, a high concentration (for example, 1.0 level 10 ¹⁸ / Cm ^Three ~ 1.0 La 10 ¹⁹ / Cm ^Three ) Is a semiconductor substrate portion at the bottom of the groove 14 where the semiconductor substrate 11 is dug down, and it is almost unnecessary to perform ion implantation as a substrate concentration on the side wall or the upper portion of the groove 14. Therefore, the semiconductor substrate portion below the diffusion layer 13 (see FIG. 7) described later has an extremely low concentration (for example, 1.0 × 10 10 ¹⁷ / Cm ^Three ~ 1.0 La 10 ¹⁸ / Cm ^Three ) Can be formed.
[0065]
Thereafter, as shown in FIG. 6 (5), a gate insulating film 15 such as a DRAM region, a high-voltage logic region (for example, a word line booster) is formed on the inner surface of the groove 14, the semiconductor substrate 11, and the element isolation region 12. Form. In this generation, the gate insulating film is generally made according to the film thickness, and is made separately using a resist process. For the gate insulating film, silicon oxide or silicon nitride is used when heat resistance is required. However, in the case of a low-cost general-purpose DRAM, it is not necessarily a necessary measure.
[0066]
DRAM cells have a slightly thicker gate insulating film than a state-of-the-art logic transistor and have a slightly longer gate length, so even in this generation, it is possible to apply a silicon oxide film by thermal oxidation. It is. Therefore, the gate insulating film 15 in the DRAM region is formed of a silicon oxide film having a thickness of about 1.5 nm to 2 nm, for example. Moreover, it is necessary to use this silicon oxide film for the gate insulating film of the high voltage logic portion.
[0067]
Further, a gate electrode formation film 73 is formed of, for example, polysilicon on the semiconductor substrate 11 and the element isolation region 12 via the gate insulating film 15 so as to fill the trench 14. The gate insulating film 15 and the gate electrode formation film 73 can be used as a dummy gate in the logic region. Therefore, the total thickness of the gate electrode formation film 73 is required to be about 150 nm to 200 nm. Next, a buffer layer 74 is formed of, for example, a silicon oxide film on the gate electrode formation film 73.
[0068]
Next, after a resist film 95 is formed on the entire surface of the buffer layer 74, only the logic region is covered with the resist film 95 in order to form word lines (including gate electrodes) in the DRAM region by lithography. Patterning is performed.
[0069]
Next, as shown in FIG. 7 (6), the buffer layer 74 and the gate electrode formation film 73 in the DRAM region are etched back using the resist film 95 as a mask. Then, the word line (part of which becomes a gate electrode) 16 is formed so as to leave the gate electrode formation film 73 only in the trench 14 in the DRAM region. At this time, the etch back for forming the word line 16 in the DRAM region is performed so as to be, for example, about 50 nm lower than that of the semiconductor substrate 11 to secure a withstand voltage distance from a diffusion layer extraction electrode to be formed later.
[0070]
In the etch back, since the logic region is covered with the resist film 95, the buffer layer 74 and the gate electrode formation film 73 are left. The buffer layer 74 is patterned when the gate electrode formation film 73 is etched back using the resist film 95 as a mask. This is because the salicide is formed in the diffusion layer in the logic region later. In order to suppress the formation of salicide on the dummy gate, it may not be formed as unnecessary if there is no problem such as contamination. Thereafter, the resist film 95 is removed.
[0071]
In the formation process so far, phosphorus in the diffusion layer 13 in the DRAM region initially formed by ion implantation is thermally diffused, and the bottom of the diffusion layer 13 has a reduced concentration, thereby relaxing the electric field with the semiconductor substrate 11. Is possible. Originally, since the semiconductor substrate 11 side is set to a low concentration at the junction of the diffusion layer 13, a junction having a low electric field strength is formed together with the diffusion layer 13. This junction maintains the trend of DRAM data retention characteristics.
[0072]
As described above, since the word line (gate electrode) 16 is embedded in the semiconductor substrate 11 via the gate insulating film 15 and the diffusion layer 13 is formed on the surface side of the semiconductor substrate 11, the channel is connected to the word line ( The gate electrode 16 is formed so as to go around the semiconductor substrate 11 on the bottom side of the groove 14 where the gate electrode 16 is formed. Therefore, an effective channel length can be ensured, and a transistor characteristic of a DRAM cell having a severe short channel effect can be stabilized by applying a back bias.
[0073]
Next, as shown in FIG. 8 (7), a protective film 75 for protecting the gate of the DRAM region is formed on the entire surface by, for example, a thin silicon nitride film (for example, a thickness of 10 nm to 50 nm). This protective film 75 is later formed in a sidewall shape on the side wall on the word line 16 in the DRAM region, and contributes to securing the breakdown voltage on the side wall of the word line 16 when the salicide is formed.
[0074]
Subsequently, as shown in (8) of FIG. 9, the dummy gate in the standard voltage logic region is patterned. First, a resist film 96 is formed on the entire surface, and the resist film 96 is processed into a gate electrode pattern in a standard voltage logic region by, for example, a lithography technique. At this time, the DRAM region is covered and protected with a resist film 96, and the resist film 96 on the high voltage logic region is removed.
[0075]
As shown in FIG. 10 (9), the protective film 75, the buffer layer 74 and the gate electrode formation film 73 are etched using the resist film 96 as an etching mask to form a dummy gate 76 in the standard voltage logic region. In this etch back processing, a silicon oxide film formed as the gate insulating film 15 is used as an etching stopper. In this etching, etch back processing is performed in the high voltage logic region, and the gate electrode formation film 73 is buried in the groove 14 formed in the high voltage logic region via the gate insulating film 15. Is formed. Thereafter, the resist film 96 is removed.
[0076]
Next, as shown in (10) of FIG. 11, a resist film (not shown) having an opening over the n-channel transistor formation region in the standard voltage logic region is formed, and then the resist film and the dummy gate 76 are masked. Then, ion implantation is performed on the semiconductor substrate 11 to form low-concentration diffusion layers 52 and 52 of n-channel transistors. Thereafter, the resist film is removed. Similarly, a resist film (not shown) opened on the p-channel transistor formation region in the standard voltage logic region is formed, and then the semiconductor substrate is formed using the resist film and dummy gate (not shown) as a mask. 11 is ion-implanted to form a low-concentration diffusion layer (not shown) of the p-channel transistor. Thereafter, the resist film is removed.
[0077]
Further, similarly, a resist film (not shown) opened on the n-channel transistor formation region in the high voltage logic region is formed, and then the resist film and the gate electrode 61 are used as a mask on the semiconductor substrate 11. Ion implantation is performed to form lightly doped diffusion layers 62 and 62 of the n-channel transistor. Thereafter, the resist film is removed. Similarly, a resist film (not shown) opened on the p-channel transistor formation region in the high voltage logic region is formed, and then the semiconductor substrate is formed using the resist film and gate electrode (not shown) as a mask. 11 is ion-implanted to form a low-concentration diffusion layer (not shown) of the p-channel transistor. In this ion implantation in the high voltage logic region, since the gate electrode 61 is formed along the groove 14 formed in the semiconductor substrate 11, ion implantation with relatively high energy is required. Thereafter, the resist film is removed.
[0078]
Next, as shown in FIG. 12 (11), a sidewall formation film 77 is formed on the entire surface. The sidewall formation film 77 is preferably formed of silicon oxide having a lower stress than silicon nitride and having good peelability by wet treatment. Alternatively, a stacked film of a silicon oxide film and a silicon nitride film or a silicon oxynitride film can be used. Thereafter, a resist film 97 is formed on the entire surface, and the resist film 97 in the logic area is removed by lithography, for example, and the DRAM film is protected by leaving the resist film 97 in the DRAM area. In this state, the sidewall formation film 77 is etched back.
[0079]
As a result, as shown in (12) of FIG. 13, the sidewall 54 is formed by the sidewall formation film 77 on the sidewall of the dummy gate 76 in the standard voltage logic region. At this time, a sidewall 64 is also formed on the sidewall of the trench 14 in the high voltage logic region. The side wall 64 has a function of protecting the side wall of the gate.
[0080]
Next, a resist film (not shown) having an opening over the n-channel transistor formation region in the standard voltage logic region is formed, and then the semiconductor substrate 11 is formed using the resist film, the dummy gate 76, and the sidewalls 54 as a mask. Ion implantation is performed to form n-channel transistor diffusion layers 55 and 55 so as to leave the low concentration diffusion layer 52 on the dummy gate 76 side. Thereafter, the resist film is removed. Similarly, a resist film (not shown) having an opening over the p-channel transistor formation region in the standard voltage logic region is formed, followed by the resist film, dummy gate (not shown), and sidewall (not shown). ) As a mask to form a p-channel transistor diffusion layer (not shown) so as to leave a low-concentration diffusion layer (not shown) on the dummy gate side. Thereafter, the resist film is removed.
[0081]
Further, similarly, a resist film (not shown) opened on the n-channel transistor formation region in the high voltage logic region is formed, and then the resist film and the gate electrode 61 are used as a mask on the semiconductor substrate 11. Ion implantation is performed to form the diffusion layers 65 and 65 of the n-channel transistor so as to leave the low concentration diffusion layer 62 in the lower layer. Thereafter, the resist film is removed. Similarly, a resist film (not shown) opened on the p-channel transistor formation region in the high voltage logic region is formed, and then the semiconductor substrate is formed using the resist film and gate electrode (not shown) as a mask. 11 is ion-implanted, and a p-channel transistor diffusion layer (not shown) is formed so as to leave a low-concentration diffusion layer (not shown) in the lower layer. Thereafter, the resist film is removed.
[0082]
Next, as shown in FIG. 14 (13), after a resist film 98 is formed on the entire surface, the resist film 98 in the DRAM region is removed by lithography, and patterning is performed so as to cover the logic region with the resist film 98. Do. Next, using the resist film 98 as a mask, the sidewall formation film 77 made of silicon oxide in the DRAM region is etched back, for example, by wet processing. In this etching, the protective film 75 made of silicon nitride formed immediately above the word line 16 of the previously formed DRAM serves as an etching stopper.
[0083]
Further, using the resist film 93 as it is, the protective film 75 in the DRAM region is etched by, for example, reactive ion etching (RIE) to expose the word line 16 in the DRAM region. As a result. A side wall 17 made of a protective film 75 is formed on the side wall of the groove 14 on the word line 16. This side wall 17 has a function of protecting the side wall. In the reactive ion etching, it is important to prevent the diffusion layer 13 in the DRAM region from being exposed, that is, to leave the buffer layer 72 on the diffusion layer 13. Thereafter, the resist film 98 is removed.
[0084]
Further, as shown in (14) of FIG. 15, by using a normal silicidation technique, the diffusion lines 55 and 65 in the logic region, the gate electrode 61 in the high voltage logic region, and the word line 16 in the DRAM region. A silicide layer 58, 68, 69, 18 is selectively formed thereon. At this time, since the buffer layer 74 made of a silicon oxide film is formed on the top of the dummy gate 76, no silicide layer is formed. In this manner, the silicide layers 58 and 68 are selectively formed on the diffusion layers 55 and 65 in the logic region where low resistance needs to be realized, on the gate electrode 61 in the high voltage logic region, and on the word line 16 in the DRAM region. 69, 18 are formed. As this silicide layer, for example, cobalt silicide (CoSi) ₂ ), Titanium silicide (TiSi) ₂ Nickel silicide (NiSi) ₂ ) Etc. can be used.
[0085]
Thereafter, a cap insulating film 78 is formed on the entire surface by, for example, a silicon nitride film. The cap insulating film 78 is effective in suppressing junction leakage in the salicide forming portion, but it is not necessary to form the cap insulating film 78 if unnecessary.
[0086]
Next, as shown in (15) of FIG. 16, after a first insulating film (insulating film) 19 is formed on the entire surface, the surface of the first insulating film 19 is planarized by CMP. The method for planarizing the surface of the first insulating film 19 is not limited to CMP as long as the planarization can be realized, and for example, an etch back method or the like can be used. Thereafter, after a resist film 99 is formed on the first insulating film 19, a connection hole pattern 100 for a diffusion layer extraction contact in the DRAM region is formed in the resist film 99 by lithography.
[0087]
Next, as shown in (16) of FIG. 17, the resist film 99 (see (15) of FIG. 9) is used as an etching mask to penetrate the first insulating film 19 into the diffusion layer 13 in the DRAM region. A connecting hole 20 is formed. At this time, since the word line (gate electrode) 16 in the DRAM region is disposed below the surface of the semiconductor substrate 11 rather than the diffusion layer 13 to be contacted, it is not necessary to use a special technique such as self-alignment contact. Further, it is desirable that the opening diameter of the connection hole 20 be as large as possible so that the entire surface of the DRAM diffusion layer 13 can be in contact with the extraction electrode. Thereby, the contact resistance is reduced.
[0088]
In the drawing, the state in which the alignment is slightly shifted is intentionally described. However, if excessive over-etching is not performed when the connection hole is opened, the physical structure of the word line extraction electrode formed in the connection hole 20 in a later step is described. It is possible to ensure a sufficient distance. In the projection design seen from above, the connection hole 20 completely overlaps the word line (gate electrode) 16.
[0089]
Next, an extraction electrode forming film 79 is formed on the first insulating film 19 so as to fill the connection hole 20. The extraction electrode formation film 79 is formed of, for example, phosphorus-doped polysilicon. As the extraction electrode forming film 79 for extracting the diffusion layer, phosphorus-doped polysilicon is desirably selected in consideration of reduction of junction leakage in the DRAM region as usual. Thereafter, heat treatment for activating the phosphorus-doped polysilicon is performed. As this heat treatment, rapid heating treatment at about 900 ° C. (hereinafter referred to as RTA, RTA is an abbreviation for Rapid Thermal Annealing) is required. After that, since it is a step of forming a gate electrode in the logic region, it is necessary to avoid any high-temperature heat treatment.
[0090]
Thereafter, as shown in FIG. 18 (17), the excessive extraction electrode formation film 79 (phosphorus-doped polysilicon) on the first insulating film 19 is removed by CMP, for example, and the diffusion layer is formed in the connection hole 20. 13 is formed, and the first insulating film 19 is polished to flatten the surface. At this time, the upper portion of the dummy gate 76 in the surface voltage logic region is exposed.
[0091]
Next, as shown in FIG. 19 (18), a cap insulating film 80 is formed on the first insulating film 19 with a silicon nitride film, for example, to protect the extraction electrode 21 for extracting the diffusion layer formed in the DRAM region. To do. Then, after forming a resist film (not shown), the resist film (not shown) is left only in the DRAM region by lithography. Since the cap insulating film 80 is removed by CMP performed in a later step, the cap insulating film 80 is not limited to the silicon nitride film. In addition to silicon nitride, silicon oxide can be used as an example. Thereafter, the dummy gate 76 (see (17) in FIG. 18) in the standard voltage logic region is removed.
[0092]
As a result, a groove 81 is formed in the portion where the dummy gate is removed. The dummy gate can be removed by reactive ion etching because the base is made of silicon oxide, or can be removed by wet etching with sulfuric acid / hydrogen fluoride.
[0093]
Then, as shown in FIG. 20 (19), after forming the gate insulating film 82 in the logic region on the inner wall of the groove 81, a gate electrode forming film 83 is formed so as to fill the groove 81. The gate insulating film 82 and the gate electrode forming film 83 are also formed on the cap insulating film 80. The gate insulating film 82 is formed of a silicon oxide film, but a high dielectric film such as zirconium oxide, hafnium oxide, tantalum oxide, aluminum oxide, or BST can also be used. The gate electrode forming film 83 is generally formed of a laminated film of a tungsten film 83W / titanium nitride film 83T.
[0094]
The excess gate insulating film 82 and the gate electrode formation film 83 on the first insulating film 19 are removed by CMP again, and the gate insulating film 82 is formed in the trench 81 as shown in FIG. Then, the gate electrode 51 made of the gate electrode formation film 83 is formed, and the surface of the first insulating film 19 is planarized. As a result, the upper portion of the gate electrode 51 in the standard voltage logic region is exposed. At this time, the upper portion of the extraction electrode 21 for extracting the diffusion layer in the DRAM region is also polished, but there is no problem.
[0095]
Next, a second insulating film (cap insulating film) 22 is formed on the first insulating film 19 so as to cover the extraction electrode 21 in the DRAM region and the gate electrode 51 in the logic region.
[0096]
Thereafter, as shown in (21) of FIG. 22, a normal DRAM process is performed. That is, after forming the second insulating film 22, the bit contact hole 23 is formed. Next, a bit line 24 made of a metal electrode is formed. The bit line 24 is formed by forming an adhesion layer 24a under the bit line 24 and forming an offset insulating film 25 over the bit line 24. Thereafter, an etching stopper layer 26 and a third insulating film 27 covering the bit line 24 are formed. Then, the surface of the third insulating film 27 is planarized. Next, a connection hole 28 connected to the extraction electrode 21 is formed in the third insulating film 27 by a technique for forming a self-aligned contact. A sidewall insulating film 29 is formed in the connection hole 28 in order to insulate from the bit line 24.
[0097]
Next, a capacitor 31 having an MIM (Metal / insulator / Metal) structure that does not require heat treatment is formed. The lower electrode 32 of the capacitor is connected to the extraction electrode 21 through the connection hole 28. The capacitor 31 having the MIM structure is expected to be indispensable for a DRAM of 0.1 μm or more. At present, as an example, the upper and lower electrodes 34 and 32 are made of ruthenium (Ru) or ruthenium oxide (RuO) based materials. The dielectric film 33 of BST (BaTiO _Three And SrTiO _Three A mixed crystal) film is used.
[0098]
Next, a fourth insulating film 35 is formed on the third insulating film 27 so as to cover the MIM structure capacitor 31. Thereafter, the surface of the fourth insulating film 35 is planarized by CMP. Next, the capacitor take-out electrode, the word line take-out electrode, the bit line take-out electrode, the diffusion layer take-out electrode in the standard voltage logic region, the gate take-out electrode in the logic region, the high voltage are applied to the fourth insulating film 35 to the first insulating film 19. Connection holes 111, 112, 113, 114 a, 114 b, 115, 116 a, 116 b, etc. are formed for forming a diffusion layer extraction electrode in the logic region.
[0099]
Further, in the connection holes 111 to 116b and the like, the capacitor extraction electrode 121, the word line extraction electrode 122, the bit line extraction electrode 123, the diffusion layer extraction electrodes 124a and 124b in the standard voltage logic region, the gate extraction electrode 125 in the logic region, Diffusion layer extraction electrodes 126a and 126b in the voltage logic region are formed. Further, a fifth insulating film 36 is formed on the fourth insulating film 35. Next, each wiring groove 131 reaching each extraction electrode 121 to 126 is formed in the fifth insulating film 36, and the first wiring 141 is formed in the wiring groove 131. The first wiring 41 is made of, for example, a copper wiring. Although not shown, an upper layer wiring is further formed as necessary.
[0100]
In the semiconductor device manufacturing method, since the silicide layer 18 is formed on the word line 16, the resistance of the word line 16 is reduced and the delay problem is avoided. Further, since the silicide layers 58 and 68 are formed on the diffusion layers 55 and 65 of the logic element, the contact resistance to the diffusion layers 55 and 65 is reduced.
[0101]
Further, since the diffusion layer 13 in the DRAM region is formed on the surface side of the semiconductor substrate 11 and the word line 16 is formed in the semiconductor substrate 11 via the gate insulating film 15, the channel is a word line (gate electrode). It is formed so as to go around the semiconductor substrate 11 on the bottom side of the groove 14 in which 16 is formed. Therefore, since an effective channel length is sufficiently ensured, a back bias is applied to stabilize the transistor characteristics of a memory element (eg, DRAM) having a severe short channel effect.
[0102]
Further, in the method of manufacturing the semiconductor device 1, the word line is formed on the word line 16 embedded in the groove 14 formed in the semiconductor substrate 11 through the gate insulating film 15 through the first insulating film 19. Since the extraction electrode 21 connected to the diffusion layer 13 formed on the surface of the semiconductor substrate 11 is formed so as to overlap with the semiconductor substrate 11, the first insulating film 19 on the word line 16 has a sufficient thickness of 20 nm to 30 nm or more. Film thickness is secured. Therefore, a withstand voltage with respect to the extraction electrode 21 connected to the diffusion layer 13 is ensured. Further, since the entire surface of the DRAM region on the diffusion layer 13 can be used as a contact, the effective area can be used effectively. Therefore, the lowest resistance value that can be realized by the cell design can be realized, and the contact resistance can be reduced.
[0103]
Further, since the diffusion layer 13 in the DRAM region is formed with a low impurity concentration in the depth direction due to the impurity diffusion, the electric field at the junction can be relaxed, and the performance of data retention characteristics is maintained.
[0104]
In addition, in order to realize a high driving force transistor in the standard voltage logic region, a single chip of a logic transistor having a gate electrode 51 formed by replacement and a DRAM is realized. As a result, the gate electrode 51 in the standard voltage logic region does not require care for heat treatment, the gate insulating film 82 can be made of a high dielectric constant material, and the gate electrode 51 can be formed of a polymetal structure or a metal material. It becomes possible.
[0105]
In addition, by the above manufacturing method, a high voltage logic element that enables high voltage operation necessary for boosting a word line of an analog circuit, an external interface, or a memory element can be mixedly mounted on a single semiconductor substrate 11 together with a standard voltage logic element. become.
[0106]
The technique used for the DRAM region can also be applied to the manufacture of a general-purpose DRAM memory chip.
[0107]
【The invention's effect】
As described above, the semiconductor device of the present invention is Set According to the manufacturing method, since the silicide layer is formed in the upper layer of the word line, the word line resistance can be reduced, and the problem of delay of the word line, which is a problem in microfabrication, can be avoided. Further, since the silicide layer is formed on the diffusion layer of the logic element, the contact resistance to the diffusion layer can be reduced.
[0108]
In addition, since the diffusion layer is formed on the semiconductor substrate surface side and the word line is embedded in the groove formed in the semiconductor substrate via the gate insulating film, the channel is on the groove bottom side where the word line is formed It is formed so as to go around the semiconductor substrate. Therefore, since the effective channel length of the cell transistor in the memory element region is sufficiently secured, the transistor characteristics of the memory element (for example, DRAM) having a severe short channel effect are stabilized by applying the back bias.
[0109]
Further, in the upper projection design, the extraction electrode of the diffusion layer in the memory element region and the word line (gate electrode) can be overlapped, and the cell can be miniaturized. Therefore, there is no need for a distance for securing a breakdown voltage between the word line and the extraction electrode in the substrate surface direction. In addition, it is easy to secure the interlayer breakdown voltage between the word line and the diffusion layer lead-out contact. Therefore, since the entire surface on the diffusion layer of the memory element is used for the contact, the effective area can be used effectively. Therefore, since the lowest resistance value that can be realized by the cell design is realized, the contact resistance can be reduced.
[0110]
In addition, it is not necessary to increase the concentration of the semiconductor substrate below the diffusion layer in the memory element region as required for the cell transistor, and the diffusion layer in the memory element region has a low impurity concentration in the depth direction. It becomes possible to alleviate the electric field of the junction, and it is possible to maintain the performance of data retention characteristics that are becoming more severe as the memory cell area is reduced.
[0111]
In addition, a logic transistor having a replacement gate electrode for realizing a high driving force transistor in the logic region and a memory element can be realized in one chip. As a result, the gate in the logic region does not require care for heat treatment, it is possible to use a high dielectric constant material for the gate insulating film, and the gate electrode can be formed with a polymetal structure.
[0112]
In order to realize a high driving force transistor in the logic region, the replacement gate electrode and the DRAM can be made into one chip. As a result, the gate in the logic region does not require care for heat treatment, and the gate insulating film is made of zirconium oxide, hafnium oxide, tantalum oxide, aluminum oxide, BST (BaTiO3). _Three And SrTiO _Three And the like, and Cu / TiN, W / TiN or the like can be used for the gate electrode, and the performance of the logic element can be improved.
[0113]
A high voltage logic element that enables high voltage operation necessary for boosting the word line of an analog circuit, an external interface, or a memory element can be mounted together with a standard voltage logic element on a single semiconductor substrate.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view showing an example of an embodiment of a semiconductor device according to the present invention.
FIG. 2 is a schematic cross-sectional view (1) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.
FIG. 3 is a schematic cross-sectional view (2) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.
FIG. 4 is a schematic cross-sectional view (3) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention.
FIG. 5 is a schematic cross-sectional view (4) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 6 is a schematic cross-sectional view (5) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 7 is a schematic cross-sectional view (6) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 8 is a schematic cross-sectional view (7) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 9 is a schematic cross-sectional view (8) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 10 is a schematic cross-sectional view (9) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 11 is a schematic cross-sectional view (10) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 12 is a schematic cross-sectional view (11) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 13 is a schematic cross-sectional view (12) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 14 is a schematic cross-sectional view (13) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 15 is a schematic cross-sectional view (14) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 16 is a schematic cross-sectional view (15) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 17 is a schematic cross-sectional view (16) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 18 is a schematic cross-sectional view (17) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 19 is a schematic cross-sectional view (18) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 20 is a schematic cross-sectional view (19) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
FIG. 21 is a schematic cross-sectional view (20) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention;
22 is a schematic cross-sectional view (21) showing an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention; FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Semiconductor substrate, 12 ... Element isolation region, 13, 55, 65 ... Diffusion layer, 14 ... Groove, 15, 82 ... Gate insulating film, 16 ... Word line, 18, 58, 68 ... Silicide layer, 19 ... 1st Insulating film, 21 ... take-out electrode, 51, 61 ... gate electrode

Claims (2)

In a method for manufacturing a semiconductor device in which a memory element and a logic element are formed on the same semiconductor substrate,
Forming a diffusion layer of the memory element region on the semiconductor substrate surface side after forming the element isolation region in the semiconductor substrate;
Forming a groove at a predetermined position of the memory element region and the first logic element region in the semiconductor substrate and the element isolation region;
Forming a gate insulating film in the trench;
Forming a word line that fills the groove while leaving the upper part of the groove in the memory element region; and
Forming a dummy gate on the semiconductor substrate of the second logic element region in the same layer as the word line, and forming a gate electrode in the groove of the first logic element region;
Forming a diffusion layer of a logic transistor on the semiconductor substrate in the first and second logic element regions;
Forming a sidewall insulating film on the trench sidewall on the word line;
Forming a silicide layer on the word line upper layer and the diffusion layer upper layer of the first and second logic element regions;
Forming an insulating film so as to fill the upper portion of the groove and cover the dummy gate;
Forming a connection hole in a state of overlapping with the word lines via the insulating film over the word line from the diffusion layer reaches the entire surface of the diffusion layer,
Forming an extraction electrode in contact with the entire surface of the diffusion layer in the connection hole in a state overlapping with the word line via the insulating film ;
Planarizing the insulating film surface and exposing an upper portion of the dummy gate;
Performing a heat treatment for activating the extraction electrode;
Removing the dummy gate to form a gate groove;
And a step of forming a gate electrode in the gate trench with a gate insulating film interposed therebetween. Method of manufacturing the diffusion layer is a semiconductor device according to claim 1, wherein the forming so that the impurity concentration becomes thinner in the depth direction.

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