KR20010004040A - Method of manufacturing SOI device - Google Patents

Abstract

PURPOSE: A method for fabricating an SOI device is to disperse a heat generated by an ESD current with ease, thereby stabilizing an operational characteristic of the SOI device. CONSTITUTION: The method comprises the steps of: providing a silicon wafer having a field oxide for defining the first region(A) in which an ESD(Electro-Static Discharge) circuit is to be formed and the second region(B) except the first region; forming an ion implantation mask on the second region; implanting oxygen ions into the first region and the ion implantation mask; removing the ion implantation mask; thermal annealing the resultant silicon wafer to divide the silicon wafer into a base layer and a semiconductor layer and form a buried oxide layer in which a portion to be formed at the first region has a depth greater than a portion to be formed at the second region; forming a gate electrode having a gate oxide interposed therebetween on the semiconductor layer corresponding to the first region and the second region; and forming a source/drain region at both sides of the gate electrode on the semiconductor layer such that the source/drain region of the first region has a depth not to be in contact with the buried oxide layer.

Description

Method of manufacturing SOI device {Method of manufacturing SOI device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an SOH element, and more particularly, to a method for manufacturing an SOH element having an electrostatic protection circuit for preventing a decrease in device operating characteristics due to static electricity.

As high integration and high performance of semiconductor devices have progressed, semiconductor integration technologies using silicon on insulator (SOI) wafers have been attracting attention instead of silicon wafers made of bulk silicon. Here, the SOI wafer has a structure in which an investment oxide film is interposed between a base substrate, which is a supporting means, and a semiconductor layer, on which the device is to be formed. It is manufactured by the SIMP (seperation by implanted oxygen) method of deeply implanting ions.

For example, transistors formed on SOI wafers have the advantage that, unlike transistors formed on bulk silicon wafers, a separate well process is not required. In particular, the semiconductor layer on which the device is to be formed is a thin film, and the source and drain Since the region is formed to be in contact with the buried oxide film, the junction capacitance can be reduced, and thus, it can be used as a high speed and low power device.

In addition, when the thickness of the semiconductor layer is 100 nm or less, the on current can be increased, and the active region is completely separated by the device isolation film and the buried oxide film, so latch-up is a major problem of the CMOS transistor. ) Does not cause problems.

However, the device formed on the SOI wafer has various advantages as described above, but has a problem that the electro-static discharge (ESD) characteristics are very weak.

More specifically, in order to protect the internal circuit from the impact of external static electricity, as shown in Figs. 1 and 2, ESD protection circuits 10 and 20 made of NMOS or CMOS are formed. In this case, a method of drawing heat generated by the ESD current injected from the outside toward the grounded well or the source terminals 5 and 15 is taken. Here, reference numeral 1 denotes a silicon wafer, 2 and 12 are gate insulating films, 3 and 13 are gate electrodes, 4a and 14a are source electrodes, 4b and 14b are drain electrodes, 11a is a base substrate, and 11b is an investment investment oxide, 11c is a semiconductor layer and 11 is an SOI wafer.

However, as shown in FIG. 1, when the ESD protection circuit 12 is formed on the bulk silicon wafer 10, heat generated by the ESD current easily escapes to the outside through silicon having excellent heat transfer characteristics. 2, when the ESD protection circuit 20 is formed on the SOI wafer 11 having the investment oxide film 11b, the heat transfer path is blocked by the investment oxide film 11b, so that the ESD current The heat generated by is not easily released to the outside.

That is, when the ESD protection circuit is formed on the SOI wafer 11, the ESD current is due to the bottom surfaces of the source and drain regions 14a and 14b contacting the buried insulating layer 2, and thus the source and drain regions ( Only through the edge regions 14a, 14b). Therefore, in the case of the ESD protection circuit formed on the SOI wafer, compared to the ESD circuit formed on the bulk silicon wafer, more current is concentrated in the semiconductor layer 11c, and the heat generated by the ESD current causes the semiconductor layer 11c to As the temperature increases, this results in instability of device operation.

Accordingly, an object of the present invention is to provide a method for manufacturing an SOI device, which is designed to solve the above problems and can easily disperse heat generated by an ESD current.

1 is a cross-sectional view showing an electrostatic protection circuit formed on a conventional silicon wafer.

2 is a cross-sectional view showing an electrostatic protection circuit formed on a conventional SOH wafer.

Figure 3a to Figure 3c is a cross-sectional view for each process for explaining the manufacturing method of the SOH element according to an embodiment of the present invention.

Figures 4a to 4c is a cross-sectional view for each process for explaining the manufacturing method of the SOH element according to another embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

30 silicon wafer 31,71 base layer

32a, 32b, 72: buried oxide film 33a, 33b, 73: semiconductor layer

40, 81: device isolation layer 41: ion implantation mask

42: oxygen ion 43: gate oxide film

44 gate electrode 45a, 45c source region

45b, 45d: Drain area 50: ESD protection circuit

60: MOS transistor 80: SOI wafer

82: antioxidant film 83: oxide film

In accordance with an aspect of the present invention, there is provided a method of manufacturing an SOI device, including: providing a silicon wafer having an isolation layer defining a first region in which an electrostatic protection circuit is to be formed and a second region other than the second region; Forming an ion implantation mask on a second region of the silicon wafer; Implanting oxygen ions into the exposed first region of the silicon wafer and the second region covered by the ion implantation mask; Removing the ion implantation mask; Heat-treating a silicon wafer implanted with oxygen ions to separate the silicon wafer into a base layer and a semiconductor layer in the silicon wafer, and a buried oxide film having a depth deeper than a portion formed in the first region is formed in the first region. Forming a; Forming a gate electrode interposed with a gate oxide film on the semiconductor layers of the first and second regions; And forming a source / drain region in the semiconductor layer portions at both sides of the gate electrode, and forming the source / drain region of the first region to a depth not in contact with the buried oxide film.

In addition, another method of manufacturing an SOI device of the present invention for achieving the above object comprises the steps of providing an SOH wafer having a laminated structure of the base layer, the buried oxide film and the semiconductor layer; Forming an isolation layer in the semiconductor layer to define a first region in which the electrostatic protection circuit is to be formed and a second region other than the buried oxide film; Forming an anti-oxidation film overlying the semiconductor layer to cover the first region thereof; Performing a thermal oxidation process to form an oxide film in a second region of the exposed semiconductor layer; Removing the anti-oxidation film and the field oxide film to obtain a semiconductor layer having a first region where an electrostatic protection circuit is to be formed relatively thicker than a second region; Forming a gate electrode interposed with a gate oxide film on first and second regions of the semiconductor layer; And forming a source / drain region in the semiconductor layer portions at both sides of the gate electrode, and forming the source / drain region of the first region to a depth not in contact with the buried oxide film.

According to the present invention, in forming the ESD protection circuit, since its source and drain regions are formed so as not to be in contact with the buried oxide film, heat generated by the ESD current can be easily released to the outside, and thus, the SOI device It is possible to prevent the deterioration in operating characteristics.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3C are cross-sectional views of respective processes for describing a method of manufacturing an SOI device according to an exemplary embodiment of the present invention.

First, as shown in FIG. 3A, a bulk silicon wafer 30 is provided, and an area A (hereinafter, referred to as a first region) in which an ESD protection circuit is to be formed and a cell region other than B (hereinafter, referred to as a second region) are formed. ) Is formed on a predetermined portion of the silicon wafer 30 through a shallow trench isolation process.

Then, an ion implantation mask 41 covering the second region B, except for the first region A on which the ESD protection circuit is to be formed, is formed on the silicon wafer 30, for example, a photoresist pattern. Oxygen ions 42 are implanted into both the exposed first region A of the silicon wafer 30 and the second region B covered by the ion implantation mask 41 in an energy range of 10 to 1,000 KeV. At this time, since the first region A of the silicon wafer 30 is exposed while the second region B is covered by the ion implantation mask 41, oxygen ions implanted into the silicon wafer 30 are ion-exposed. The ion implantation depth of 42 is such that the first region A is deeper than the second region B.

Meanwhile, in the ion implantation process, the first region A of the exposed silicon wafer 30 may be damaged. Therefore, in order to prevent damage by ion implantation, a damage prevention layer (not shown) is formed on the first region A of the exposed silicon wafer 30 before the ion implantation process. Here, an oxide film is used as the damage prevention layer, and the oxide film is formed to a thickness of 50 to 1,000 Pa by a wet or dry oxidation process at a temperature of 700 to 1,200 ° C.

Next, as shown in FIG. 3B, in the state where the ion implantation mask covering the second region B of the silicon wafer is removed, the silicon wafer in which oxygen ions are ion implanted is heat-treated, and then 500 in the silicon wafer. The buried oxide films 32a and 32b having a thickness of ˜5,000 kPa are formed. As a result, the silicon wafer is separated into the base layer 31, the buried oxide films 32a and 32b, and the semiconductor layers 33a and 33b.

Here, the buried oxide films 30a and 30b are implanted into the first region A because oxygen ions are implanted at different depths in the first region A and the second region B of the silicon wafer. The depth of the buried oxide film 30a formed is deeper than the depth of the buried oxide film 30b formed in the second region B. Accordingly, the thickness of the semiconductor layer portion 33a on which the ESD circuit is to be formed is a portion other than that ( It becomes relatively thicker than the thickness of 33b).

Next, as shown in FIG. 3C, the gate electrode having the gate oxide film 43 interposed in each of the first region A and the second region B in a known manner on the semiconductor layers 33a and 33b. 44 is formed, and ion-implanted impurities of a predetermined conductivity type are implanted into portions of the semiconductor layers 33a and 33b on both sides of the gate electrode 44 to form source and drain regions 45a, 45b, 45c, and 45d. do. As a result, an ESD protection circuit 50 having a MOS structure is formed in the first region A of the silicon wafer, and a general MOS transistor 60 is formed in the second region B. As shown in FIG. At this time, since the semiconductor layer portion 33a of the first region A in which the ESD protection circuit is to be formed has a relatively thicker thickness than the semiconductor layer portion 33b in which the MOS transistor 60 is to be formed, impurities are formed at the same energy. In the case of ion implantation, the source / drain regions 45a and 45b in the ESD protection circuit 50 do not contact the buried oxide film 32a, while the source / drain regions 45c and 45d in the MOS transistor are buried oxide films. It comes in contact with (32b).

Therefore, when the ESD protection circuit 50 is formed in the first region A in the same manner as described above, the source / drain regions 45a and 45b of the ESD protection circuit 50 are buried in the buried oxide film 32a. Since there is no contact, even when an ESD current flows into the ESD protection circuit 50, the ESD current can be effectively dispersed.

Therefore, since the reliability of the ESD protection circuit 50 can be improved, the deterioration of the device operation characteristics by the ESD is not generated, and the MOS transistors other than the ESD protection circuit 50 are not provided with the source / drain thereof. Since the regions 45c and 45d are in contact with the buried oxide film 32b, the junction capacitance is small, so that the advantages of the SOI element can be maintained.

4A to 4C are cross-sectional views illustrating processes for manufacturing a SOI device according to another exemplary embodiment of the present invention. In this embodiment, a thickness of a semiconductor layer in which an ESD protection circuit is to be formed and a general MOS transistor are formed. In order to make the thickness of the semiconductor layer different, the following process is performed.

First, as shown in FIG. 4A, an SOI wafer 80 in which a base layer 71, an investment oxide film 72, and a semiconductor layer 73 are sequentially stacked is prepared. Then, a trench isolation process is performed in which the device isolation layer 81 defining the first region A and the second region B, in which the ESD protection circuit is to be formed, is formed in a predetermined portion of the semiconductor layer 73. The anti-oxidation film 82 is formed on the first region A of the semiconductor layer 73.

Next, as shown in FIG. 4B, a thermal oxidation process is performed to form an oxide film 83 in the second region B of the exposed semiconductor layer 73, and as shown in FIG. 4C. The anti-oxidation film covering the first region A of the semiconductor layer 73 and the oxide film formed in the second region B of the semiconductor layer 73 are removed to form the first region A in which the ESD protection circuit is to be formed. ), A semiconductor layer 73 having a thickness relatively thicker than that of the second region B in which the MOS transistor is to be formed is obtained.

Subsequently, although not shown, a process similar to the above-described embodiment is performed to form an ESD protection circuit in which the source / drain region does not come into contact with the buried oxide film, and the source / drain region is formed in the second region. A MOS transistor in contact with the buried oxide film is formed.

As described above, in the present invention, in forming the SOI device, the thickness of the semiconductor layer portion in which the ESD protection circuit is to be formed is made relatively thicker than the other portions, so that the source / drain regions of the ESD protection circuit are formed with the investment oxide film. The source / drain regions of the MOS transistors other than the ESD protection circuit may be formed to be in contact with the buried oxide film.

Therefore, since the reliability of the ESD protection circuit can be improved, the operation characteristics of the SOI element can be improved, and the high-speed and low-power element can be realized because the characteristics of the SOI element can be maintained as it is. .

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (8)

Providing a silicon wafer having an isolation layer defining a first region in which an electrostatic protection circuit is to be formed and a second region other than the second region; Forming an ion implantation mask on a second region of the silicon wafer; Implanting oxygen ions into the exposed first region of the silicon wafer and the second region covered by the ion implantation mask; Removing the ion implantation mask; Heat-treating a silicon wafer implanted with oxygen ions to separate the silicon wafer into a base layer and a semiconductor layer in the silicon wafer, and a buried oxide film having a depth deeper than a portion formed in the first region is formed in the first region. Forming a; Forming a gate electrode interposed with a gate oxide film on the semiconductor layers of the first and second regions; And Forming a source / drain region in a portion of the semiconductor layer on both sides of the gate electrode, wherein the source / drain region of the first region is formed to a depth not in contact with the buried oxide film; Manufacturing method. The method of claim 1, wherein the ion implantation mask is a photoresist pattern. According to claim 1, Before the oxygen ion implantation step, And forming a damage prevention layer on the first region of the exposed silicon wafer. The method of claim 3, wherein the damage prevention layer is an oxide film. The method of claim 4, wherein the oxide film is formed to a thickness of 50 to 1,000 Pa by a wet or dry oxidation process at a temperature of 700 to 1,200 ° C. 6. The method of claim 1, wherein the oxygen ions are implanted in an energy range of 10 to 1,000 KeV. The method of claim 1, wherein the buried oxide film is formed to a thickness of 500 ~ 5,000Å. Providing an SOH wafer having a laminated structure of a base layer, an investment oxide film, and a semiconductor layer; Forming an isolation layer in the semiconductor layer to define a first region in which the electrostatic protection circuit is to be formed and a second region other than the buried oxide film; Forming an anti-oxidation film overlying the semiconductor layer to cover the first region thereof; Performing a thermal oxidation process to form an oxide film in a second region of the exposed semiconductor layer; Removing the anti-oxidation film and the field oxide film to obtain a semiconductor layer having a first region where an electrostatic protection circuit is to be formed relatively thicker than a second region; Forming a gate electrode interposed with a gate oxide film on first and second regions of the semiconductor layer; And Forming a source / drain region in a portion of the semiconductor layer on both sides of the gate electrode, wherein the source / drain region of the first region is formed to a depth not in contact with the buried oxide film; Manufacturing method.