KR20010001595A - Method for forming capacitor - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor is to provide a high dielectric layer such as Ta2o5, BST needed in a high temperature subsequent thermal process by forming a stable storage node contact in a high temperature acid-resistant atmosphere, and to eliminate a Pt etching problem by forming the Pt layer by a superior electroplating method. CONSTITUTION: An interlayer dielectric formed on a semiconductor substrate is selectively etched to form a contact hole. A stacked structure consisting of a plug, a diffusion blocking layer and a metal oxide layer(16) is formed in the contact hole. A capacitor storage electrode(17) adjacent to the metal oxide layer is formed. A dielectric layer(18) is formed on the storage electrode. A plate electrode(19) of a capacitor is formed on the dielectric layer.

Description

Capacitor Manufacturing Method {METHOD FOR FORMING CAPACITOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor memory device manufacturing, and more particularly, to a method of manufacturing a capacitor capable of preventing oxidation of a diffusion barrier formed between a lower electrode and a polycrystalline silicon plug.

Currently, semiconductor memory devices can be classified into read / write memory and read-only memory (ROM). In particular, the read / write memory is divided into a dynamic RAM (hereinafter referred to as DRAM) and a static RAM.

DRAM is a device that is one of the most advanced in the integration of one transistor (transistor) and one capacitor unit cell (unit cell).

As the degree of integration of semiconductor devices is increased to more than one gigabyte of dynamic random access memory (DRAM), high capacitance of a capacitor is required. A stacked structure of a silicon oxide film and a silicon nitride film or a tantalum oxide film (Ta ₂ O ₅ ), which is used as a conventional storage material, cannot cope with the required capacitance, and thus a higher dielectric constant such as (Ba, Sr) TiO ₃ (BST) Attempts have been made to use thin films of materials having constants as dielectric films.

In the capacitor to which the high dielectric constant film is applied, an electrode must be formed of a platinum film (Pt film) having strong oxidation resistance on the upper and lower parts of the high dielectric constant film to exhibit the required excellent characteristics. In particular, in the case of using a platinum film as the lower electrode, the use of a diffusion barrier to suppress the reaction of platinum and silicon between the platinum film and the polysilicon plug to maintain the thermal stability of the lower electrode for charge storage. It is essential.

As a diffusion barrier of a next generation high dielectric constant capacitor in a semiconductor device, research on TiN, TiAlN, TiSiN, and the like has been conducted. Such a diffusion barrier is formed by a sputtering method. As the electrode, an element of a Pt, Ir or Ru system or a metal oxide is used, and these are also formed by a sputtering method.

TiN, which is used as a diffusion barrier, has a problem of being oxidized at a temperature of about 500 ° C. in a high dielectric film deposition process such as BST or a subsequent thermal process. In the case of Pt electrodes, oxygen diffuses through grain boundaries of Pt, and in the case of Ir and Ru, they themselves oxidize at temperatures of about 450 to 500 ° C. during BST deposition, This is because it oxidizes to the diffusion barrier.

Recently, three-phase nitride films such as TiAlN or TiSiN have been studied as diffusion barriers having oxidation resistance. Under the same conditions of using Pt as a lower electrode, the three-phase nitride film has improved oxidation characteristics compared to TiN, and has an advantage of being oxidized at a temperature of about 100 ° C. to 150 ° C. higher than TiN. Difficulties arise in the formation of ohmic contacts.

On the other hand, when Ir or Ru is used as the lower electrode, the lowering of the diffusion barrier layer can be suppressed to some extent, but the electrode itself is oxidized to IrO ₂ or RuO ₂ . IrO ₂ or RuO ₂ formed as described above is a serious problem that a highly conductive oxide material or a very rough oxide film having a roughness of several tens of nm is formed in the high dielectric / electrode interface, thereby deteriorating the insulation properties of the high dielectric by about 10 to 100 times. There is this.

Therefore, studies are actively underway to use Pt as an upper and lower electrode material to obtain excellent dielectric properties of Y1 series materials such as SBT (SrBi ₂ Ta ₂ O ₉ ) and high dielectric materials such as BST or Ta ₂ O ₅ . . As described above, the Pt film used as the electrode of the capacitor is formed by sputtering or metal organic chemical vapor deposition.

In order to obtain a larger capacitance in a given unit area in a capacitor structure having a stacked structure, a Pt film having a thickness of 3000 이상의 or more must be formed and an etching process is performed. Due to the characteristic of less reactive Pt, reactive gas Since the etching slope is only about 70 ° to 80 ° depending on the ion etching, there is a difficulty in the integration of high density devices. In addition, the step coverage of the Pt film is not good when forming the upper electrode, which leads to performance of the device and difficulties in subsequent processes.

Disclosure of Invention The present invention devised to solve the above problems can effectively prevent oxidation of the diffusion barrier under the capacitor lower electrode, and provide a method of manufacturing a capacitor capable of reducing the increase in the roughness of the lower electrode surface. have.

In addition, another object of the present invention is to provide a method for manufacturing a capacitor that can further improve the layer covering characteristic of the upper electrode.

1A to 1C are cross-sectional views of a capacitor manufacturing process according to an embodiment of the present invention;

2a to 2d are cross-sectional views of a capacitor manufacturing process according to another embodiment of the present invention.

* Description of reference numerals for the main parts of the drawings *

13, 23: polycrystalline silicon film 14, 24: TiSi ₂ layer

15, 25: diffusion barrier 16, 26: metal oxide film

17, 29A: Pt lower electrode 18, 30: dielectric film

19, 31: Pt upper electrode

The present invention for achieving the above object, a first step of forming a contact hole by selectively etching the interlayer insulating film formed on a semiconductor substrate; Forming a stacked structure including a plug, a diffusion barrier layer, and a metal oxide layer in the contact hole; Forming a lower electrode of the capacitor in contact with the metal oxide film; Forming a dielectric film on the lower electrode; And a fifth step of forming an upper electrode of the capacitor on the dielectric layer.

The present invention is characterized by laminating a diffusion barrier and a metal oxide between a plug for connecting the lower electrode to the semiconductor substrate and the lower electrode. In addition, there is another feature in forming the upper electrode by an electroplating method on the dielectric film on the lower electrode.

The metal oxide may prevent oxygen from diffusing into the diffusion barrier, and the diffusion barrier may prevent the formation of a silicon oxide layer at the interface between the plug and the metal oxide. In particular, by forming the diffusion barrier in the contact hole on the plug, it is possible to form a stable storage node contact in the thermal process of the subsequent oxidizing atmosphere by minimizing the contact area with oxygen or eliminating the possibility of contact with oxygen. In addition, when the lower electrode of the high dielectric constant capacitor is formed of a Pt film, there is an advantage that the leakage current can be reduced when forming the lower electrode using only metal oxides such as IrO ₂ or RuO ₂ furnace. In addition, when the upper electrode of the capacitor is formed of a Pt film by using an electroplating method, the layer covering characteristic may be improved.

Hereinafter, a capacitor manufacturing method according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1C are cross-sectional views of a capacitor manufacturing process according to an embodiment of the present invention.

First, as shown in FIG. 1A, an interlayer insulating film 11 having a thickness of 500 kV to 7000 kPa is formed on an insulator of boro-phospho-silicate glass (BPSG) or SiO ₂ type on the semiconductor substrate 10 on which a predetermined substructure is completed. ) And selectively etch the interlayer insulating film 11 to form a contact hole exposing the active region 12.

Subsequently, the doped polycrystalline silicon film having a thickness of 500 Å to 7000 에 was deposited on the entire structure and etched back so that the polycrystalline silicon film 13 having a thickness of 300 Å to 2000 Å remains inside the contact hole. A film (not shown) is deposited, a heat treatment process and a selective etching process are performed, that is, a TiSi ₂ layer 14 is formed on the polycrystalline silicon film 13 by self alignment. A portion of the polycrystalline silicon film 13 may be etched back before the Ti film deposition.

Next, the diffusion barrier 15 is formed on the entire structure. As the diffusion barrier 15, Ti _1-x Y _x N containing TiN or TiN is used. Y is Al or Si and x is a composition of the Y component.

When using Al as Y, _{x of} Ti _1-x Al _x N is in the range of 0.05 to 0.60, and is formed by nitrogen reactive sputtering using a TiAl _x target, or magnetron sputtering using a Ti _1-x Al _x N target. It is formed by the (magnetron sputtering) method.

When using Si as Y, _{x of} Ti _1-x Si _x N is in the range of 0.05 to 0.50, and is formed by nitrogen reactive sputtering using a TiSi _x target. Ti _1-x Si _x N may be formed by chemical vapor deposition using TiCl ₄ , SiH ₄ , N _2, and NH ₃ . As a source of Ti, tetrakis diethyl amino titanium (TDEAT) or tetrakis dimethyl amino titanium (TDMAT) is used. Further, Ti _1-x Si _x N was formed by low pressure chemical vapor deposition (LPCVD) with a wafer temperature of 550 ° C. to 850 ° C., or a wafer temperature of 300 ° C. to 650 ° C. and a plasma of 50 W to 10000 W. It may be formed by plasma enhanced chemical vapor deposition (PECVD) using a direct or remote plasma method at power, 10 MHz or 3 GHz frequency conditions.

Subsequently, a metal oxide film 16 such as IrO ₂ or RuO ₂ is formed on the diffusion barrier 15. IrO ₂ is formed by oxygen reactive sputtering using an Ir target, or by DC magnetron sputtering using an IrO ₂ target.

Next, as shown in FIG. 1B, the metal oxide layer 16 and the diffusion barrier layer 15 are etched back by chemical mechanical polishing or reactive ion etching to remove the interlayer dielectric layer 12. The metal oxide film 16, the diffusion barrier film 15 is left only on the plug in the contact hole made of the TiSi ₂ layer 14 and the polycrystalline silicon film 13.

Next, as shown in FIG. 1C, a Pt lower electrode 17 having a stack structure in contact with the metal oxide film 16 is formed, and a BST, 50 μs to 500 μs thick, is formed on the Pt lower electrode 17. A dielectric film 18 made of a Ta ₂ O _{5 having a} thickness of 500 kV to 500 kV or an SBT film having a thickness of 200 kV to 2000 kPa is formed, and the Pt upper electrode 19 is formed on the dielectric film 18 by sputtering.

In accordance with an embodiment of the present invention described above, the diffusion barrier layer is embedded in the contact hole, and a metal oxide layer is formed on the diffusion barrier layer to prevent diffusion of oxygen, thereby effectively inhibiting the oxidation of the diffusion barrier layer. In addition, the surface roughness of the lower electrode can be reduced by forming the lower electrode with a Pt film instead of a metal oxide.

A capacitor manufacturing process method according to another embodiment of the present invention will be described with reference to FIGS. 2A to 2D.

First, as shown in FIG. 2A, an interlayer insulating film 21 having a thickness of 500 Å to 7000 로 is formed on an insulator of BPSG or SiO ₂ type on the semiconductor substrate 20 on which a predetermined substructure is completed, and an interlayer insulating film ( 21 is selectively etched to form a contact hole exposing the active region 22.

Subsequently, the doped polycrystalline silicon film having a thickness of 500 m to 7000 m is deposited on the entire structure and etched back so that the polycrystalline silicon film 23 having a thickness of 300 m to 2000 m is left inside the contact hole, followed by a Ti film (not shown). The TiSi ₂ layer 24 having a thickness of 200 GPa to 1000 GPa is formed on the polycrystalline silicon film 23 by performing a heat treatment process and a selective etching process. The polycrystalline silicon film 23 may be etched back before the Ti film deposition.

Next, the diffusion barrier 25 is formed on the entire structure. As the diffusion barrier 25, Ti _1-x Y _x N containing TiN or TiN is used. Y is Al or Si and x is a composition of the Y component.

When using Al as Y, _{x of} Ti _1-x Al _x N is in the range of 0.05 to 0.60, and is formed by nitrogen reactive sputtering using a TiAl _x target or by a magnetron sputtering method using a Ti _1-x Al _x N target. do.

When using Si as Y, _{x of} Ti _1-x Si _x N is in the range of 0.05 to 0.50, and is formed by nitrogen reactive sputtering using a TiSi _x target. Ti _1-x Si _x N may be formed by chemical vapor deposition using TiCl ₄ , SiH ₄ , N _2, and NH ₃ .

Subsequently, a metal oxide film 26 such as IrO ₂ or RuO ₂ is formed on the diffusion barrier 25. IrO ₂ is formed by oxygen activated sputtering using an Ir target, or by direct current magnetron sputtering using an IrO ₂ target.

Next, the metal oxide film 26, the diffusion barrier film 25 and the Ti film are etched back by chemical mechanical polishing or reactive ion etching to expose the interlayer dielectric film 22, and the metal oxide film 26 and the diffusion barrier film 25 ) Remains only in the contact hole on the plug made of the TiSi ₂ layer 24 and the polycrystalline silicon film 23.

Next, as illustrated in FIG. 2B, a sacrificial layer 27 is formed of a BPSG or high density plasma-based SiO ₂ film on the entire structure, and the sacrificial layer 27 is selectively etched to form the polycrystal. A trench type opening 28 exposing a contact hole in which the silicon film 23, the TiSi ₂ layer 24, the diffusion barrier film 25, and the metal oxide film 26 are stacked is formed.

Next, as shown in Fig. 2C, a first Pt film 29 having a thickness of 50 mV to 1000 mV to form a lower electrode of the capacitor is formed on the entire structure by the sputtering method. The first Pt layer 29 may be formed by chemical vapor deposition, or an additional Pt layer may be further formed on the first Pt layer 29 by electroplating.

A metal oxide film such as an IrO ₂ film may be additionally formed after the above-described chemical mechanical polishing process or etch back process and before deposition of the first Pt film. At this time, the thickness of the IrO ₂ film is 50 kPa to 2000 kPa.

Next, an oxide film or a photosensitive film (not shown) is filled in the opening 28, and the first Pt film 29 is chemically mechanically polished until the sacrificial film 27 is exposed to form the Pt lower electrode 29A. Then, the oxide film or the photoresist film and the sacrificial film 27 are removed to expose the Pt lower electrode 29A as shown in FIG. 2D, and the BST, 50 Å to 500 Å thickness BST, 50 상 에 on the Pt lower electrode 29A is shown. A dielectric film 30 formed of a Ta ₂ O _{5 having a} thickness of 500 kV to 500 kV or an SBT film having a thickness of 200 kV to 2000 kPa, and formed on the dielectric film 30 by a sputtering method or a physical vapor deposition method. A Pt upper electrode 31 composed of a second Pt film having a thickness and a third Pt film having a thickness of 100 kV to 2500 kV formed by an electroplating method is formed thereon. The second Pt film may be formed by chemical vapor deposition.

The third Pt film contains 10 g / l Pt (NH ₂ ) ₂ (NO ₂ ) ₂ (dinitrodiamino Pt), 100 g / l NH ₄ NO ₃ (ammonium nitrate), 10 g / l NaNO ₃ as a Pt source. (sodium nitrate), 44 g / L NH ₃ (ammonia) mixed solution while maintaining a temperature of 80 ℃ to 110 ℃ 6 A / dm ² to 8 A / dm ² to supply a current, the current efficiency ( The current efficiency is 10%, and a voltage of 2 V to 4 V is applied to glass or rubber lined and the solution is maintained by adding platinum slat.

Another embodiment of the present invention made as described above can prevent the difficulty of etching due to the process of making the Pt film to a high step by forming the capacitor of the cylinder structure using the opening of the trench form instead of the stack structure.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

The present invention made as described above can form a stable storage node contact (storage node contact) in a high temperature oxidation resistant atmosphere to form a high-k dielectric film, such as Ta ₂ O ₅ , BST or Y1 required during the high temperature subsequent thermal process, layer covering characteristics By forming a Pt film by this excellent electrical conductivity method and solving the Pt etching problem, there is an effect that early development of a high-speed device having a high density can be achieved.

Claims (7)

In the capacitor manufacturing method, Forming a contact hole by selectively etching the interlayer insulating film formed on the semiconductor substrate; Forming a stacked structure including a plug, a diffusion barrier layer, and a metal oxide layer in the contact hole; Forming a lower electrode of the capacitor in contact with the metal oxide film; Forming a dielectric film on the lower electrode; And A fifth step of forming an upper electrode of a capacitor on the dielectric layer Capacitor manufacturing method comprising a. The method of claim 1, The second step, Forming the plug in a stack structure of a polycrystalline silicon film and a silicide layer in the contact hole; Forming the diffusion barrier layer on the plug with TiN, TiAlN or TiSiN; And Forming the metal oxide layer on the diffusion barrier layer by IrO ₂ or RuO ₂ Capacitor manufacturing method comprising a. The method of claim 2, Each of the lower electrode and the upper electrode is formed of a Pt film The dielectric film is formed of any one of (Ba, Sr) TiO ₃ , Ta ₂ O ₅ film or SrBi ₂ Ta ₂ O ₉ film. The method of claim 3, wherein In the third step, A capacitor manufacturing method, comprising forming a lower electrode of a cylinder structure. The method of claim 4, wherein The fifth step, Forming a first Pt layer on the dielectric layer to form the upper electrode by physical vapor deposition; And And forming a second Pt film on the first upper electrode Pt film by an electroplating method. The method of claim 4, wherein The third step, Forming a third Pt film to form the lower electrode by physical vapor deposition; And And forming a fourth Pt film on the third Pt film by an electroplating method. The method according to claim 5 or 6, The first Pt film or the third Pt film is formed by a chemical vapor deposition method, characterized in that the capacitor manufacturing method.