KR20000076648A - 공유 메모리 - Google Patents
공유 메모리 Download PDFInfo
- Publication number
- KR20000076648A KR20000076648A KR1020000006532A KR20000006532A KR20000076648A KR 20000076648 A KR20000076648 A KR 20000076648A KR 1020000006532 A KR1020000006532 A KR 1020000006532A KR 20000006532 A KR20000006532 A KR 20000006532A KR 20000076648 A KR20000076648 A KR 20000076648A
- Authority
- KR
- South Korea
- Prior art keywords
- memory
- shared memory
- copy
- bus
- port
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1663—Access to shared memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Software Systems (AREA)
- Static Random-Access Memory (AREA)
- Dram (AREA)
- Multi Processors (AREA)
- Memory System (AREA)
Abstract
Description
Claims (5)
- 각각이 복사버스 기능을 가지는 적어도 하나의 포트와 사용자 측에서 엑세스할 수 있는 적어도 하나의 포트를 갖는 복수개의 다중포트 메모리; 및상기 복사버스 기능을 갖는 적어도 하나의 포트에 연결되는 적어도 하나의 복사버스를 구비하며,특히 적응적으로 바뀌어서 상기 사용자 측의 쓰기 동작에 의해 변화된 상기 다중포트 메모리들 중 어느 하나의 저장내용을 적어도 하나의 복사버스를 통해 다른 다중포트 메모리로 복사하도록 구성된 것을 특징으로 하는 공유메모리.
- 제 1항에 있어서, 상기 저장내용은 광학적으로 복사되도록 변형되는 것을 특징으로 하는 공유메모리.
- 제 1항 또는 제 2항에 있어서, 상기 공유메모리는 집적회로기술에 의해 형성되는 것을 특징으로 하는 공유메모리.
- 제 3항에 있어서, 상기 집적회로기술은 2차원 집적회로기술인 것을 특징으로 하는 공유메모리.
- 제 3항에 있어서, 상기 집적회로기술은 3차원 집적회로기술인 것을 특징으로 하는 공유메모리.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11033753A JP2000231546A (ja) | 1999-02-12 | 1999-02-12 | 共有メモリ |
JP?11-33,753 | 1999-02-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20000076648A true KR20000076648A (ko) | 2000-12-26 |
KR100350525B1 KR100350525B1 (ko) | 2002-08-28 |
Family
ID=12395197
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020000006532A KR100350525B1 (ko) | 1999-02-12 | 2000-02-11 | 공유 메모리 |
Country Status (6)
Country | Link |
---|---|
US (1) | US6874068B1 (ko) |
EP (1) | EP1033722B1 (ko) |
JP (1) | JP2000231546A (ko) |
KR (1) | KR100350525B1 (ko) |
DE (1) | DE60007010T2 (ko) |
TW (1) | TW436868B (ko) |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS613450A (ja) | 1984-06-18 | 1986-01-09 | Hiroshima Daigaku | 三次元光結合共有メモリ集積装置 |
US5590349A (en) * | 1988-07-11 | 1996-12-31 | Logic Devices, Inc. | Real time programmable signal processor architecture |
JPH03100991A (ja) | 1989-09-14 | 1991-04-25 | Hitachi Ltd | 共有メモリ |
GB9008366D0 (en) * | 1990-04-12 | 1990-06-13 | British Aerospace | Data interaction architecture(dia)for real time embedded multi processor systems |
WO1992002885A1 (en) * | 1990-08-06 | 1992-02-20 | Epic Industries Incorporated | Processing element for a multi-processor digital computing system |
DE69227956T2 (de) * | 1991-07-18 | 1999-06-10 | Tandem Computers Inc., Cupertino, Calif. | Multiprozessorsystem mit gespiegeltem Speicher |
JPH05282869A (ja) | 1992-03-31 | 1993-10-29 | Nec Corp | 半導体記憶装置 |
US6021472A (en) * | 1995-08-21 | 2000-02-01 | Canon Kabushiki Kaisha | Information processing device and control method thereof |
US6223260B1 (en) * | 1996-01-25 | 2001-04-24 | Unisys Corporation | Multi-bus data processing system in which all data words in high level cache memories have any one of four states and all data words in low level cache memories have any one of three states |
US5802561A (en) * | 1996-06-28 | 1998-09-01 | Digital Equipment Corporation | Simultaneous, mirror write cache |
US6170046B1 (en) * | 1997-10-28 | 2001-01-02 | Mmc Networks, Inc. | Accessing a memory system via a data or address bus that provides access to more than one part |
US6480927B1 (en) * | 1997-12-31 | 2002-11-12 | Unisys Corporation | High-performance modular memory system with crossbar connections |
US6148375A (en) * | 1998-02-13 | 2000-11-14 | International Business Machines Corporation | Hierarchical bus simple COMA architecture for shared memory multiprocessors having a bus directly interconnecting caches between nodes |
US6321298B1 (en) * | 1999-01-25 | 2001-11-20 | International Business Machines Corporation | Full cache coherency across multiple raid controllers |
US6434674B1 (en) * | 2000-04-04 | 2002-08-13 | Advanced Digital Information Corporation | Multiport memory architecture with direct data flow |
-
1999
- 1999-02-12 JP JP11033753A patent/JP2000231546A/ja active Pending
-
2000
- 2000-02-03 TW TW089101956A patent/TW436868B/zh not_active IP Right Cessation
- 2000-02-07 EP EP00102565A patent/EP1033722B1/en not_active Expired - Lifetime
- 2000-02-07 DE DE60007010T patent/DE60007010T2/de not_active Expired - Lifetime
- 2000-02-08 US US09/500,254 patent/US6874068B1/en not_active Expired - Lifetime
- 2000-02-11 KR KR1020000006532A patent/KR100350525B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
EP1033722A3 (en) | 2001-05-23 |
DE60007010D1 (de) | 2004-01-22 |
KR100350525B1 (ko) | 2002-08-28 |
DE60007010T2 (de) | 2004-09-09 |
EP1033722A2 (en) | 2000-09-06 |
TW436868B (en) | 2001-05-28 |
US6874068B1 (en) | 2005-03-29 |
EP1033722B1 (en) | 2003-12-10 |
JP2000231546A (ja) | 2000-08-22 |
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