KR20000075307A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
KR20000075307A
KR20000075307A KR1019990019828A KR19990019828A KR20000075307A KR 20000075307 A KR20000075307 A KR 20000075307A KR 1019990019828 A KR1019990019828 A KR 1019990019828A KR 19990019828 A KR19990019828 A KR 19990019828A KR 20000075307 A KR20000075307 A KR 20000075307A
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KR
South Korea
Prior art keywords
insulating film
semiconductor device
photoresist
forming
film
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KR1019990019828A
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Korean (ko)
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유춘근
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김영환
현대전자산업 주식회사
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Priority to KR1019990019828A priority Critical patent/KR20000075307A/en
Publication of KR20000075307A publication Critical patent/KR20000075307A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/42—Stripping or agents therefor
    • G03F7/427—Stripping or agents therefor using plasma means only

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to guarantee a processing margin and to make a highly integrated device, by forming an insulating layer of a uniform thickness along a step difference of a lower pattern at a low temperature. CONSTITUTION: An insulating layer is formed along a step difference of a structure. A photoresist layer is formed on the entire surface of the resultant structure. The photoresist layer is hardened, and is partially eliminated to expose the surface of the insulating layer. The exposed insulating layer is etched. The remaining photoresist layer is eliminated.

Description

반도체소자 제조방법{Method for fabricating semiconductor device}Method for fabricating semiconductor device

본 발명은 반도체소자 제조방법에 관한 것으로, 특히 층덮힘이 좋지 않은 박막으로 패턴의 표면 단차를 따라 상기 박막을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming the thin film along a surface step of a pattern with a thin film having a poor layer covering.

잘 알려진 바와 같이, 화학기상증착(CVD : Chemical Vapor Deposition)이란 특정의 반응기체들을 반응용기 속에 계속 투입하면서 적절한 조건을 유지시켜 주므로써 고체상의 물질이 생성되면서 가공하고자 하는 물체(웨이퍼) 위에 내려 쌓이게(증착)되는 현상을 이용하는 공정으로서, 이때의 증착반응은 일반적으로 기판에 유지되는 온도 및 그에 따른 열적에너지에 의하여 진행되나, 때로는 전기장에 의한 플라즈마(PECVD : Plasma Enhanced Chemical Vapor Deposition) 또는 자외선에 의한 빛 에너지(PVD) 등의 상승작용에 의하여 촉진되기도 한다.As is well known, Chemical Vapor Deposition (CVD) is a process in which certain reactors are continuously introduced into a reaction vessel to maintain appropriate conditions, thereby producing solid materials that are deposited on the object to be processed (wafer). In this process, the deposition reaction is generally carried out by the temperature maintained on the substrate and the thermal energy thereof, but sometimes by plasma (PECVD: Plasma Enhanced Chemical Vapor Deposition) or ultraviolet rays. It may be promoted by synergy such as light energy (PVD).

그리고, PECVD(Plasma Enhanced Chemical Vapor Deposition) 방법으로 박막을 증착할 경우, 웨이퍼의 전면만 증착이 가능하고 저온에서 박막의 형성이 가능하기 때문에 공정마진이 향상되는 장점이 있으나, 층덮힘이 나쁘기 때문에 PECVD 증착에 의한 절연막을 층간절연막으로 적용할 경우 보이드(Void)가 발생된다. 도1a 내지 도1c는 PECVD 방법으로 층간절연막(1)이 증착되는 과정과 증착 후 패턴(2) 간의 간극에서 보이드가 발생되는 것을 도시하고 있다.In addition, when the thin film is deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition) method, it is possible to deposit only the entire surface of the wafer and to form the thin film at low temperature, thereby improving the process margin. When the insulating film by deposition is applied as an interlayer insulating film, voids are generated. 1A to 1C show a process of depositing the interlayer insulating film 1 by PECVD and generating voids in the gap between the pattern 2 after the deposition.

또한, LPCVD(Low Pressure Chemical Vapor Deposition) 방법은 층덮힘이 우수하나 고온에서 공정이 이루어지기 때문에 공정 마진이 좋지 않은 것이 단점이다.In addition, LPCVD (Low Pressure Chemical Vapor Deposition) method is excellent in layer covering, but the process margin is not good because the process is performed at a high temperature.

한편, 반도체소자를 제조함에 있어, 특히 고집적 메모리소자를 제조함에 있어, 패턴의 단차를 따라 균일한 두께로 산화막, 질화막, 질산화막 등의 박막을 형성하여야 하는 경우가 발생되는데, 현재에는 도2a에 도시된 것과 같이 고온의 층덮힘성이 좋은 LPCVD 절연막(1)을 사용하고 있다.On the other hand, in the manufacture of semiconductor devices, particularly in the manufacture of highly integrated memory devices, there is a case where a thin film of an oxide film, a nitride film, or an oxynitride film has to be formed with a uniform thickness along a step of a pattern. As shown in the drawing, an LPCVD insulating film 1 having a high temperature layer covering property is used.

그러나, 앞으로 더 발전하게 될 차세대의 고집적 소자에는 증착온도가 낮고, 웨이퍼의 전면만 증착이 가능하고, 또한 폭넓은 공정마진이 있는 PECVD 절연막이 적용될 필요가 있다.However, in the next generation of highly integrated devices to be further developed in the future, it is necessary to apply a PECVD insulating film having a low deposition temperature, capable of depositing only the entire surface of the wafer, and having a wide process margin.

그런데, 앞서 설명한 바와같이 PECVD 절연막은 층덮힘이 나쁘기 때문에 패턴(2)의 측벽에서 충분한 두께를 얻기 위해서는 패턴의 상단부로 필요 이상의 두꺼운 박막이 증착되어 단차가 높아지는 문제점을 가져오게 되며, 아울러, 패턴(2) 사이 갭(Gap)이 더욱 좁아져서 후속의 산화물 박막으로 상기 갭(Gap)을 채우기 힘들어지는 문제점이 발생되게 된다.However, as described above, since the PECVD insulating layer has a bad layer covering, a thick film more than necessary is deposited on the upper end of the pattern in order to obtain a sufficient thickness on the sidewall of the pattern 2, resulting in a step difference. 2) The gap between the gaps (gap) is further narrowed to cause a problem that it is difficult to fill the gap (gap) with a subsequent oxide thin film.

본 발명은 상술한 바와 같은 종래기술의 문제점을 해결하기 위하여 안출된 것으로써, 하부 패턴의 단차를 따라 균일한 두께로 절연막을 형성하되 저온에서 공정이 가능하여 원하는 고집적소자를 얻을 수 있도록 하여주는 반도체소자 제조방법을 제공하는데 그 목적이 있다.The present invention has been made in order to solve the problems of the prior art as described above, while forming an insulating film with a uniform thickness along the step difference of the lower pattern, the semiconductor can be processed at a low temperature to obtain a desired high integration device Its purpose is to provide a device manufacturing method.

도1a 내지 도1c는 PECVD 절연막에 의한 보이드 형성 과정을 보여주는 공정 단면도,1A to 1C are cross-sectional views illustrating a process of forming a void by a PECVD insulating film;

도2a는 LPCVD 방법을 사용하여 패턴의 단차를 따라 균일한 두께로 박막을 형성한 상태를 도시한 단면도,2A is a cross-sectional view showing a state in which a thin film is formed with a uniform thickness along a step of a pattern using the LPCVD method;

도2b는 PECVD 방법을 사용하여 패턴의 단차를 따라 박막을 형성한 상태를 도시한 단면도,2B is a cross-sectional view showing a state in which a thin film is formed along a step of a pattern using a PECVD method;

도3a 내지 도3f는 본 발명의 방법에 따른 일실시예로서, PECVD 방법을 사용하여 게이트의 스페이서 보호막을 형성하는 방법을 설명하기 위한 공정 단면도.3A to 3F are cross-sectional views for explaining a method of forming a spacer protective film of a gate using a PECVD method as an embodiment according to the method of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 층간절연막 2 : 패턴1: interlayer insulating film 2: pattern

상기 목적을 달성하기 위한 본 발명은, 소정의 단차를 갖는 구조물 상에 상기 구조물의 단차를 따라 균일한 두께로 절연막을 형성하기 위한 반도체소자 제조방법에 있어서, 상기 구조물의 단차를 따라 절연막을 형성하는 제1단계; 상기 제1단계가 완료된 결과물 전체구조 상부에 감광제를 형성하는 제2단계; 상기 감광제를 경화하고, 상기 절연막의 표면이 드러나도록 상기 감광제를 에치백하는 제3단계; 상기 드러난 절연막을 식각하는 제4단계; 및 상기 에치백후 잔류하는 감광제를 제거하는 제5단계를 포함하여 이루어짐을 특징으로 한다.The present invention for achieving the above object, in the semiconductor device manufacturing method for forming an insulating film with a uniform thickness along the step of the structure on a structure having a predetermined step, forming an insulating film along the step of the structure First step; A second step of forming a photoresist on the entire structure of the resultant product in which the first step is completed; Hardening the photoresist and etching back the photoresist to expose the surface of the insulating film; A fourth step of etching the exposed insulating film; And a fifth step of removing the photosensitive agent remaining after the etch back.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

도3a 내지 도3f는 본 발명의 일실시예에 따른 PECVD 방법을 사용한 게이트 스페이서 보호막 형성 공정을 도시한 공정도이다.3A to 3F are flowcharts illustrating a process of forming a gate spacer protective film using a PECVD method according to an exemplary embodiment of the present invention.

먼저 도3a에 도시된 바와 같이,　소정의 공정을 마친 반도체 기판 상에 전도라인 등의 패턴(2)을 형성한다. 그리고, 상기 패턴(2)이 형성된 결과물 상에 PECVD 방법을 사용하여 측벽의 프로파일이 수직이 되도록 예컨대 질화막 또는 질산화막(SiON)과 같은 절연막(1)을 증착시킨다.First, as shown in FIG. 3A, a pattern 2, such as a conductive line, is formed on a semiconductor substrate after a predetermined process has been completed. Then, an insulating film 1 such as, for example, a nitride film or a nitride oxide film (SiON) is deposited on the resulting product on which the pattern 2 is formed by using a PECVD method.

PECVD 절연막은 층덮힘성이 좋지 않기 때문에 너무 얇은 두께로 증착할 경우에는 패턴(2)의 측벽 및 저부에 거의 증착되지 않을 수 있고, 또한 너무 두껍게 증착할 경우에는 도1b와 같이 패턴(2)의 모서리 부분이 불록해지기 때문에 측벽의 프로파일이 수직이될 때까지만 증착을 수행한다. 한편, 이때 도면에 도시된 바와같이 패턴(2)의 상단부에서는 PECVD 박막(1)이 측벽보다 상대적으로 두껍워지게 된다.Since the PECVD insulating film is poor in layer coverage, it may be hardly deposited on the sidewalls and the bottom of the pattern 2 when deposited with a too thin thickness. Since the part is lumped, deposition is only performed until the sidewall profile is vertical. Meanwhile, as shown in the figure, the PECVD thin film 1 becomes relatively thicker than the sidewall at the upper end of the pattern 2.

다음으로 도3b에 도시된 바와 같이 결과물 전체구조 상부에 충분한 평탄도를 가질 정도의 두께의 감광제(3)를 코팅한 후 감광제가 코팅된 웨이퍼를 열처리하여 감광제 내부의 용매를 증발시켜 경화시킨다.Next, as shown in FIG. 3B, the photoresist 3 having a thickness sufficient to have sufficient flatness is coated on the entire structure of the resultant, and then the photoresist-coated wafer is heat treated to evaporate and cure the solvent inside the photoresist.

다음으로 도3c에 도시된 바와 같이 패턴(2) 측벽부의 절연막은 덮되 패턴(2)의 상단부의 절연막은 드러나도록 부분적으로 감광제를 에치백한다. 이때, 감광제의 에치백은 산소 플라즈마 식각법을 사용한다.Next, as shown in FIG. 3C, the photoresist is partially etched back so that the insulating film of the side wall portion of the pattern 2 is covered but the insulating film of the upper end of the pattern 2 is exposed. At this time, the etch back of the photosensitive agent uses an oxygen plasma etching method.

이어서, 도3d에 도시된 바와 같이 상기 감광제 제거 후에 드러난 박막의 일부를 식각한다. 식각은 건식또는 습식 모두 가능하다. 또한, 경우에 따라서는 상기 드러난 박막 모두를 제거할 수도 있다.Subsequently, as shown in FIG. 3D, a portion of the thin film exposed after removing the photoresist is etched. Etching can be either dry or wet. In some cases, all of the exposed thin films may be removed.

다음으로 도3e에 도시된 바와 같이 잔류한 감광제(3)를 산소 플라즈마 식각과 후속세정 공정을 통해서 제거한다.Next, as shown in FIG. 3E, the remaining photosensitive agent 3 is removed through oxygen plasma etching and subsequent cleaning processes.

이어서, 도3f와 같이 측벽 층덮힘 두께를 높이기 위해서 다시 PECVD 방법을 사용하여 절연막(4)을 증착한다. 절연막(4)을 다시 증착하는 과정은 경우에 따라서 그 생략이 가능하며, 필요한 경우, 즉 원하는 측벽 두께의 박막을 얻기 위해서는 상기와 같은 도3a 내지 도3f에서 도시된 공정을 반복 진행할 수 있다.Subsequently, the insulating film 4 is deposited again using PECVD to increase the sidewall layer covering thickness as shown in FIG. 3F. The process of re-depositing the insulating film 4 may be omitted in some cases, and if necessary, that is, in order to obtain a thin film having a desired sidewall thickness, the process illustrated in FIGS. 3A to 3F may be repeated.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 바와 같은 본 발명은 층덮힘이 우수하지 못한 방법으로 박막을 형성하면서 하부 패턴의 단차를 따라 박막을 형성할 필요가 있을때, 모두 적용가능하며, 특히 저온 공정이 가능한 LPCVD 방법으로 게이트 스페이서 보호막을 형성가능하여 공정 마진 확보 및 원하는 고집적소자의 개발을 앞당길 수 있는 효과가 있다.As described above, the present invention is applicable when the thin film is formed along the step pattern of the lower pattern while the thin film is formed by a method in which the layer covering is not excellent. Particularly, the gate spacer protective film may be formed by an LPCVD method that enables a low temperature process. Formability is effective in securing process margins and speeding up development of desired integrated devices.

Claims (4)

소정의 단차를 갖는 구조물 상에 상기 구조물의 단차를 따라 균일한 두께로 절연막을 형성하기 위한 반도체소자 제조방법에 있어서,In the semiconductor device manufacturing method for forming an insulating film with a uniform thickness along the step of the structure on a structure having a predetermined step, 상기 구조물의 단차를 따라 절연막을 형성하는 제1단계;A first step of forming an insulating film along a step of the structure; 상기 제1단계가 완료된 결과물 전체구조 상부에 감광제를 형성하는 제2단계;A second step of forming a photoresist on the entire structure of the resultant product in which the first step is completed; 상기 감광제를 경화하고, 상기 절연막의 표면이 드러나도록 부분적으로 상기 감광제를 제거하는 제3단계;Hardening the photoresist and partially removing the photoresist to expose the surface of the insulating film; 상기 드러난 절연막을 식각하는 제4단계; 및A fourth step of etching the exposed insulating film; And 잔류하는 감광제를 제거하는 제5단계5th step of removing residual photoresist 를 포함하여 이루어지는 반도체소자 제조방법.A semiconductor device manufacturing method comprising a. 제1항에 있어서,The method of claim 1, 상기 감광제의 제거는 산소 플라즈마 식각법을 사용하는 것을 특징으로 하는 반도체소자 제조방법.The removal of the photosensitive agent is a semiconductor device manufacturing method, characterized in that using the oxygen plasma etching method. 제1항에 있어서,The method of claim 1, 상기 절연막은 PECVD 방법에 의한 질화막 또는 질산화막임을 특징으로 하는 반도체소자 제조방법.The insulating film is a semiconductor device manufacturing method characterized in that the nitride film or nitride oxide film by the PECVD method. 제1항 내지 제3항중 어느한 항에 있어서,The method according to any one of claims 1 to 3, 상기 제5단계후 그 결과물의 단차를 따라 두번째 절연막을 형성하는 단계를 더 포함하여 이루어진 반도체소자 제조방법.And forming a second insulating film along the resulting step after the fifth step.
KR1019990019828A 1999-05-31 1999-05-31 Method for fabricating semiconductor device KR20000075307A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100436288B1 (en) * 2002-07-11 2004-06-16 주식회사 하이닉스반도체 Method of manufacturing a capacitor in a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100436288B1 (en) * 2002-07-11 2004-06-16 주식회사 하이닉스반도체 Method of manufacturing a capacitor in a semiconductor device

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