KR20000061167A - a liquid crystal display having data redundancy lines and a manufacturing method thereof - Google Patents

Abstract

PURPOSE: A liquid crystal display device is provided to prevent a transparent conductive connection pattern of a thin film transistor substrate from being shorted with a transparent electrode of an upper substrate. CONSTITUTION: A liquid crystal display device comprises upper and lower gate lines(110,120) which are formed on an insulation substrate(10) in parallel and in a horizontal direction. Left and right connection parts(130,140) are formed in a vertical direction so as to connect the upper and lower gate lines(110,120). An auxiliary line(150) is formed between the connection parts(130,140) of an adjacent pixel and in the vertical direction on the insulation substrate(10), and is not connected to the upper and lower gate lines(110,120). A gate insulation film(20) is covered over a ring gate wire(110,120,130,140) and the auxiliary line(150), and a semiconductor layer(200) is formed over an upper gate line(110). A data line(300) is formed on the gate insulation film(20) so as to be intersected with the gate lines(110,120) in the vertical direction, and is overlapped with the auxiliary line(150). A conductive connection pattern(410) is formed extending two pixels so as to be intersected with a lower gate line of one pixel and with an upper gate line(110) of an adjacent pixel.

Description

Liquid crystal display having a data auxiliary line and a method of manufacturing the same {a liquid crystal display having data redundancy lines and a manufacturing method}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a manufacturing method thereof, and more particularly, to a liquid crystal display device having a data auxiliary line and a manufacturing method thereof.

In general, a liquid crystal display device has a structure in which a liquid crystal is injected between two substrates of a thin film transistor substrate and a color filter substrate, and an amount of light transmission is controlled by adjusting an intensity of an electric field applied thereto.

The thin film transistor substrate of the liquid crystal display device includes a pixel region defined by a plurality of gate lines through which scan signals are transmitted, a plurality of data lines through which image signals are transmitted, and intersecting the gate lines, and portions where the gate lines and data lines intersect, and formed therein. And a thin film transistor and a pixel electrode.

On the other hand, R, G, and B color filters are alternately formed on the color filter substrate corresponding to the thin film transistor substrate, a light shielding film is formed between the color filters, and a transparent electrode is formed entirely on the light shielding film and the color filter. have.

In the twisted nematic method, in which a liquid crystal having a positive dielectric constant is injected between the thin film transistor substrate and the color filter substrate and the major axis of the liquid crystal is oriented parallel to the substrate surface, the liquid crystal is not applied when a voltage is not applied. The liquid crystal is operated in such a way that the upper and lower substrates are twisted continuously by 90 degrees, and when a voltage is applied, the long axis of the liquid crystal is arranged perpendicular to the substrate.

On the other hand, in the vertical alignment method in which a liquid crystal having a negative dielectric constant is injected between the thin film transistor substrate and the color filter substrate and the initial orientation is perpendicular to the substrate surface, the liquid crystal is perpendicular to the substrate surface in the state where no voltage is applied. When the voltage is applied and the liquid crystal is arranged in parallel with the substrate, the liquid crystal operates. In the case of the vertical alignment method, a linear opening is formed in the transparent electrode of the upper color filter substrate to induce the liquid crystal to operate in a predetermined direction by using a fringe field formed between the opening and the pixel electrode pattern. .

The wiring and electrode structures of the upper and lower substrates of the twisted nematic or vertical alignment type liquid crystal display device are formed by stacking and patterning thin films one by one, and the films may be partially broken at the overlapping portions of the plurality of films. In particular, defects such as disconnection of data lines frequently occur at portions where the gate lines and the data lines cross each other in the thin film transistor substrate.

Conventionally, data line defects are duplicated by duplexing the data lines only at the intersections of the gate lines and the data lines, or by forming additional auxiliary lines by depositing and patterning a separate metal on or under the data line pattern to duplicate the data lines. Reduced.

In the case of the first method, if the data line is disconnected except at the intersection of the gate line and the data line, it should be repaired by using a separate repair line. In addition, a laser bonding process is required in this repair process, and it is difficult to apply it to a high-definition display device.

In the second method, a separate metal must be deposited and patterned to form an auxiliary line, and an insulating layer etching process for connecting the auxiliary line and the data line has to be added.

An object of the present invention is to manufacture an auxiliary line structure capable of reducing data line disconnection defects without adding a process.

Another object of the present invention is to prevent the transparent conductive connection pattern of the thin film transistor substrate from being electrically shorted with the transparent electrode of the upper facing substrate.

Another object of the present invention is to prevent the auxiliary line and the gate wiring from being shorted.

1 is a wiring diagram of a thin film transistor substrate of a twisted nematic liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II-II 'of FIG. 1;

3 is a cross-sectional view taken along line III-III ′ of FIG. 1;

FIG. 4 is a cross-sectional view taken along line II-II ′ of FIG. 1 and is a cross-sectional view of a liquid crystal display in a state in which a color filter substrate corresponds to a thin film transistor substrate.

5 is a wiring diagram of a vertical alignment liquid crystal display according to a second exemplary embodiment of the present invention.

6 is a cross-sectional view taken along line VI-VI 'of FIG. 5,

FIG. 7 is a cross-sectional view taken along the line VII-VII ′ of FIG. 5;

8A to 8F are plan views illustrating a method of manufacturing a liquid crystal display according to a second embodiment of the present invention, in the order of a process.

In order to solve this problem, the thin film transistor substrate side of the liquid crystal display according to the present invention forms a plurality of auxiliary lines separated in pixel units under the data line on the same layer as the gate line and one gate line on the data line. After forming a transparent conductive connection pattern connecting the ends of the auxiliary lines positioned on both sides as a reference, the color filter substrate including the transparent electrode having an opening formed in a portion to correspond to the transparent conductive connection pattern faces the thin film transistor substrate. Let's do it.

In the liquid crystal display according to the exemplary embodiment of the present invention, a plurality of gate lines are formed in a horizontal direction on an insulating substrate for a thin film transistor substrate, and an auxiliary line is formed in a vertical direction between two adjacent gate lines. The gate line and the auxiliary line are covered by the gate insulating film, and a semiconductor layer is formed on a part of the gate insulating film above the gate line. In addition, data lines such as a plurality of data lines crossing the gate line and overlapping the auxiliary line, a source electrode extending from the data line and overlapping the edge of the semiconductor layer, and a drain electrode overlapping the edge of the semiconductor layer on the opposite side of the source electrode, It is formed on the gate insulating film. The semiconductor layer and the data wiring are covered by a protective insulating film. The semiconductor insulating film and the data wiring are located in the pixel area surrounded by the gate line and the data line on the protective insulating film, and electrically connect the pixel electrode connected to the drain electrode and the auxiliary lines located on both sides of the gate line. A conductive connection pattern is formed. The insulating substrate for the color filter substrate corresponds to the insulating substrate for the thin film transistor substrate, and the first opening pattern and the second opening pattern are formed in the portion facing the pixel region and the portion facing the conductive connection pattern, respectively. It includes a transparent electrode,

In this case, the conductive connection pattern is preferably electrically connected to the data line, and may be simultaneously connected to the auxiliary line and the data line located on both sides of the gate line through a contact hole formed in the protective insulating film and the gate insulating film. In order to facilitate such a connection, an end portion of the auxiliary line may be deviated by an angle from the data line. In addition, the conductive connection pattern is preferably formed of ITO which is the same material as the pixel electrode.

It is preferable that the width of the second opening pattern is formed to be wider than the width of the conductive connection pattern, and it is appropriate that the edge of the conductive connection pattern and the edge of the second opening pattern have an interval of 3 μm to 6 μm.

In addition, an auxiliary gate line may be formed between two adjacent gate lines to be parallel to the gate line, and a connecting portion connecting the gate line and the auxiliary gate line in the vertical direction may be formed in the pixel area. In this case, the auxiliary line may be formed of the same material as the gate line, the auxiliary gate line, and the connecting portion, and in this case, the distance between the connecting portion and the auxiliary line is preferably about 4 μm to about 7 μm.

A light blocking film may be disposed below the transparent electrode to surround the outside of the pixel area, and the light blocking film may be an organic insulating film or a metal film. When the light shielding film is formed of a metal film, it is preferable to further include a protective film covering the light shielding film.

The pixel electrode may be formed in a shape in which a plurality of square portions are connected in a vertical direction. In this case, the first opening pattern may be formed in a cross shape corresponding to each of the first opening patterns.

In the method of manufacturing a liquid crystal display according to an exemplary embodiment of the present invention, data auxiliary lines positioned between a plurality of gate lines and two adjacent gate lines are simultaneously formed on a first substrate for a thin film transistor substrate, and a gate insulating layer is stacked thereon. Then, a data line is formed. Subsequently, a protective insulating film covering the data line is stacked, and the protective insulating film and the gate insulating film are patterned to form a plurality of contact holes exposing the data auxiliary line and contact holes exposing the data line. Next, a connection pattern for connecting the data auxiliary line and the data line positioned on both sides of the gate line with the pixel electrode and the contact hole is formed. A transparent conductive film is deposited on the second substrate for the color filter substrate, and the transparent conductive film is patterned to form a first opening pattern, and then the first substrate and the second substrate correspond to each other so that the first opening pattern faces the connection pattern. Let's do it.

In the forming of the gate line and the data auxiliary line, it is possible to form an auxiliary gate line parallel to the gate line between two adjacent gate lines, and to form a gate connection part connecting the auxiliary gate line and the gate line to each other.

Next, the liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

1 is a wiring diagram of a thin film transistor substrate of a twisted nematic liquid crystal display device according to a first embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views taken along lines II-II 'and III-III' of FIG. The auxiliary line is a gate wiring metal, which is formed under the data line to the intersection of the data line and the gate line, and is connected to the ITO at the intersection of the data line and the gate line.

1 to 3, upper and lower gate lines 110 and 120 parallel to each other are formed on the insulating substrate 10 in a horizontal direction, and the upper and lower gate lines 110 and 120 are connected to each other. Left and right connecting portions 120 and 130 are formed in the vertical direction, respectively. As such, the portion of the pixel PX is surrounded by the ring gate wiring including the upper and lower gate lines 110 and 120 and the left and right connecting portions 120 and 130.

In addition, the auxiliary line 150 is formed in the vertical direction between the left and right connecting portions 130 and 120 of the adjacent pixel PX on the insulating substrate 10, and the auxiliary line 150 is formed on the upper and lower gate lines. The upper and lower gate lines 110 and 120 are cut off so as not to be connected to the 110 and 120, and the end portions thereof are deviated by a predetermined angle from the vertical direction. In addition, the auxiliary line 150 is formed to be at least 6 μm or more away from the connection portions 120 and 130 of the gate wiring to avoid an electrical short circuit with the gate wiring.

The gate insulating film 20 is covered on the ring gate wirings 110, 120, 130, and 140 and the auxiliary line 150, and the semiconductor layer 200 made of amorphous silicon is formed on the upper insulating film 20. ) Is formed on top. The data line 300 is further formed on the gate insulating film 20 in the vertical direction so as to intersect the upper and lower gate lines 110 and 120, and overlaps the auxiliary line 150. A source electrode having a portion of the data line 300 extending therefrom overlaps the semiconductor layer 200, and a drain electrode 310 is formed to overlap the semiconductor layer 200 on the opposite side of the source electrode. The drain electrode 310 extends toward the front end pixel PX. Meanwhile, an ohmic contact layer 201 made of doped amorphous silicon is formed between the source electrode and the drain electrode 310 of the data line 300 and the semiconductor layer 200.

A protective insulating layer 30 is formed on the data line 300, the drain electrode 310, and the semiconductor layer 200, and the pixel surrounded by the ring gate lines 110, 120, 130, and 140 is formed on the protective insulating layer 30. A transparent pixel electrode 400 is formed in PX. The pixel electrode 400 is made of indium-tin-oxide (ITO) and is connected to the drain electrode 310 through a contact hole C2 bored through the protective insulating layer 30. In addition, the conductive connection pattern 410 is formed of the same material as the pixel electrode 400 on the protective insulating layer 30. The conductive connection pattern 410 is formed vertically across two pixels so as to intersect the lower gate line 140 of one pixel and the upper gate line 110 of an adjacent pixel, and each extends toward the end of the auxiliary line 150. And overlaps with the auxiliary line 150. In this case, the conductive connection pattern 410 is formed at the ends of the auxiliary line 150 projected toward the data line 300 through the contact holes C3 and C4 bored through the gate insulating film 20 and the protective insulating film 30, respectively. The data line 300 is connected to the data line 300 through the contact hole C1 formed in the protective insulating layer 30 on the data line 300.

As described above, since the connection pattern 410 of the above-described form is formed near the intersection of the data line 300 and the gate lines 110 and 140, which may cause the layers to be broken because the layers of layers are stacked, the data line ( Even if 300 is disconnected, a signal is transmitted along the connection pattern 410 connected to the auxiliary line 150.

Therefore, the defect caused by disconnection of the data line can be eliminated.

In the wiring structure of the thin film transistor substrate, the auxiliary line 150 is simultaneously formed in patterning the gate wiring metal film to form the gate wiring, and the conductive connection pattern 410 is formed in the patterning of the ITO pixel electrode 400. And forming contact layers C, C3, and C4 for connecting the connection pattern 410 to the data line 300 and the auxiliary line 150 at the same time. Because of the formation, no additional process is added.

FIG. 4 is a cross-sectional view taken along line II-II ′ of FIG. 1 and is a cross-sectional view of the liquid crystal display in a state in which a color filter substrate corresponds to the thin film transistor substrate.

As shown in FIG. 4, the thin film transistor substrate described with reference to FIGS. 1 to 3 corresponds to face the counter substrate 11 on which the transparent electrode 500 is formed. In this case, since the distance between the two substrates 10 and 11 is about several μm, the gate line 110 and 140 and the data line 300, which are relatively thick portions of the entire film thickness, intersect with each other, and a transparent conductive connection pattern is disposed on the upper portion. In the stepped portion 410, the conductive connection pattern 410 of the lower substrate and the transparent electrode 500 of the upper substrate 11 may be electrically connected by the conductive particles S2.

5 to 7 show a second embodiment to prevent electrical shorts between the upper and lower substrates.

5 is a wiring diagram of a liquid crystal display according to a second exemplary embodiment of the present invention, FIG. 6 is a cross-sectional view taken along line VI-VI 'of FIG. 5, and FIG. 7 is a cross-sectional view taken along line VII-VII' of FIG. 5. A liquid crystal display device in which a pixel electrode and a transparent opposing electrode are formed on a thin film transistor substrate and an opposing substrate, and an opening is formed in the transparent opposing electrode, thereby dividing a region.

In the second embodiment, the ring gate wirings 110, 120, 130, and 140 and the auxiliary line 150, the semiconductor layer 200, the data line 300, and the drain electrode 310 are almost similar to those of the first embodiment. And a transparent conductive connection pattern 410 is formed.

However, as illustrated in FIGS. 5 to 7, the pixel electrode 420 of the thin film transistor substrate includes a plurality of quadrangular portions, and these portions are connected in the vertical direction by thin connecting portions.

The transparent electrode 500 is formed over the entire surface of the substrate 11 on the opposite substrate surface facing the thin film transistor substrate. A cross-shaped opening 501 is formed in the transparent electrode 510 at a position facing the rectangular portion of the pixel electrode 420 of the thin film transistor substrate.

In addition, an opening 512 is formed in the transparent electrode 510 facing the portion where the transparent conductive connection pattern 410 is formed on the thin film transistor substrate. At this time, the intervals L2, L3, L4 between the edge of the opening 512 and the edge of the connection pattern 410 are patterned to be 2 μm or more, preferably 3 μm to 6 μm, so that conductive particles are present near the stepped portion. Even if there is no electrical short between the transparent electrode 510 of the upper opposing substrate and the conductive connection pattern 410 of the lower thin film transistor substrate.

Although not shown, a light shielding film is formed on the upper opposing substrate side with an organic insulating film, a metal film, or the like at a portion corresponding to the edge of the pixel PX. When the light shielding film is formed of a metal film such as chromium (Cr), an insulating film such as an organic film, a silicon oxide film, or a silicon nitride film is provided on the light shielding film, and the opening 512 is partially removed from the transparent electrode 510. The conductive connection pattern 410 and the light blocking layer of the lower thin film transistor substrate are not electrically shorted.

As in the first embodiment, the gap L1 between the auxiliary line 150 and the left and right connection parts 120 and 130 of the thin film transistor substrate is formed to be 6 μm or more, preferably 4 μm to 7 μm, and thus the auxiliary line Prevents short circuit between the 150 and the connection (120, 130).

Next, a manufacturing method of the liquid crystal display according to the second exemplary embodiment of the present invention will be described with reference to FIGS. 5 to 7 and 8A to 8F.

8A to 8F are plan views illustrating a method of manufacturing a liquid crystal display according to a second exemplary embodiment of the present invention, in the order of a process, and is illustrated based on a stepped portion in which lower and upper gate lines and data lines of two adjacent pixels cross each other. have.

First, as shown in FIGS. 5 to 7 and 8A, a gate wiring metal film is deposited and patterned on the lower thin film transistor substrate insulating substrate 10 to form upper and lower gate lines 110 and 140 and left and right connecting portions ( Ring gate wirings 120 and 130, isolated from ring gate wirings 110, 120, 130 and 140 between the left and right connecting portions 120 and 130 of two adjacent pixels and between the upper and lower gate lines 110 and 140. To form the auxiliary line 150 and the gate pads (not shown) formed at the ends of the gate lines 110 and 140. In this case, each of the connection parts 120 and 130 adjacent to the auxiliary line 150 is patterned to be separated from the auxiliary line 150 by 6 μm or more, so that the auxiliary line 150 and the connection parts 120 and 130 are electrically connected by the etching failure. Do not connect.

Next, as shown in FIGS. 5 to 7 and 8B, a ohmic contact layer such as a gate insulating film 20, a semiconductor film such as an amorphous silicon film, and a doped amorphous silicon film is successively deposited, and then an ohmic contact layer. And the semiconductor film are etched to form the semiconductor layer 200.

Next, as shown in FIGS. 5 to 7 and 8C, the metal film for data wiring is deposited and patterned, and is formed in a vertical direction so as to overlap the auxiliary line 150, and a portion thereof extends to the edge of the semiconductor layer 200. The data line 300 overlaps with the data line 300, and the drain electrode 310 overlaps with the semiconductor layer 200 on the opposite side of the data line 300, and is connected to one end of the data line 300. A data pad (not shown) is formed.

Next, as shown in FIGS. 5 to 7 and 8D, the contact hole exposing the gate pad and the data pad by depositing the protective insulating film 30 and etching the protective insulating film 30 and / or the gate insulating film 20. And contact holes C1, C2, C3, and C4 exposing both ends of the data line, the drain electrode, and the auxiliary line at the intersection.

Next, as shown in FIGS. 5 to 7 and 8E, a transparent conductive film such as ITO is deposited and patterned to form a pixel electrode in the pixel PX area inside the ring gate wirings 110, 120, 130, and 140. 420, and at the same time, the step portion where the gate lines 110 and 140 and the data line 300 intersect is formed through the contact holes C1, C3, and C4, respectively, the data line 300 and the auxiliary line of one pixel ( 150, a transparent conductive connection pattern 410 is formed to contact the auxiliary line 150 of two adjacent pixels to the data line 300 by contacting the auxiliary line 150 of the other adjacent pixel. In this case, the pixel electrode 420 is patterned in such a manner that a plurality of rectangular portions are connected in the vertical direction.

Next, a color filter, a light shielding film, a protective film, or the like is formed on the insulating substrate 11 for the upper color filter substrate. When the light shielding film is formed of an organic insulating film or the like instead of a metal film, it is not necessary to form a protective film on the light shielding film. Thereafter, a transparent electrode 510 such as ITO is formed on the color filter, the light blocking film, and the protective film, and then etched to form a cross-shaped opening 511 at a portion of the lower insulating substrate 10 corresponding to the square portion of the pixel electrode 400. An opening 512 is formed in which portions corresponding to the conductive connection patterns 410 are removed.

Next, as shown in FIG. 8F, the insulating substrate 10 for the lower thin film transistor substrate and the insulating substrate 11 for the upper color filter substrate are assembled.

As such, since the transparent electrode 510 of the portion corresponding to the upper portion of the conductive connection pattern 410 is removed, an electrical short between the upper substrate and the lower substrate is removed. In addition, the auxiliary line 150 of the lower substrate is simultaneously formed in the patterning of the gate wiring, and the conductive connection pattern 410 is simultaneously formed in the patterning of the pixel electrode 400, and the upper portion of the conductive connection pattern 410 is formed. Since the openings 512 of the transparent electrode 510 corresponding to are formed at the same time in forming the openings 511 for dividing the regions, the liquid crystal display device having the data auxiliary line 150 without adding a process is added. It can manufacture. As described above, by forming the auxiliary line 150 and the connecting parts 120 and 130 to have a spacing of 3 μm to 6 μm, an electrical short between the auxiliary line 150 and the connecting parts 120 and 130 may also be removed. .

As described above, in the liquid crystal display device and the manufacturing method thereof according to the present invention, an auxiliary line structure capable of reducing data line disconnection defects can be manufactured without adding a process, and the thin film transistor substrate and the upper color filter substrate are electrically The short circuit can be prevented, and the auxiliary line and the gate wiring can be prevented from being shorted.

Claims (20)

First substrate, A plurality of gate lines formed in the first direction on the first substrate, An auxiliary line formed in the first substrate and positioned between two adjacent gate lines; A gate insulating film covering the gate line and the auxiliary line, A semiconductor layer formed on a portion of the gate insulating film above the gate line; A plurality of data lines formed on the gate insulating layer to intersect the gate line and overlapping the auxiliary line, a source electrode extending from the data line to overlap the edge of the semiconductor layer, and an edge of the semiconductor layer opposite to the source electrode; A data wiring comprising a drain electrode overlapping the A protective insulating film covering the semiconductor layer and the data wiring, A pixel electrode formed on the protective insulating layer in the pixel region surrounded by the gate line and the data line and electrically connected to the drain electrode; A conductive connection pattern formed on the protective insulating layer and electrically connecting the auxiliary lines positioned on both sides of the gate line; A second substrate corresponding to face the first substrate, and A transparent electrode formed on the second substrate and having a first opening pattern formed in a first portion facing the conductive connection pattern; Liquid crystal display comprising a. In claim 1, And the conductive connection pattern is electrically connected to the data line. In claim 2, And the conductive connection pattern is connected to the auxiliary line through first and second contact holes formed in the protective insulating film and the gate insulating film, and is connected to the data line through third contact holes formed in the protective insulating film. In claim 3, And an end portion of the auxiliary line is formed to be out of a predetermined angle from the data line. In claim 1, And the conductive connection pattern and the pixel electrode are formed of ITO. In claim 1, The width of the second opening pattern is wider than the width of the conductive connection pattern. In claim 6, And an edge of the conductive connection pattern and an edge of the first opening pattern having a spacing of 3 μm to 6 μm. In claim 1, An auxiliary gate line formed parallel to the gate line between two adjacent gate lines, and And a connection part connecting the gate line and the auxiliary gate line in the second direction in the pixel area. In claim 8, And the auxiliary line is formed of the same material as the gate line, the auxiliary gate line, and the connection part. In claim 9, A liquid crystal display device wherein a distance between the connecting portion and the auxiliary line is 4 μm to 7 μm. In claim 1, And a light blocking film formed under the transparent electrode and surrounded by the outside of the pixel area. In claim 11, The light blocking film is an organic insulating film. In claim 11, And a protective film covering the light blocking film, wherein the light blocking film is a metal film. In claim 1, And a second opening pattern formed in the transparent electrode in a second portion facing the pixel region. The method of claim 14, The pixel electrode may have a plurality of quadrangular portions connected in the second direction, and the second opening pattern may have a cross shape formed in the quadrangular portion. Simultaneously forming a plurality of gate lines and a data auxiliary line positioned between two adjacent gate lines on the first substrate, Stacking a gate insulating film, Forming a data line on the gate insulating layer; Stacking a protective insulating film covering the data line; Patterning the protective insulating film and the gate insulating film to form a plurality of first contact holes exposing the data auxiliary line, and forming second contact holes exposing the data line; Forming a connection pattern connected to the pixel electrode and the data auxiliary line positioned at both sides of the gate line through the first contact hole and to the data line through the second contact hole; Depositing a transparent conductive film on a second substrate, Patterning the transparent conductive film to form a first opening pattern, and Matching the first substrate and the second substrate such that the first opening pattern and the connection pattern face each other; Method of manufacturing a liquid crystal display comprising a. The method of claim 16, Forming an auxiliary gate line parallel to the gate line between two adjacent gate lines in the forming of the gate line and the data auxiliary line, and forming a gate connection part connecting the auxiliary gate line and the gate line to each other; Method of manufacturing the device. The method of claim 17, And forming the gate connection part and the data auxiliary line so as to have a spacing of 4 μm to 7 μm. The method of claim 16, And manufacturing a width of the first opening pattern to be wider than a width of the connection pattern. The method of claim 19, A method of manufacturing a liquid crystal display device, wherein the first and second substrates are made to correspond to each other so that an interval between an edge of the first opening pattern and an edge of the connection pattern is 3 μm to 6 μm.