CN114185211A

CN114185211A - Array substrate and liquid crystal display panel

Info

Publication number: CN114185211A
Application number: CN202111242736.6A
Authority: CN
Inventors: 朱龙; 康报虹
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2021-10-25
Filing date: 2021-10-25
Publication date: 2022-03-15
Anticipated expiration: 2041-10-25
Also published as: CN114185211B

Abstract

The application relates to an array substrate and a liquid crystal display panel. The array substrate comprises a pixel area and a peripheral wiring area positioned on at least one side of the pixel area, the array substrate comprises a first metal layer, a grid insulation layer, a second metal layer, an interlayer insulation layer and a transparent conductive layer which are sequentially formed on a substrate, and the transparent conductive layer comprises a plurality of shielding common electrodes positioned in the pixel area and shielding metal strips which are positioned in the peripheral wiring area and are electrically connected with the shielding common electrodes; in the peripheral wiring area, the shielding metal strip comprises a plurality of sub-metal blocks which are segmented and distributed at intervals, the sub-metal blocks are electrically connected with the shielding common electrode, and the interval between every two adjacent sub-metal blocks exposes the area of the interlayer insulating layer covering the data line. The array substrate can reduce the static charge in the circuit, prevent the circuit from being damaged by explosion due to large current generated by the discharge of a large amount of static charge, and improve the reliability of the array substrate and the display effect of the liquid crystal display panel.

Description

Array substrate and liquid crystal display panel

Technical Field

The present disclosure relates to display technologies, and particularly to an array substrate and a liquid crystal display panel.

Background

The COA (Color-filter on Array, where the Color filter is located on the Array substrate) technology is an integration technology in which the Color filter is directly fabricated on the Array substrate, and can reduce the alignment error between the Color filter substrate and the Array substrate. In addition, data lines are disposed between adjacent color filters, and a BM (Black Matrix) is disposed on the side of the color filter substrate corresponding to the adjacent color filters, and is used for shielding the data lines, so as to improve the contrast of the liquid crystal display panel.

The DBS (Dataline BM Less, no black matrix is above the data line) technology cancels the BM above the data line on the basis of COA, and sets a transparent shielding common electrode on the array substrate side to shield the electric field above the data line, and makes the potential of the shielding common electrode the same as the potential of the common electrode on the color film substrate, so that the corresponding liquid crystal molecules above the data line are always kept in an undeflected state, thereby achieving the effect of light shielding.

However, in the peripheral wiring region on the pixel region side, only one insulating layer is present between the data line and the shielding metal strip, and the thickness of the insulating layer is usually only 2000 μm, so that the distance between the data line and the shielding common electrode is small, a large amount of static charges are easily accumulated, and the static charges discharge to generate a large current to damage the circuit.

Disclosure of Invention

The array substrate can reduce static charges in a circuit and prevent the circuit from being damaged by explosion due to large current generated by discharge of a large amount of static charges by removing the part of the shielding metal strip in the peripheral wiring area covering the data line or increasing the distance between the data line and the shielding metal strip.

In a first aspect, an embodiment of the present application provides an array substrate for a liquid crystal display panel, where the array substrate includes a pixel region and a peripheral routing region located on at least one side of the pixel region, and the array substrate includes a first metal layer, a gate insulating layer, a second metal layer, an interlayer insulating layer, and a transparent conductive layer, which are sequentially formed on a substrate; the first metal layer is provided with a plurality of scanning lines, the second metal layer is provided with a plurality of data lines, the transparent conducting layer comprises a plurality of shielding public electrodes positioned in the pixel area and shielding metal strips positioned in the peripheral wiring area and electrically connected with the shielding public electrodes, the orthographic projection of the shielding public electrodes on the substrate covers the orthographic projection of the data lines on the substrate, and the shielding metal strips are electrically connected with the first metal layer through first via holes.

In one possible embodiment, the sub-metal block is provided with a wire extending toward the pixel region, and the sub-metal block is electrically connected to the shielding common electrode through the wire.

In one possible embodiment, the conductive lines include a first conductive line, a second conductive line and a third conductive line electrically connected to each other, the first conductive line is parallel to the data line and electrically connected to the sub-metal block, the second conductive line and the third conductive line are symmetrically disposed on both sides of the first conductive line, and the second conductive line and the third conductive line are electrically connected to the shielding common electrodes on both sides of the sub-metal block, respectively.

In a possible implementation manner, the transparent conductive layer further includes a plurality of pixel electrodes located in the pixel region and distributed at intervals, and the pixel electrodes are not connected to the shielding common electrode; the array substrate further comprises a color resistance layer, the color resistance layer is arranged between the interlayer insulating layer and the transparent conducting layer, the color resistance layer comprises a plurality of color resistance units which are in one-to-one correspondence with the pixel electrodes, the color resistance units are of strip structures which are parallel to the data lines, and the orthographic projection of the overlapping area of two adjacent color resistance units on the substrate covers the orthographic projection of the data lines on the substrate.

In one possible implementation, the color resistance unit comprises a first light resistance section positioned in the pixel area and a second light resistance section positioned in the peripheral wiring area; the orthographic projection of the shielding common electrode on the substrate base plate covers the orthographic projection of the overlapped area of two adjacent first light resistance sections on the substrate base plate; the orthographic projection of the sub-metal blocks on the substrate base plate covers the orthographic projection of the corresponding second light resistance sections on the substrate base plate.

In one possible implementation, the plurality of color resistance units includes a red color resistance unit, a green color resistance unit, and a blue color resistance unit.

In one possible embodiment, an orthogonal projection of the first via hole on the substrate base plate is disposed adjacent to an orthogonal projection of the sub-metal block on the substrate base plate, and the first via hole penetrates through each film layer between the transparent conductive layer and the first metal layer.

In a possible implementation manner, the first metal layer is further formed with a common electrode line and a gate of the thin film transistor, the second metal layer is further formed with a source and a drain of the thin film transistor, each film layer between the transparent conductive layer and the first metal layer is provided with a second via hole, and an orthographic projection of the second via hole on the substrate is adjacent to an orthographic projection of the source or the drain on the substrate; one of the source electrode and the drain electrode is electrically connected with the data line, and the other one is exposed out of the second through hole, so that the pixel electrode is electrically connected with the source electrode or the drain electrode and the common electrode line respectively through the second through hole.

In a second aspect, an embodiment of the present application further provides an array substrate for a liquid crystal display panel, where the array substrate includes a pixel region and a peripheral wiring region located on at least one side of the pixel region, and the array substrate includes a first metal layer, a gate insulating layer, a second metal layer, an interlayer insulating layer, a color resistance layer, and a transparent conductive layer, which are sequentially formed on a substrate; the first metal layer is provided with a plurality of scanning lines, the second metal layer is provided with a plurality of data lines, the transparent conducting layer comprises a plurality of pixel electrodes, a plurality of shielding common electrodes and shielding metal strips, the pixel electrodes are positioned in the pixel area and distributed at intervals, the shielding metal strips are positioned in the peripheral wiring area and electrically connected with the shielding common electrodes, the orthographic projection of the shielding common electrodes on the substrate covers the orthographic projection of the data lines on the substrate, and the shielding metal strips are electrically connected with the first metal layer through first through holes; in the peripheral wiring area, the color resistance layer comprises a plurality of color resistance units which correspond to the pixel electrodes one by one, and each color resistance unit comprises a first light resistance section positioned in the pixel area and a second light resistance section positioned in the peripheral wiring area; the orthographic projection of the shielding common electrode on the substrate base plate covers the orthographic projection of the overlapped area of two adjacent first light resistance sections on the substrate base plate; the orthographic projection of the shielding metal strip on the substrate base plate covers the orthographic projection of the second light resistance section on the substrate base plate.

In a third aspect, an embodiment of the present application further provides a liquid crystal display panel, which includes a first substrate, a second substrate and a liquid crystal layer disposed between the first substrate and the second substrate, where the first substrate is the array substrate as described above.

According to the array substrate and the liquid crystal display panel, the shielding metal strips in the peripheral wiring area are segmented into the plurality of sub-metal blocks which are distributed at intervals, and the interval between two adjacent sub-metal blocks exposes the area of the interlayer insulating layer covering the data line, so that static charges in a circuit can be reduced, the circuit is prevented from being damaged due to the fact that a large amount of static charges are discharged to generate large current, and the reliability of the array substrate and the display effect of the liquid crystal display panel are improved.

Drawings

Features, advantages and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, like parts are provided with like reference numerals. The drawings are not necessarily to scale, and are merely intended to illustrate the relative positions of the layers, the thicknesses of the layers in some portions being exaggerated for clarity, and the thicknesses in the drawings are not intended to represent the proportional relationships of the actual thicknesses.

Fig. 1 is a schematic cross-sectional view illustrating a liquid crystal display panel according to an embodiment of the present disclosure;

fig. 2 is a schematic cross-sectional view illustrating a liquid crystal display panel according to another embodiment of the present disclosure;

fig. 3 is a top view of an array substrate according to an embodiment of the present disclosure;

fig. 4 is a cross-sectional view of the array substrate of fig. 3 taken along a direction B-B;

fig. 5 is a partially enlarged schematic view of a region C in fig. 3;

FIG. 6 shows a cross-sectional view of FIG. 5 along the direction D-D;

fig. 7 is a top view of an array substrate according to a second embodiment of the present disclosure;

fig. 8 is a partial enlarged structural view of a region E in fig. 7;

FIG. 9 shows a cross-sectional view of FIG. 8 taken along the direction F-F;

fig. 10 is a top view of an array substrate provided in a third embodiment of the present application;

fig. 11 is a partially enlarged schematic view of a region G in fig. 10;

fig. 12 shows a cross-sectional view along the direction H-H of fig. 11.

Description of reference numerals:

1. an array substrate; AA. A pixel region; NA, peripheral routing area; px-sub-pixel; h1, a first via; h2, a second via;

11. a substrate base plate;

12. a first metal layer; 121. scanning a line; 122. a common electrode line; 123. a gate electrode;

13. a gate insulating layer;

14. a second metal layer; 141. a data line; 142. a source electrode; 143. a drain electrode;

15. an interlayer insulating layer;

16. a transparent conductive layer; 161. pixel electrode, 162, shielding common electrode; 163. a shielding metal strip; 1631. a sub-metal block; 1632. a wire; a-a first conductive line; b-a second wire; c-a third conductive line;

17. a color resist layer; 171. a color resistance unit; 171a, a first photoresist segment; 171b, a second photoresist segment; 18. a planarization layer;

2. butting the substrates; 21. aligning the substrate; 22. aligning the common electrode; 3. and a liquid crystal layer.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof. In the drawings and the following description, at least some well-known structures and techniques have not been shown in detail in order to avoid unnecessarily obscuring the present application; also, the size of the region structures may be exaggerated for clarity. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Fig. 1 is a schematic cross-sectional view illustrating a liquid crystal display panel according to an embodiment of the present disclosure, and fig. 2 is a schematic cross-sectional view illustrating a liquid crystal display panel according to another embodiment of the present disclosure.

Referring to fig. 1 and 2, an embodiment of the present application provides a liquid crystal display panel, including: the liquid crystal display panel comprises an array substrate 1, a butt substrate 2 arranged opposite to the array substrate 1, and a liquid crystal layer 3 arranged between the array substrate 1 and the butt substrate 2. The liquid crystal layer 3 comprises a plurality of liquid crystal molecules, which are typically rod-shaped and both fluid like a liquid and have certain crystalline characteristics. When liquid crystal molecules are placed in an electric field, their alignment direction changes according to the change of the electric field.

Since the lcd panel is a non-emissive light receiving device, a light source needs to be provided through a backlight module disposed on a backlight side thereof. The liquid crystal display panel controls the rotation of liquid crystal molecules of the liquid crystal layer 3 by applying a driving voltage on the array substrate 1 and the butt substrate 2, so as to refract light provided by the backlight module to generate a picture. In order to display a color picture, a thin film transistor array is generally fabricated on the array substrate 1 for driving the rotation of liquid crystal molecules to control the display of each sub-pixel Px.

In some embodiments, a color resist layer 17 is prepared on the counter substrate 2 for forming the color of each subpixel Px. The array substrate 1 adopts a DBS (Dataline BM Less) architecture, and a transparent shielding common electrode 162 is disposed on the array substrate 1 side instead of the black matrix BM above the data line 141.

As shown in fig. 1, the docking board 2 includes a docking substrate 21, a color resist layer 17 disposed on the docking substrate 21, and a docking common electrode 22 disposed on the color resist layer 17. The transparent shielding common electrode 162 is disposed on one side of the array substrate 1 to shield the electric field above the data line 141, and the potential of the shielding common electrode 162 is the same as the potential of the alignment common electrode 22 on the docking substrate 2, so that the corresponding liquid crystal molecules above the data line 141 are always in an undeflected state, thereby achieving the effect of shielding light.

When the thin film transistor of the array substrate 1 is turned on by a signal applied to the gate electrode 123, a signal applied to the data line 141 is applied to the pixel electrode 161. Thereby, an electric field of a predetermined intensity is generated between the pixel electrode 161 and the counter common electrode 22, and the alignment of the liquid crystal molecules can be changed by applying different voltages, thereby adjusting the transmittance of light and displaying an image.

In other embodiments, a color resist layer 17 is prepared on the array substrate 1 side for forming the color of each subpixel Px. The array substrate 1 adopts a DBS (Dataline BM Less) architecture, and a transparent shielding common electrode 162 is disposed on the array substrate 1 side instead of the black matrix BM above the data line 141.

As shown in fig. 2, the docking substrate 2 includes a docking substrate 21 and a docking common electrode 22 disposed on the docking substrate 21. The transparent shielding common electrode 162 is disposed on one side of the array substrate 1 to shield the electric field above the data line 141, and the potential of the shielding common electrode 162 is the same as the potential of the alignment common electrode 22 on the docking substrate 2, so that the corresponding liquid crystal molecules above the data line 141 are always in an undeflected state, thereby achieving the effect of shielding light.

The following describes in detail a specific structure of an array substrate provided in embodiments of the present application with reference to the accompanying drawings.

Example one

Fig. 3 is a top view of an array substrate according to an embodiment of the present disclosure; fig. 4 is a cross-sectional view of the array substrate of fig. 3 taken along a direction B-B; fig. 5 is a partially enlarged schematic view of a region C in fig. 3; fig. 6 shows a cross-sectional view along the direction D-D of fig. 5.

As shown in fig. 3 and 4, the array substrate 1 includes a pixel area AA and a peripheral wiring area NA located at least on one side of the pixel area AA, and the array substrate 1 includes a first metal layer 12, a gate insulating layer 13, a second metal layer 14, an interlayer insulating layer 15 and a transparent conductive layer 16 sequentially formed on a substrate 11.

The first metal layer 12 is formed with a plurality of scan lines 121, the second metal layer 14 is formed with a plurality of data lines 141, the transparent conductive layer 16 includes a plurality of shielding common electrodes 162 located in the pixel area AA and shielding metal bars 163 located in the peripheral wiring area NA and electrically connected to the plurality of shielding common electrodes 162, an orthographic projection of the shielding common electrodes 162 on the substrate 11 covers an orthographic projection of the data lines 141 on the substrate 11, and the shielding metal bars 163 are electrically connected to the first metal layer 12 through first vias H1.

In the peripheral wiring area NA, the shielding metal strip 163 includes a plurality of sub-metal blocks 1631 that are segmented and distributed at intervals, the sub-metal blocks 1631 are electrically connected to the shielding common electrode 162, and the interval between two adjacent sub-metal blocks 1631 exposes the area where the interlayer insulating layer 15 covers the data line 141.

As shown in fig. 5, in the peripheral wiring area NA, only the interlayer insulating layer 15 exists between the data line 141 of the second metal layer 14 and the shielding metal strip 163 of the transparent conductive layer 16, and the thickness of the interlayer insulating layer 15 is usually only 2000 μm, so that the distance between the data line 141 and the shielding metal strip 163 is small, the capacitance is large, a large amount of static charges are easily accumulated, and the static charges discharge to generate a large current to burst the circuit, which causes a bad phenomenon such as LCD display abnormality.

Therefore, in the array substrate 1 provided in the embodiment of the present application, the shielding metal strips 163 in the peripheral wiring area NA are segmented into the plurality of sub-metal blocks 1631 distributed at intervals, and the interval between two adjacent sub-metal blocks 1631 exposes the area of the interlayer insulating layer 15 covering the data line 141, so that a part of the shielding metal strips 163 covering the data line 141 is removed, thereby reducing the electrostatic charges in the circuit, preventing the circuit from being damaged by the large current generated by the large electrostatic charge discharge, and improving the reliability of the array substrate 1.

Further, in order to electrically connect the sub-metal block 1631 of the peripheral wiring area NA with the shielding common electrode 162 of the display area AA, the sub-metal block 1631 is provided with a conductive line 1632 extending toward the pixel area AA, and the sub-metal block 1631 is electrically connected with the shielding common electrode 162 through the conductive line 1632.

In some embodiments, the conductive line 1632 includes a first conductive line a, a second conductive line b, and a third conductive line c electrically connected to each other, the first conductive line a is parallel to the data line 141 and electrically connected to the sub-metal block 1631, the second conductive line b and the third conductive line c are symmetrically disposed at both sides of the first conductive line a, and the second conductive line b and the third conductive line c are electrically connected to the shielding common electrodes 162 at both sides of the sub-metal block 1631, respectively.

The conducting wire 1632 is divided into two branches, i.e., a second conducting wire b and a third conducting wire c, which are electrically connected to the two adjacent shielding common electrodes 162, as a fool-proof design, when one of the two branches is in poor contact, the other branch can be electrically connected to the shielding common electrode 162, so that the reliability of the array substrate 1 is improved.

Further, as described above, the shield metal bar 163 is electrically connected to the first metal layer 12 through the first via H1. The orthographic projection of the first via H1 on the substrate base plate 11 is adjacent to the orthographic projection of the sub metal block 1631 on the substrate base plate 11, and the first via H1 penetrates through each film layer between the transparent conductive layer 16 and the first metal layer 12.

In some embodiments, as shown in fig. 4, the first metal layer 12 is further formed with a common electrode line 122 and a gate electrode 123 of the thin film transistor, the second metal layer 14 is further formed with a source electrode 142 and a drain electrode 143 of the thin film transistor, a second via H2 is disposed on each film layer between the transparent conductive layer 16 and the first metal layer 12, and an orthographic projection of the second via H2 on the substrate base 11 is disposed adjacent to an orthographic projection of the source electrode 142 or the drain electrode 143 on the substrate base 11.

One of the source electrode 142 and the drain electrode 143 is electrically connected to the data line 141, and the other is exposed from the second via H2, so that the pixel electrode 161 is electrically connected to the source electrode 142 or the drain electrode 143 and the common electrode line 122 through the second via H2, respectively. By such arrangement, the structure and the manufacturing process of the array substrate 1 can be simplified, and the thickness of the liquid crystal display panel can be further reduced.

In addition, the transparent conductive layer 16 further includes a plurality of pixel electrodes 161 located in the pixel area AA and distributed at intervals, and the pixel electrodes 161 are not connected to the shielding common electrode 162. The pixel electrode 161 is electrically connected to a corresponding thin film transistor, and the thin film transistor is also electrically connected to a corresponding scan line 121 and data line 141. The plurality of scan lines 121 and the plurality of data lines 141 cross each other to define a plurality of subpixels Px, which correspond one-to-one to the plurality of pixel electrodes 161.

In some embodiments, the array substrate 1 further includes a planarization layer (not shown) formed on and covering the thin film transistors and the data lines 141, and an alignment film (not shown), wherein the plurality of pixel electrodes 161 are disposed on the planarization layer and the alignment film is disposed on the pixel electrodes 161.

Accordingly, as shown in fig. 1, the side of the butt substrate 2 of the liquid crystal display panel is prepared with a color resist layer 17 for forming the color of each sub-pixel Px. The liquid crystal display panel controls the rotation of liquid crystal molecules of the liquid crystal layer 3 by applying a driving voltage to the pixel electrode 161 of the array substrate 1 and the alignment common electrode 22 of the docking substrate 2, so as to refract light provided by the backlight module to generate a picture.

Example two

Fig. 6 is a plan view of an array substrate according to a second embodiment of the present disclosure, fig. 7 is a schematic diagram illustrating a partially enlarged structure of a region E in fig. 6, and fig. 8 is a cross-sectional view of fig. 7 along a direction F-F.

Referring to fig. 6 to 8, an Array substrate 1 is further provided in the present embodiment, which is similar to the Array substrate 1 in the first embodiment, except that the Array substrate 1 adopts a COA (Color-filter on Array, where Color filters are located on the Array substrate side) structure, that is, a Color resist layer 17 is disposed on one side of the Array substrate 1 for forming the Color of each sub-pixel Px. Accordingly, the structure of the docking substrate 2 is as shown in fig. 2.

Specifically, the array substrate 1 further includes a color resistance layer 17, the color resistance layer 17 is disposed between the interlayer insulating layer 15 and the transparent conductive layer 16, the color resistance layer 17 includes a plurality of color resistance units 171 corresponding to the plurality of pixel electrodes 161 one by one, the color resistance units 171 are in a stripe structure disposed parallel to the data lines 141, and an orthogonal projection of an overlapping area of two adjacent color resistance units 171 on the substrate 11 covers an orthogonal projection of the data lines 141 on the substrate 11.

Further, the color resistance unit 171 includes a first photo-resist segment 171a located in the pixel area AA and a second photo-resist segment 171b located in the peripheral routing area NA.

The orthographic projection of the shielding common electrode 162 on the substrate base plate 11 covers the orthographic projection of the overlapped area of the adjacent two first light blocking sections 171a on the substrate base plate 11.

The orthographic projection of the sub-metal block 1631 on the substrate base 11 covers the orthographic projection of the corresponding second photoresist segment 171b on the substrate base 11.

As shown in fig. 7 and 8, the shielding metal strips 163 in the peripheral wiring area NA are arranged in segments as a plurality of sub-metal blocks 1631 distributed at intervals, and the interval between two adjacent sub-metal blocks 1631 exposes the area of the interlayer insulating layer 15 covering the data line 141, and the shielding metal strips 163 covering the data line 141 are partially removed, so that the electrostatic charge in the circuit can be reduced, and the circuit can be prevented from being damaged by a large current generated by a large amount of electrostatic discharge.

Meanwhile, the interlayer insulating layer 15 and the color resistance layer 17 are arranged between the data line 141 of the second metal layer 14 and the sub-metal block 1631 of the transparent conductive layer 16, and compared with the technical scheme that only the interlayer insulating layer 15 is arranged between the second metal layer 14 and the transparent conductive layer 16 in the related art, the thickness between the two layers is increased, and the distance between the data line 141 and the sub-metal block 1631 is increased, so that the electrostatic charge in the circuit can be further reduced, the circuit is prevented from being damaged due to the large current generated by the discharge of a large amount of electrostatic charge, and the reliability of the array substrate and the display effect of the liquid crystal display panel are further improved.

In some embodiments, the plurality of color resistance units 171 include a red color resistance unit 171, a green color resistance unit 171, and a blue color resistance unit 171. In other embodiments, the color resistance units 171 may also include color resistance units of other colors, which are determined according to specific design requirements and are not described in detail.

In the array substrate 1 provided in the embodiment of the present application, on one hand, the shielding metal strips 163 in the peripheral wiring area NA are segmented into the plurality of sub-metal blocks 1631 that are distributed at intervals, and the interval between two adjacent sub-metal blocks 1631 exposes the area where the interlayer insulating layer 15 covers the data line 141, and on the other hand, the color resist layer 17 is added between the data line 141 of the second metal layer 14 and the sub-metal block 1631 of the transparent conductive layer 16, so as to increase the distance between the data line 141 and the sub-metal block 1631, thereby further reducing the electrostatic charge in the circuit, preventing the circuit from being damaged by a large current generated by the discharge of a large amount of electrostatic charge, and further improving the reliability of the array substrate and the display effect of the liquid crystal display panel.

EXAMPLE III

Fig. 9 is a plan view of an array substrate according to a third embodiment of the present application, fig. 10 is a schematic diagram illustrating a partially enlarged structure of a region G in fig. 9, and fig. 11 is a cross-sectional view of fig. 10 taken along a direction H-H.

Referring to fig. 9 to 11, an Array substrate 1 is further provided in the embodiment of the present application, the Array substrate 1 has a similar structure to the Array substrate 1 described in the second embodiment, and both adopt a COA (Color-filter on Array, where Color filters are located on the Array substrate side) architecture, that is, the Color resist layer 17 is disposed on one side of the Array substrate 1 for forming the Color of each sub-pixel Px. The difference is that the color resist layer 17 and the shielding metal strip 163 have different structures in the peripheral display region. That is, the shielding metal strips 163 of the peripheral display region are not arranged in segments, and the color resist layer 17 is laid on the peripheral display region in a whole layer. Accordingly, the structure of the docking substrate 2 is as shown in fig. 2.

Specifically, the array substrate includes a pixel area AA and a peripheral wiring area NA located on at least one side of the pixel area AA, and the array substrate includes a first metal layer 12, a gate insulating layer 13, a second metal layer 14, an interlayer insulating layer 15, a color resistance layer 17 and a transparent conductive layer 16, which are sequentially formed on a substrate 11.

The first metal layer 12 is formed with a plurality of scanning lines 121 and a plurality of common electrode lines 122, the second metal layer 14 is formed with a plurality of data lines 141, the transparent conductive layer 16 includes a plurality of pixel electrodes 161 located in the pixel area AA and distributed at intervals, a plurality of shielding common electrodes 162, and shielding metal bars 163 located in the peripheral wiring area NA and electrically connected to the plurality of shielding common electrodes 162, an orthographic projection of the shielding common electrodes 162 on the substrate 11 covers an orthographic projection of the data lines 141 on the substrate 11, the shielding metal bars 163 are electrically connected to the first metal layer 12 through a first via H1, and the pixel electrodes 161 are electrically connected to the common electrode lines 122 through a second via H2.

In the peripheral routing area NA, the color resist layer 17 includes a plurality of color resist units 171 corresponding to the plurality of pixel electrodes 161 one by one, and the color resist units 171 include a first photoresist segment 171a located in the pixel area AA and a second photoresist segment 171b located in the peripheral routing area NA.

The orthographic projection of the shielding metal strip 163 on the substrate base 11 covers the orthographic projection of the second photoresist segment 171b on the substrate base 11.

In the embodiment of the present application, since the interlayer insulating layer 15 and the color resistance layer 17 are disposed between the data line 141 of the second metal layer 14 and the shielding metal strip 163 of the transparent conductive layer 16, compared with the technical scheme in the related art in which only the interlayer insulating layer 15 is disposed between the second metal layer 14 and the transparent conductive layer 16, the thickness between the two layers is increased, and the distance between the data line 141 and the shielding metal strip 163 is increased, so that the electrostatic charge in the circuit can be reduced, the circuit can be prevented from being damaged by a large current generated by the discharge of a large amount of electrostatic charge, and the reliability of the array substrate is improved.

According to the array substrate 1 provided by the embodiment of the application, the color resistance layer 17 is additionally arranged between the data line 141 of the second metal layer 14 and the transparent conductive layer 16, so that the distance between the data line 141 and the shielding metal strip 163 is increased, static charges in a circuit can be reduced, the circuit is prevented from being damaged due to large current generated by discharging of a large amount of static charges, and the reliability of the array substrate is improved.

It can be understood that the technical solution of the array substrate 1 provided In the embodiments of the present application can be widely applied to various liquid crystal display panels, such as TN (Twisted Nematic) display panel, IPS (In-plane switching) display panel, VA (Vertical Alignment) display panel, and MVA (Multi-Domain Vertical Alignment) display panel.

It should be readily understood that "on … …", "above … …" and "above … …" in this application should be interpreted in its broadest sense such that "on … …" means not only "directly on something", but also includes the meaning of "on something" with intervening features or layers therebetween, and "above … …" or "above … …" includes not only the meaning of "above something" or "above" but also includes the meaning of "above something" or "above" without intervening features or layers therebetween (i.e., directly on something).

The term "substrate" as used herein refers to a material upon which subsequent layers of material are added. The substrate base plate itself may be patterned. The material added atop the substrate base plate may be patterned or may remain unpatterned. Further, the substrate base plate may comprise a wide range of materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate base plate may be made of a non-conductive material (e.g., glass, plastic, or sapphire wafer, etc.).

The term "layer" as used herein may refer to a portion of material that includes a region having a thickness. A layer may extend over the entire underlying or overlying structure or may have a smaller extent than the underlying or overlying structure. Furthermore, a layer may be a region of a continuous structure, homogeneous or heterogeneous, having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of lateral planes at the top and bottom surfaces. The layers may extend laterally, vertically, and/or along a tapered surface. The substrate base may be a layer, may include one or more layers therein, and/or may have one or more layers located thereon, above and/or below. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (within which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate is used for a liquid crystal display panel and comprises a pixel area and a peripheral wiring area positioned on at least one side of the pixel area, wherein the array substrate comprises a first metal layer, a grid electrode insulating layer, a second metal layer, an interlayer insulating layer and a transparent conducting layer which are sequentially formed on a substrate;

the first metal layer is formed with a plurality of scanning lines, the second metal layer is formed with a plurality of data lines, the transparent conductive layer comprises a plurality of shielding common electrodes positioned in the pixel area and shielding metal strips positioned in the peripheral wiring area and electrically connected with the shielding common electrodes, the orthographic projection of the shielding common electrodes on the substrate covers the orthographic projection of the data lines on the substrate, and the shielding metal strips are electrically connected with the first metal layer through first via holes,

in the peripheral wiring area, the shielding metal strip comprises a plurality of sub-metal blocks which are segmented and distributed at intervals, the sub-metal blocks are electrically connected with the shielding common electrode, and the interval between every two adjacent sub-metal blocks exposes the area of the interlayer insulating layer covering the data line.

2. The array substrate of claim 1, wherein the sub-metal block is provided with a conductive line extending toward the pixel region, and the sub-metal block is electrically connected to the shielding common electrode through the conductive line.

3. The array substrate of claim 2, wherein the conductive lines comprise a first conductive line, a second conductive line and a third conductive line electrically connected to each other, the first conductive line is parallel to the data line and electrically connected to the sub-metal block, the second conductive line and the third conductive line are symmetrically disposed on two sides of the first conductive line, and the second conductive line and the third conductive line are electrically connected to the shielding common electrodes on two sides of the sub-metal block, respectively.

4. The array substrate of claim 1, wherein the transparent conductive layer further comprises a plurality of pixel electrodes located in the pixel region and distributed at intervals, and the pixel electrodes are not connected to the shielding common electrode;

the array substrate further comprises a color resistance layer, the color resistance layer is arranged between the interlayer insulating layer and the transparent conducting layer, the color resistance layer comprises a plurality of color resistance units which are in one-to-one correspondence with the pixel electrodes, the color resistance units are of strip structures which are parallel to the data lines, and the orthographic projection of the overlapping area of two adjacent color resistance units on the substrate covers the orthographic projection of the data lines on the substrate.

5. The array substrate of claim 4, wherein the color resistance unit comprises a first photo-resist segment located in the pixel region and a second photo-resist segment located in the peripheral routing region;

the orthographic projection of the shielding common electrode on the substrate base plate covers the orthographic projection of the overlapped area of two adjacent first light resistance sections on the substrate base plate;

and the orthographic projection of the sub-metal block on the substrate base plate covers the orthographic projection of the corresponding second light resistance section on the substrate base plate.

6. The array substrate of claim 4, wherein the plurality of color-resisting units comprise a red color-resisting unit, a green color-resisting unit and a blue color-resisting unit.

7. The array substrate of claim 1, wherein an orthographic projection of the first via on the substrate base plate is disposed adjacent to an orthographic projection of the sub-metal block on the substrate base plate, and the first via penetrates through each film layer between the transparent conductive layer and the first metal layer.

8. The array substrate of claim 1, wherein the first metal layer further forms a common electrode line and a gate electrode of a thin film transistor, the second metal layer further forms a source electrode and a drain electrode of the thin film transistor, a second via hole is disposed on each film layer between the transparent conductive layer and the first metal layer, and an orthographic projection of the second via hole on the substrate is disposed adjacent to an orthographic projection of the source electrode or the drain electrode on the substrate;

one of the source electrode and the drain electrode is electrically connected with the data line, and the other one is exposed out of the second via hole, so that the pixel electrode is electrically connected with the source electrode or the drain electrode and the common electrode line through the second via hole respectively.

9. An array substrate is used for a liquid crystal display panel and comprises a pixel area and a peripheral wiring area positioned on at least one side of the pixel area, wherein the array substrate comprises a first metal layer, a grid electrode insulating layer, a second metal layer, an interlayer insulating layer, a color resistance layer and a transparent conducting layer which are sequentially formed on a substrate;

the first metal layer is formed with a plurality of scanning lines, the second metal layer is formed with a plurality of data lines, the transparent conductive layer comprises a plurality of pixel electrodes which are positioned in the pixel area and distributed at intervals, a plurality of shielding common electrodes and shielding metal strips which are positioned in the peripheral wiring area and electrically connected with the shielding common electrodes, the orthographic projection of the shielding common electrodes on the substrate covers the orthographic projection of the data lines on the substrate, and the shielding metal strips are electrically connected with the first metal layer through first via holes,

in the peripheral wiring area, the color resistance layer comprises a plurality of color resistance units which are in one-to-one correspondence with the plurality of pixel electrodes, and each color resistance unit comprises a first light resistance section positioned in the pixel area and a second light resistance section positioned in the peripheral wiring area;

and the orthographic projection of the shielding metal strip on the substrate base plate covers the orthographic projection of the second light resistance section on the substrate base plate.

10. A liquid crystal display panel comprising:

an array substrate according to any one of claims 1 to 8 or claim 9;

the butt joint substrate is arranged opposite to the array substrate;

and the liquid crystal layer is arranged between the array substrate and the butt joint substrate.