CN114185211B - Array substrate and liquid crystal display panel - Google Patents
Array substrate and liquid crystal display panel Download PDFInfo
- Publication number
- CN114185211B CN114185211B CN202111242736.6A CN202111242736A CN114185211B CN 114185211 B CN114185211 B CN 114185211B CN 202111242736 A CN202111242736 A CN 202111242736A CN 114185211 B CN114185211 B CN 114185211B
- Authority
- CN
- China
- Prior art keywords
- substrate
- layer
- shielding
- array substrate
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 186
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 45
- 239000010410 layer Substances 0.000 claims abstract description 186
- 229910052751 metal Inorganic materials 0.000 claims abstract description 136
- 239000002184 metal Substances 0.000 claims abstract description 136
- 230000002093 peripheral effect Effects 0.000 claims abstract description 39
- 239000011229 interlayer Substances 0.000 claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- 239000010409 thin film Substances 0.000 claims description 13
- 239000010408 film Substances 0.000 claims description 9
- 210000001503 joint Anatomy 0.000 claims description 5
- 230000003068 static effect Effects 0.000 abstract description 19
- 230000000694 effects Effects 0.000 abstract description 8
- 230000002829 reductive effect Effects 0.000 description 8
- 230000005684 electric field Effects 0.000 description 7
- 238000007599 discharging Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000011159 matrix material Substances 0.000 description 5
- 238000003032 molecular docking Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
Abstract
The application relates to an array substrate and a liquid crystal display panel. The array substrate comprises a pixel area and a peripheral wiring area positioned at least one side of the pixel area, wherein the array substrate comprises a first metal layer, a gate insulating layer, a second metal layer, an interlayer insulating layer and a transparent conductive layer which are sequentially formed on a substrate, and the transparent conductive layer comprises a plurality of shielding public electrodes positioned in the pixel area and shielding metal strips positioned in the peripheral wiring area and electrically connected with the shielding public electrodes; the shielding metal strip comprises a plurality of sub-metal blocks which are segmented and distributed at intervals in the peripheral wiring area, the sub-metal blocks are electrically connected with the shielding public electrode, and the interval between two adjacent sub-metal blocks exposes the area of the interlayer insulating layer covering the data line. The array substrate can reduce static charges in the circuit, prevent the circuit from being blasted due to large current generated by discharge of a large amount of static charges, and improve the reliability of the array substrate and the display effect of the liquid crystal display panel.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to an array substrate and a liquid crystal display panel.
Background
The COA (Color-filter on Array) technology is an integrated technology in which a Color filter is directly fabricated on an Array substrate, so that an alignment error between the Color filter substrate and the Array substrate can be reduced. In addition, a data line is arranged between the adjacent color filters, and a BM (Black Matrix) is arranged between the color film substrate side corresponding to the adjacent color filters, and is used for shading the data line so as to improve the contrast of the liquid crystal display panel.
The DBS (data BM Less) technology is to cancel BM above the data line on the basis of COA, set transparent shielding public electrode on the side of the array substrate to shield electric field above the data line, and make the potential of the shielding public electrode identical to that of the public electrode on the color film substrate, so that the corresponding liquid crystal molecules above the data line are always kept in undeflected state, and further the shading effect is achieved.
However, in the peripheral wiring area at one side of the pixel area, only one insulating layer is present between the data line and the shielding metal strip, and the thickness of the insulating layer is usually only 2000 μm, which results in a small distance between the data line and the shielding common electrode, and a large amount of static charges are easily accumulated, and the static charges discharge can generate a large current burst circuit.
Disclosure of Invention
The application aims to provide an array substrate and a liquid crystal display panel, wherein the array substrate can reduce static charges in a circuit by removing a part of a peripheral wiring area, which is covered by a shielding metal strip, or increasing the distance between the data wire and the shielding metal strip, so as to prevent the circuit from being burst due to large current generated by discharging a large amount of static charges.
In a first aspect, an embodiment of the present application provides an array substrate for a liquid crystal display panel, where the array substrate includes a pixel area and a peripheral wiring area located at least one side of the pixel area, and the array substrate includes a first metal layer, a gate insulating layer, a second metal layer, an interlayer insulating layer, and a transparent conductive layer sequentially formed on a substrate; the first metal layer is formed with a plurality of scanning lines, the second metal layer is formed with a plurality of data lines, the transparent conducting layer comprises a plurality of shielding public electrodes located in a pixel area and shielding metal strips located in a peripheral wiring area and electrically connected with the shielding public electrodes, orthographic projection of the shielding public electrodes on a substrate covers orthographic projection of the data lines on the substrate, the shielding metal strips are electrically connected with the first metal layer through first through holes, the shielding metal strips comprise a plurality of sub-metal blocks which are segmented and distributed at intervals in the peripheral wiring area, the sub-metal blocks are electrically connected with the shielding public electrodes, and an interval between two adjacent sub-metal blocks exposes an area where an interlayer insulating layer covers the data lines.
In one possible embodiment, the sub-metal block is provided with a wire extending toward the pixel region, and the sub-metal block is electrically connected to the shielding common electrode through the wire.
In one possible embodiment, the conductive lines include a first conductive line, a second conductive line, and a third conductive line electrically connected to each other, the first conductive line is parallel to the data line and electrically connected to the sub-metal block, the second conductive line and the third conductive line are symmetrically disposed at both sides of the first conductive line, and the second conductive line and the third conductive line are electrically connected to the shielding common electrode at both sides of the sub-metal block, respectively.
In one possible implementation manner, the transparent conductive layer further comprises a plurality of pixel electrodes which are located in the pixel area and are distributed at intervals, and the pixel electrodes are not connected with the shielding common electrode; the array substrate further comprises a color resistance layer, the color resistance layer is arranged between the interlayer insulating layer and the transparent conducting layer, the color resistance layer comprises a plurality of color resistance units corresponding to the pixel electrodes one by one, the color resistance units are of strip-shaped structures which are parallel to the data lines, and orthographic projection of overlapping areas of two adjacent color resistance units on the substrate covers orthographic projection of the data lines on the substrate.
In one possible implementation, the color resist unit includes a first photoresist segment located in the pixel region and a second photoresist segment located in the peripheral wiring region; the orthographic projection of the shielding public electrode on the substrate covers the orthographic projection of the overlapping area of the two adjacent first photoresist sections on the substrate; the orthographic projection of the sub-metal block on the substrate covers the orthographic projection of the corresponding second photoresist segment on the substrate.
In one possible embodiment, the plurality of color resist units includes a red color resist unit, a green color resist unit, and a blue color resist unit.
In one possible embodiment, the orthographic projection of the first via on the substrate is disposed adjacent to the orthographic projection of the sub-metal block on the substrate, and the first via penetrates each film layer between the transparent conductive layer and the first metal layer.
In one possible implementation manner, the first metal layer is further formed with a common electrode line and a gate electrode of the thin film transistor, the second metal layer is further formed with a source electrode and a drain electrode of the thin film transistor, a second via hole is arranged on each film layer between the transparent conductive layer and the first metal layer, and the orthographic projection of the second via hole on the substrate is arranged adjacent to the orthographic projection of the source electrode or the drain electrode on the substrate; either the source electrode or the drain electrode is electrically connected with the data line, and the other is exposed from the second via hole, so that the pixel electrode is electrically connected with the source electrode or the drain electrode and the common electrode line through the second via hole, respectively.
In a second aspect, an embodiment of the present application further provides an array substrate for a liquid crystal display panel, where the array substrate includes a pixel area and a peripheral wiring area located at least one side of the pixel area, and the array substrate includes a first metal layer, a gate insulating layer, a second metal layer, an interlayer insulating layer, a color resist layer, and a transparent conductive layer sequentially formed on a substrate; the transparent conductive layer comprises a plurality of pixel electrodes, a plurality of shielding common electrodes and shielding metal strips, wherein the pixel electrodes are arranged in a pixel area and are distributed at intervals, the shielding metal strips are arranged in a peripheral wiring area and are electrically connected with the shielding common electrodes, orthographic projection of the shielding common electrodes on a substrate covers orthographic projection of the data lines on the substrate, and the shielding metal strips are electrically connected with the first metal layer through first through holes; the color resistance layer comprises a plurality of color resistance units which are in one-to-one correspondence with the pixel electrodes in the peripheral wiring area, wherein the color resistance units comprise a first light resistance section positioned in the pixel area and a second light resistance section positioned in the peripheral wiring area; the orthographic projection of the shielding public electrode on the substrate covers the orthographic projection of the overlapping area of the two adjacent first photoresist sections on the substrate; the orthographic projection of the shielding metal strip on the substrate base plate covers the orthographic projection of the second photoresist section on the substrate base plate.
In a third aspect, an embodiment of the present application further provides a liquid crystal display panel, including a first substrate, a second substrate, and a liquid crystal layer disposed between the first substrate and the second substrate, where the first substrate is an array substrate as described above.
According to the array substrate and the liquid crystal display panel provided by the embodiment of the application, the shielding metal strips of the peripheral wiring area are arranged into the plurality of sub-metal blocks in a segmented mode, the interval between two adjacent sub-metal blocks exposes the area of the interlayer insulating layer covering the data line, static charges in the circuit can be reduced, the circuit is prevented from being burst due to large current generated by discharging of a large amount of static charges, and the reliability of the array substrate and the display effect of the liquid crystal display panel are improved.
Drawings
Features, advantages, and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, like parts are designated with like reference numerals. The drawings are not drawn to scale, but are merely for illustrating relative positional relationships, and the layer thicknesses of certain portions are exaggerated in order to facilitate understanding, and the layer thicknesses in the drawings do not represent the actual layer thickness relationships.
Fig. 1 is a schematic cross-sectional view of a liquid crystal display panel according to an embodiment of the disclosure;
fig. 2 is a schematic cross-sectional view of a liquid crystal display panel according to another embodiment of the present disclosure;
fig. 3 is a top view of an array substrate according to an embodiment of the disclosure;
FIG. 4 illustrates a cross-sectional view of the array substrate of FIG. 3 along the B-B direction;
fig. 5 shows a partially enlarged structural schematic view of the region C in fig. 3;
FIG. 6 shows a cross-sectional view of FIG. 5 along the direction D-D;
fig. 7 shows a top view of an array substrate provided in a second embodiment of the present application;
FIG. 8 shows a partially enlarged schematic construction of the region E in FIG. 7;
FIG. 9 shows a cross-sectional view of FIG. 8 along the direction F-F;
fig. 10 shows a top view of an array substrate provided in a third embodiment of the present application;
fig. 11 shows a partially enlarged structural schematic view of the region G in fig. 10;
fig. 12 shows a cross-section of fig. 11 along the direction H-H.
Reference numerals illustrate:
1. an array substrate; AA. A pixel region; NA, peripheral wiring area; px-subpixels; h1, a first via hole; h2, second vias;
11. a substrate base;
12. a first metal layer; 121. a scanning line; 122. a common electrode line; 123. a gate;
13. a gate insulating layer;
14. a second metal layer; 141. a data line; 142. a source electrode; 143. a drain electrode;
15. an interlayer insulating layer;
16. a transparent conductive layer; 161. pixel electrodes 162, shielding common electrode; 163. shielding metal strips; 1631. a sub-metal block; 1632. a wire; a-a first wire; b-a second wire; c-a third wire;
17. a color resist layer; 171. a color resistance unit; 171a, a first photoresist segment; 171b, a second photoresist segment; 18. a planarization layer;
2. butting substrates; 21. aligning the substrate; 22. aligning the common electrode; 3. and a liquid crystal layer.
Detailed Description
Features and exemplary embodiments of various aspects of the present application are described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by showing an example of the present application. In the drawings and the following description, at least some well-known structures and techniques are not shown in order to avoid unnecessarily obscuring the present application; also, the size of the region structures may be exaggerated for clarity. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Fig. 1 is a schematic cross-sectional view of a liquid crystal display panel according to an embodiment of the present application, and fig. 2 is a schematic cross-sectional view of a liquid crystal display panel according to another embodiment of the present application.
Referring to fig. 1 and 2, an embodiment of the present application provides a liquid crystal display panel, including: the array substrate 1, a butt joint substrate 2 arranged opposite to the array substrate 1 and a liquid crystal layer 3 arranged between the array substrate 1 and the butt joint substrate 2. The liquid crystal layer 3 comprises a plurality of liquid crystal molecules, typically rod-shaped, which both flow like a liquid and have certain crystal characteristics. When the liquid crystal molecules are in an electric field, the alignment direction thereof is changed according to the change of the electric field.
Since the liquid crystal display panel is a non-emissive light receiving element, a light source is required to be provided by a backlight module disposed on one side of a backlight surface thereof. The liquid crystal display panel controls the rotation of liquid crystal molecules of the liquid crystal layer 3 by applying driving voltages to the array substrate 1 and the butt joint substrate 2 so as to refract light provided by the backlight module to generate a picture. In order to display a color picture, a thin film transistor array is generally prepared on the array substrate 1 for driving the rotation of liquid crystal molecules, and controlling the display of each subpixel Px.
In some embodiments, an excellent resist layer 17 is prepared on the docking substrate 2 for forming the color of each sub-pixel Px. The array substrate 1 adopts a DBS (data BM Less, black matrix) architecture, and a transparent shielding common electrode 162 is disposed on the side of the array substrate 1 to replace the black matrix BM above the data line 141.
As shown in fig. 1, the docking substrate 2 includes a counter substrate 21, a color resist layer 17 provided on the counter substrate 21, and a counter common electrode 22 provided on the color resist layer 17. A transparent shielding common electrode 162 is disposed on one side of the array substrate 1 to shield the electric field above the data line 141, and the potential of the shielding common electrode 162 is the same as the potential of the alignment common electrode 22 on the opposite substrate 2, so that the liquid crystal molecules corresponding to the upper side of the data line 141 are always kept in an undeflected state, and further the light shielding effect is achieved.
When the thin film transistor of the array substrate 1 is turned on by a signal applied to the gate electrode 123, a signal applied to the data line 141 is applied to the pixel electrode 161. Thereby, an electric field of a predetermined intensity is generated between the pixel electrode 161 and the alignment common electrode 22, and the application of different voltages may change the orientation of the liquid crystal molecules, thereby adjusting the transmittance of light and displaying an image.
In other embodiments, an excellent resist layer 17 is prepared on one side of the array substrate 1 for forming the color of each sub-pixel Px. The array substrate 1 adopts a DBS (data BM Less, black matrix) architecture, and a transparent shielding common electrode 162 is disposed on the side of the array substrate 1 to replace the black matrix BM above the data line 141.
As shown in fig. 2, the counter substrate 2 includes a counter substrate 21 and a counter common electrode 22 provided on the counter substrate 21. A transparent shielding common electrode 162 is disposed on one side of the array substrate 1 to shield the electric field above the data line 141, and the potential of the shielding common electrode 162 is the same as the potential of the alignment common electrode 22 on the opposite substrate 2, so that the liquid crystal molecules corresponding to the upper side of the data line 141 are always kept in an undeflected state, and further the light shielding effect is achieved.
When the thin film transistor of the array substrate 1 is turned on by a signal applied to the gate electrode 123, a signal applied to the data line 141 is applied to the pixel electrode 161. Thereby, an electric field of a predetermined intensity is generated between the pixel electrode 161 and the alignment common electrode 22, and the application of different voltages may change the orientation of the liquid crystal molecules, thereby adjusting the transmittance of light and displaying an image.
The following describes in detail the specific structure of the array substrate provided in each embodiment of the present application with reference to the accompanying drawings.
Example 1
Fig. 3 is a top view of an array substrate according to an embodiment of the disclosure; FIG. 4 illustrates a cross-sectional view of the array substrate of FIG. 3 along the B-B direction; fig. 5 shows a partially enlarged structural schematic view of the region C in fig. 3; fig. 6 shows a cross-section of fig. 5 in the direction D-D.
As shown in fig. 3 and 4, the array substrate 1 includes a pixel area AA and a peripheral routing area NA located at least one side of the pixel area AA, and the array substrate 1 includes a first metal layer 12, a gate insulating layer 13, a second metal layer 14, an interlayer insulating layer 15, and a transparent conductive layer 16 sequentially formed on a substrate 11.
The first metal layer 12 is formed with a plurality of scan lines 121, the second metal layer 14 is formed with a plurality of data lines 141, the transparent conductive layer 16 includes a plurality of shielding common electrodes 162 located in the pixel region AA and shielding metal strips 163 located in the peripheral wiring region NA and electrically connected to the plurality of shielding common electrodes 162, and the front projection of the shielding common electrodes 162 on the substrate 11 covers the front projection of the data lines 141 on the substrate 11, and the shielding metal strips 163 are electrically connected to the first metal layer 12 through the first vias H1.
In the peripheral routing area NA, the shielding metal stripe 163 includes a plurality of sub-metal blocks 1631 that are segmented and spaced apart, the sub-metal blocks 1631 are electrically connected to the shielding common electrode 162, and a space between two adjacent sub-metal blocks 1631 exposes an area of the interlayer insulating layer 15 covering the data line 141.
As shown in fig. 5, in the peripheral routing area NA, only the interlayer insulating layer 15 is present between the data line 141 of the second metal layer 14 and the shielding metal strip 163 of the transparent conductive layer 16, and the thickness of the interlayer insulating layer 15 is usually only 2000 μm, which results in a small distance between the data line 141 and the shielding metal strip 163, large capacitance, and easy accumulation of a large amount of static charges, which may generate a large current to burst a circuit, and cause LCD display anomalies and other adverse phenomena.
Therefore, in the array substrate 1 provided in this embodiment of the present application, the shielding metal strips 163 of the peripheral routing area NA are arranged in segments to form a plurality of sub-metal blocks 1631 distributed at intervals, and the interval between two adjacent sub-metal blocks 1631 exposes the area of the interlayer insulating layer 15 covering the data line 141, so that part of the shielding metal strips 163 covering the data line 141 is removed, static charges in a circuit can be reduced, the circuit is prevented from being blasted due to large current generated by discharging of a large amount of static charges, and the reliability of the array substrate 1 is improved.
Further, in order to electrically connect the sub-metal block 1631 of the peripheral routing area NA with the shielding common electrode 162 of the display area AA, the sub-metal block 1631 is provided with a wire 1632 extending toward the pixel area AA, and the sub-metal block 1631 is electrically connected with the shielding common electrode 162 through the wire 1632.
In some embodiments, the conductive lines 1632 include a first conductive line a, a second conductive line b, and a third conductive line c electrically connected to each other, the first conductive line a is parallel to the data line 141 and electrically connected to the sub-metal block 1631, the second conductive line b and the third conductive line c are symmetrically disposed at both sides of the first conductive line a, and the second conductive line b and the third conductive line c are electrically connected to the shielding common electrode 162 at both sides of the sub-metal block 1631, respectively.
The lead 1632 is divided into a second lead b and a third lead c, and the two branches are respectively and electrically connected with the two adjacent shielding public electrodes 162, so that when one branch lead is in poor contact, the other branch lead can be electrically connected with the shielding public electrode 162, and the reliability of the array substrate 1 is improved.
Further, as described above, the shielding metal bar 163 is electrically connected to the first metal layer 12 through the first via H1. The front projection of the first via H1 on the substrate 11 is disposed adjacent to the front projection of the sub-metal block 1631 on the substrate 11, and the first via H1 penetrates each film layer between the transparent conductive layer 16 and the first metal layer 12.
In some embodiments, as shown in fig. 4, the first metal layer 12 is further formed with a common electrode line 122 and a gate electrode 123 of the thin film transistor, the second metal layer 14 is further formed with a source electrode 142 and a drain electrode 143 of the thin film transistor, a second via H2 is disposed on each film layer between the transparent conductive layer 16 and the first metal layer 12, and an orthographic projection of the second via H2 on the substrate 11 is disposed adjacent to an orthographic projection of the source electrode 142 or the drain electrode 143 on the substrate 11.
Either one of the source electrode 142 and the drain electrode 143 is electrically connected to the data line 141, and the other is exposed from the second via H2, so that the pixel electrode 161 is electrically connected to the source electrode 142 or the drain electrode 143 and the common electrode line 122 through the second via H2, respectively. By this arrangement, the structure and the manufacturing process of the array substrate 1 can be simplified, and the thickness of the liquid crystal display panel can be further reduced.
In addition, the transparent conductive layer 16 further includes a plurality of pixel electrodes 161 disposed in the pixel area AA and spaced apart from each other, and the pixel electrodes 161 are not connected to the shielding common electrode 162. The pixel electrode 161 is electrically connected to a corresponding thin film transistor, and the thin film transistor is also electrically connected to a corresponding scan line 121 and data line 141. The plurality of scan lines 121 and the plurality of data lines 141 cross each other to define a plurality of sub-pixels Px, which are in one-to-one correspondence with the plurality of pixel electrodes 161.
In some embodiments, the array substrate 1 further includes a planarization layer (not shown) formed over the thin film transistor and the data line 141 and covering the thin film transistor and the data line 141, and an alignment film (not shown) over the planarization layer and over the pixel electrodes 161.
Accordingly, as shown in fig. 1, an excellent resist layer 17 is prepared on the side of the docking substrate 2 of the liquid crystal display panel for forming the color of each sub-pixel Px. The liquid crystal display panel controls the rotation of the liquid crystal molecules of the liquid crystal layer 3 by applying a driving voltage to the pixel electrode 161 of the array substrate 1 and the alignment common electrode 22 of the opposite substrate 2, so as to refract the light provided by the backlight module to generate a picture.
Example two
Fig. 6 is a top view of an array substrate according to a second embodiment of the present application, fig. 7 is a schematic view of a partial enlarged structure of a region E in fig. 6, and fig. 8 is a cross-sectional view of fig. 7 along a direction F-F.
Referring to fig. 6 to 8, the embodiment of the present application further provides an Array substrate 1, which is similar to the structure of the Array substrate 1 described in the first embodiment, and is different in that the Array substrate 1 adopts a COA (Color filter on Array) architecture, that is, a Color blocking layer 17 is disposed on one side of the Array substrate 1 for forming the Color of each sub-pixel Px. Accordingly, the structure of the docking substrate 2 is shown in fig. 2.
Specifically, the array substrate 1 further includes a color resist layer 17, where the color resist layer 17 is disposed between the interlayer insulating layer 15 and the transparent conductive layer 16, the color resist layer 17 includes a plurality of color resist units 171 corresponding to the plurality of pixel electrodes 161 one by one, the color resist units 171 are in a stripe structure disposed parallel to the data lines 141, and orthographic projections of overlapping regions of two adjacent color resist units 171 on the substrate 11 cover orthographic projections of the data lines 141 on the substrate 11.
Further, the color resist unit 171 includes a first photoresist segment 171a located in the pixel area AA and a second photoresist segment 171b located in the peripheral routing area NA.
The orthographic projection of the shielding common electrode 162 on the substrate 11 covers the orthographic projection of the overlapping area of the adjacent two first photoresist segments 171a on the substrate 11.
The orthographic projection of the sub-metal block 1631 onto the substrate base plate 11 covers the orthographic projection of the corresponding second photoresist segment 171b onto the substrate base plate 11.
As shown in fig. 7 and 8, the shielding metal strips 163 of the peripheral routing area NA are arranged in segments as a plurality of sub-metal blocks 1631 distributed at intervals, and the interval between two adjacent sub-metal blocks 1631 exposes the area where the interlayer insulating layer 15 covers the data line 141, and part of the shielding metal strips 163 covering the data line 141 is removed, so that static charges in the circuit can be reduced, and the circuit is prevented from being burst due to large current generated by discharge of a large amount of static charges.
Meanwhile, the interlayer insulating layer 15 and the color resist layer 17 are arranged between the data line 141 of the second metal layer 14 and the sub-metal block 1631 of the transparent conductive layer 16, and compared with the technical scheme that only the interlayer insulating layer 15 is arranged between the second metal layer 14 and the transparent conductive layer 16 in the related art, the thickness between the two is increased, and the distance between the data line 141 and the sub-metal block 1631 is increased, so that static charges in a circuit can be further reduced, the circuit is prevented from being blasted due to large current generated by discharge of a large amount of static charges, and the reliability of the array substrate and the display effect of the liquid crystal display panel are further improved.
In some embodiments, the plurality of color resist units 171 includes a red color resist unit 171, a green color resist unit 171, and a blue color resist unit 171. In other embodiments, the plurality of color resist units 171 may further include color resist units of other colors, which are not described herein again according to specific design requirements.
According to the array substrate 1 provided by the embodiment of the application, on one hand, the shielding metal strips 163 of the peripheral wiring area NA are arranged in a segmented mode to form the plurality of sub-metal blocks 1631 which are distributed at intervals, the interval between two adjacent sub-metal blocks 1631 exposes the interlayer insulating layer 15 to cover the area of the data line 141, on the other hand, the color resistance layer 17 is added between the data line 141 of the second metal layer 14 and the sub-metal blocks 1631 of the transparent conductive layer 16, the distance between the data line 141 and the sub-metal blocks 1631 is increased, and therefore static charges in a circuit can be further reduced, the circuit is prevented from being burst due to large current generated by a large amount of static charge discharge, and the reliability of the array substrate and the display effect of the liquid crystal display panel are further improved.
Example III
Fig. 9 is a top view of an array substrate according to a third embodiment of the present application, fig. 10 is a schematic view of a partial enlarged structure of a region G in fig. 9, and fig. 11 is a cross-sectional view of fig. 10 along H-H direction.
Referring to fig. 9 to 11, the present embodiment further provides an Array substrate 1, and the Array substrate 1 is similar to the Array substrate 1 described in the second embodiment in structure, and adopts a COA (Color-filter on Array) architecture, that is, a Color blocking layer 17 is disposed on one side of the Array substrate 1 for forming the Color of each sub-pixel Px. The difference is that the color resist layer 17 and the shielding metal bar 163 are different in structure in the peripheral display area. That is, the shielding metal strips 163 of the peripheral display area are not arranged in a segmented manner, and the color resistance layer 17 is entirely laid on the peripheral display area. Accordingly, the structure of the docking substrate 2 is shown in fig. 2.
Specifically, the array substrate includes a pixel area AA and a peripheral routing area NA located on at least one side of the pixel area AA, and the array substrate includes a first metal layer 12, a gate insulating layer 13, a second metal layer 14, an interlayer insulating layer 15, a color resist layer 17 and a transparent conductive layer 16 sequentially formed on a substrate 11.
The first metal layer 12 is formed with a plurality of scan lines 121 and a plurality of common electrode lines 122, the second metal layer 14 is formed with a plurality of data lines 141, the transparent conductive layer 16 includes a plurality of pixel electrodes 161 located in the pixel area AA and distributed at intervals, a plurality of shielding common electrodes 162, and shielding metal strips 163 located in the peripheral wiring area NA and electrically connected to the plurality of shielding common electrodes 162, the front projection of the shielding common electrodes 162 on the substrate 11 covers the front projection of the data lines 141 on the substrate 11, the shielding metal strips 163 are electrically connected to the first metal layer 12 through the first vias H1, and the pixel electrodes 161 are electrically connected to the common electrode lines 122 through the second vias H2.
In the peripheral routing area NA, the color resist layer 17 includes a plurality of color resist units 171 corresponding to the pixel electrodes 161 one by one, and the color resist units 171 include a first photoresist section 171a located in the pixel area AA and a second photoresist section 171b located in the peripheral routing area NA.
The orthographic projection of the shielding common electrode 162 on the substrate 11 covers the orthographic projection of the overlapping area of the adjacent two first photoresist segments 171a on the substrate 11.
The orthographic projection of the shielding metal bar 163 on the substrate 11 covers the orthographic projection of the second photoresist segment 171b on the substrate 11.
In this embodiment of the present application, since the interlayer insulating layer 15 and the color resist layer 17 are disposed between the data line 141 of the second metal layer 14 and the shielding metal strip 163 of the transparent conductive layer 16, compared with the technical scheme that only the interlayer insulating layer 15 is disposed between the second metal layer 14 and the transparent conductive layer 16 in the related art, the thickness between the two layers is increased, and the distance between the data line 141 and the shielding metal strip 163 is increased, thereby reducing the electrostatic charge in the circuit, preventing the circuit from being blasted due to large current generated by discharging a large amount of electrostatic charge, and improving the reliability of the array substrate.
According to the array substrate 1 provided by the embodiment of the application, the color resistance layer 17 is added between the data line 141 of the second metal layer 14 and the transparent conductive layer 16, so that the distance between the data line 141 and the shielding metal strip 163 is increased, static charges in a circuit can be reduced, the circuit is prevented from being burst due to large current generated by discharging a large amount of static charges, and the reliability of the array substrate is improved.
It can be understood that the technical solution of the array substrate 1 provided In the embodiments of the present application may be widely used for various liquid crystal display panels, such as a TN (Twisted Nematic) display panel, an IPS (In-plane switching) display panel, a VA (vertical alignment) display panel, a MVA (Multi-Domain Vertical Alignment, multi-quadrant vertical alignment) display panel.
It should be readily understood that the terms "on … …", "above … …" and "above … …" in this application should be interpreted in the broadest sense such that "on … …" means not only "directly on something" but also includes the meaning of "on something" with intermediate features or layers therebetween, and "above … …" or "above … …" includes the meaning of "not only" on something "or" above "but also" above "or" above "without intermediate features or layers therebetween (i.e., directly on something).
The term "substrate base" as used herein refers to a material to which subsequent layers of material are added. The substrate itself may be patterned. The material added atop the substrate base plate may be patterned or may remain unpatterned. In addition, the substrate base may comprise a wide range of materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate base plate may be made of a non-conductive material (e.g., glass, plastic, or sapphire wafer, etc.).
The term "layer" as used herein may refer to a portion of material that includes regions having a certain thickness. The layer may extend over the entire underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Further, the layer may be a region of a continuous structure, either homogenous or non-homogenous, having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of lateral planes at the top and bottom surfaces. The layers may extend laterally, vertically and/or along a tapered surface. The substrate base may be a layer, may include one or more layers therein, and/or may have one or more layers located thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (within which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. An array substrate for a liquid crystal display panel, the array substrate comprises a pixel area and a peripheral wiring area positioned on at least one side of the pixel area, and the array substrate comprises a first metal layer, a gate insulating layer, a second metal layer, an interlayer insulating layer and a transparent conductive layer which are sequentially formed on a substrate;
the first metal layer is formed with a plurality of scanning lines, the second metal layer is formed with a plurality of data lines, the transparent conductive layer comprises a plurality of shielding public electrodes positioned in the pixel area and shielding metal strips positioned in the peripheral wiring area and electrically connected with the shielding public electrodes, the orthographic projection of the shielding public electrodes on the substrate covers the orthographic projection of the data lines on the substrate, the shielding metal strips are electrically connected with the first metal layer through first through holes,
in the peripheral wiring area, the shielding metal strip comprises a plurality of sub-metal blocks which are segmented and distributed at intervals, the sub-metal blocks are electrically connected with the shielding public electrode, and the interval between two adjacent sub-metal blocks exposes the area of the interlayer insulating layer covering the data line.
2. The array substrate of claim 1, wherein the sub-metal block is provided with a wire extending toward the pixel region, the sub-metal block being electrically connected to the shielding common electrode through the wire.
3. The array substrate of claim 2, wherein the conductive lines include a first conductive line, a second conductive line, and a third conductive line electrically connected to each other, the first conductive line is parallel to the data line and electrically connected to the sub-metal block, the second conductive line and the third conductive line are symmetrically disposed at both sides of the first conductive line, and the second conductive line and the third conductive line are electrically connected to the shielding common electrode at both sides of the sub-metal block, respectively.
4. The array substrate according to claim 1, wherein the transparent conductive layer further comprises a plurality of pixel electrodes located in the pixel region and spaced apart from each other, and the pixel electrodes are not connected to the shielding common electrode;
the array substrate further comprises a color resistance layer, the color resistance layer is arranged between the interlayer insulating layer and the transparent conducting layer, the color resistance layer comprises a plurality of color resistance units corresponding to the pixel electrodes one by one, the color resistance units are of strip-shaped structures parallel to the data lines, and orthographic projections of overlapping areas of two adjacent color resistance units on the substrate cover orthographic projections of the data lines on the substrate.
5. The array substrate of claim 4, wherein the color resist unit comprises a first photoresist segment in the pixel region and a second photoresist segment in the peripheral wiring region;
orthographic projection of the shielding common electrode on the substrate covers orthographic projection of overlapping areas of two adjacent first light resistance sections on the substrate;
the orthographic projection of the sub-metal block on the substrate base plate covers the orthographic projection of the corresponding second photoresist segment on the substrate base plate.
6. The array substrate of claim 4, wherein the plurality of color resist cells comprises a red color resist cell, a green color resist cell, and a blue color resist cell.
7. The array substrate of claim 1, wherein the orthographic projection of the first via on the substrate is disposed adjacent to the orthographic projection of the sub-metal block on the substrate, and the first via penetrates each film layer between the transparent conductive layer and the first metal layer.
8. The array substrate according to claim 1, wherein the first metal layer is further formed with a common electrode line and a gate electrode of a thin film transistor, the second metal layer is further formed with a source electrode and a drain electrode of the thin film transistor, a second via hole is disposed on each film layer between the transparent conductive layer and the first metal layer, and an orthographic projection of the second via hole on the substrate is disposed adjacent to an orthographic projection of the source electrode or the drain electrode on the substrate;
either one of the source and drain electrodes is electrically connected to the data line, and the other is exposed from the second via hole, so that the pixel electrode is electrically connected to the source or drain electrode and the common electrode line through the second via hole, respectively.
9. An array substrate for a liquid crystal display panel, the array substrate comprises a pixel area and a peripheral wiring area positioned on at least one side of the pixel area, and the array substrate comprises a first metal layer, a gate insulating layer, a second metal layer, an interlayer insulating layer, a color resistance layer and a transparent conductive layer which are sequentially formed on a substrate;
the first metal layer is formed with a plurality of scanning lines, the second metal layer is formed with a plurality of data lines, the transparent conductive layer comprises a plurality of pixel electrodes, a plurality of shielding public electrodes and shielding metal strips, the pixel electrodes are arranged in the pixel area and distributed at intervals, the shielding metal strips are arranged in the peripheral wiring area and electrically connected with the shielding public electrodes, the orthographic projection of the shielding public electrodes on the substrate covers the orthographic projection of the data lines on the substrate, the shielding metal strips are electrically connected with the first metal layer through first through holes,
the color resistance layer comprises a plurality of color resistance units which are in one-to-one correspondence with the pixel electrodes in the peripheral wiring area, and the color resistance units comprise a first light resistance section positioned in the pixel area and a second light resistance section positioned in the peripheral wiring area;
orthographic projection of the shielding common electrode on the substrate covers orthographic projection of overlapping areas of two adjacent first light resistance sections on the substrate;
the orthographic projection of the shielding metal strip on the substrate plate covers the orthographic projection of the second photoresist section on the substrate plate.
10. A liquid crystal display panel, comprising:
the array substrate of any one of claims 1 to 8 or claim 9;
the butt joint substrate is arranged opposite to the array substrate;
the liquid crystal layer is arranged between the array substrate and the butt joint substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111242736.6A CN114185211B (en) | 2021-10-25 | 2021-10-25 | Array substrate and liquid crystal display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111242736.6A CN114185211B (en) | 2021-10-25 | 2021-10-25 | Array substrate and liquid crystal display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114185211A CN114185211A (en) | 2022-03-15 |
| CN114185211B true CN114185211B (en) | 2023-06-30 |
Family
ID=80539871
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111242736.6A Active CN114185211B (en) | 2021-10-25 | 2021-10-25 | Array substrate and liquid crystal display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114185211B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114883344B (en) * | 2022-04-24 | 2023-06-30 | 绵阳惠科光电科技有限公司 | Display panel and display device |
| CN115458537B (en) * | 2022-09-30 | 2024-09-10 | 厦门天马微电子有限公司 | Array substrate, preparation method thereof and display panel |
| WO2024182924A1 (en) * | 2023-03-03 | 2024-09-12 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method therefor and display apparatus |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN207424484U (en) * | 2017-11-27 | 2018-05-29 | 京东方科技集团股份有限公司 | A kind of array substrate and display device |
| CN110082970A (en) * | 2019-04-09 | 2019-08-02 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and display device |
| CN111025803A (en) * | 2019-12-12 | 2020-04-17 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
| CN111090199A (en) * | 2020-01-08 | 2020-05-01 | 深圳市华星光电半导体显示技术有限公司 | TFT array substrate and display panel |
-
2021
- 2021-10-25 CN CN202111242736.6A patent/CN114185211B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN207424484U (en) * | 2017-11-27 | 2018-05-29 | 京东方科技集团股份有限公司 | A kind of array substrate and display device |
| CN110082970A (en) * | 2019-04-09 | 2019-08-02 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and display device |
| CN111025803A (en) * | 2019-12-12 | 2020-04-17 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
| CN111090199A (en) * | 2020-01-08 | 2020-05-01 | 深圳市华星光电半导体显示技术有限公司 | TFT array substrate and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114185211A (en) | 2022-03-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9417498B2 (en) | Liquid crystal display | |
| KR100831229B1 (en) | A liquid crystal display having high aperture ratio | |
| CN114185211B (en) | Array substrate and liquid crystal display panel | |
| TWI424221B (en) | Liquid crystal display and panel therefor | |
| KR100612994B1 (en) | A liquid crystal display and a substrate for the same | |
| EP1979784B1 (en) | Liquid crystal display apparatus using an electric field substantially parallel to the substrate surfaces | |
| JP4162890B2 (en) | Liquid crystal display | |
| KR100966452B1 (en) | In plane switching mode liquid crystal display device and fabrication method thereof | |
| KR100908357B1 (en) | Transverse electric field liquid crystal display panel | |
| US8767147B2 (en) | Liquid crystal display wherein a first light blocking portion and a first colored portion extends generally along a gate line and generally covers the gate line and a thin film transistor | |
| KR20020069168A (en) | In-plane switching mode active matrix type liquid crystal display device and method of fabricating the same | |
| KR20020063498A (en) | Liquid crystal display device | |
| US20150022766A1 (en) | Liquid crystal display | |
| KR101807729B1 (en) | Liquid crystal display | |
| CN100451782C (en) | Liquid crystal display, thin film diode panel, and manufacturing method of the same | |
| US9846331B2 (en) | Liquid crystal display | |
| KR20050014414A (en) | Multi-domain liquid crystal display including the same | |
| CN114299894B (en) | Array substrate and liquid crystal display panel | |
| US9400409B2 (en) | Liquid crystal display | |
| US6822716B2 (en) | In-plane switching liquid crystal display with an alignment free structure and method of using back exposure to form the same | |
| KR20040047400A (en) | In-Plane Switching Mode Liquid Crystal Display Device and A method for manufacturing the same | |
| JP4441507B2 (en) | Liquid crystal display | |
| EP4246505A1 (en) | Array substrate and liquid crystal display panel | |
| KR100816331B1 (en) | Vertically aligned mode liquid crystal display | |
| JP4750072B2 (en) | Manufacturing method of liquid crystal display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |