KR20000055377A - Manufacturing method for mos transistor - Google Patents
Manufacturing method for mos transistor Download PDFInfo
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- KR20000055377A KR20000055377A KR1019990003961A KR19990003961A KR20000055377A KR 20000055377 A KR20000055377 A KR 20000055377A KR 1019990003961 A KR1019990003961 A KR 1019990003961A KR 19990003961 A KR19990003961 A KR 19990003961A KR 20000055377 A KR20000055377 A KR 20000055377A
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- oxide film
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000000151 deposition Methods 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 238000000059 patterning Methods 0.000 claims abstract description 8
- 150000002500 ions Chemical class 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 238000000034 method Methods 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 239000013078 crystal Substances 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract 6
- 238000007254 oxidation reaction Methods 0.000 abstract 6
- 230000001105 regulatory effect Effects 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 모스 트랜지스터 제조방법에 관한 것으로, 특히 소자분리영역을 형성하지 않아 공정단계를 감소시키며, 집적도를 향상시키는데 적당하도록 한 모스 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MOS transistor, and more particularly, to a method of manufacturing a MOS transistor, in which a device isolation region is not formed, thereby reducing process steps and improving integration.
도1a 내지 도1d는 종래 모스 트랜지스터의 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)에 필드산화막(2)을 형성하여, 소자형성영역을 정의하고, 그 소자형성영역의 상부에 게이트산화막과 다결정실리콘을 순차적으로 증착한 후, 사진식각공정을 통해 상기 다결정실리콘과 게이트산화막을 패터닝하여 게이트(3)를 형성한 다음, 그 게이트(3)의 측면 기판(1)하부에 저농도 소스 및 드레인(4)을 형성하는 단계(도1a)와; 상기 게이트(3)가 형성된 기판(1)의 상부전면에 절연막을 증착하고, 건식식각하여 상기 게이트(3)의 측면에 측벽(5)을 형성하는 단계(도1b)와; 상기 측벽(5)의 측면 기판(1)에 불순물 이온을 주입하여 고농도 소스 및 드레인(6)을 형성하는 단계(도1c)로 구성된다.1A to 1D are cross-sectional views of a manufacturing process of a conventional MOS transistor. As shown in FIG. 1, a field oxide film 2 is formed on a substrate 1 to define an element formation region, and a gate is formed on the element formation region. After depositing an oxide film and polysilicon sequentially, a gate 3 is formed by patterning the polysilicon and the gate oxide film through a photolithography process, and then a low concentration source and Forming a drain 4 (FIG. 1A); Depositing an insulating film on the upper surface of the substrate (1) on which the gate (3) is formed and dry etching to form sidewalls (5) on the side of the gate (3); Injecting impurity ions into the side substrate 1 of the side wall 5 to form a high concentration source and drain 6 (Fig. 1C).
이하, 상기와 같이 구성된 종래 모스 트랜지스터 제조방법을 좀 더 상세히 설명한다.Hereinafter, the conventional MOS transistor manufacturing method configured as described above will be described in more detail.
먼저, 도1a에 도시한 바와 같이 기판(1)의 상부에 패드산화막과 질화막을 순차적으로 증착하고, 그 질화막을 패터닝시켜 패드산화막의 일부를 노출시킨 후, 노출된 패드산화막에 열산화막을 성장시켜, 필드산화막(2)을 형성하여, 소자가 형성될 영역을 정의하고, 그 소자형성영역간의 전기적인 절연을 실시한다.First, as illustrated in FIG. 1A, a pad oxide film and a nitride film are sequentially deposited on the substrate 1, the nitride film is patterned to expose a portion of the pad oxide film, and then a thermal oxide film is grown on the exposed pad oxide film. The field oxide film 2 is formed to define the region where the element is to be formed and to electrically insulate between the element formation regions.
그 다음, 상기 패드산화막과 질화막을 제거하여 소자형성영역인 기판(1)을 노출시킨다.Next, the pad oxide film and the nitride film are removed to expose the substrate 1, which is an element formation region.
그 다음, 도1b에 도시한 바와 같이 상기 필드산화막(2)이 형성된 기판(1)의 상부전면에 게이트산화막과 다결정실리콘을 순차적으로 증착하고, 그 다결정실리콘의 상부에 포토레지스트를 도포한 후, 노광 및 현상하여 포토레지스트 패턴을 형성한 후, 그 패턴을 식각마스크로 사용하는 식각공정으로 상기 다결정실리콘과 게이트산화막을 식각하여 게이트(3)를 형성한다.Subsequently, as shown in FIG. 1B, a gate oxide film and polysilicon are sequentially deposited on the upper surface of the substrate 1 on which the field oxide film 2 is formed, and a photoresist is applied on the polysilicon. After exposure and development to form a photoresist pattern, the polysilicon and the gate oxide film are etched by an etching process using the pattern as an etching mask to form a gate 3.
그 다음, 상기 게이트(3)의 측면 기판(1) 하부에 저농도 불순물 이온을 이온주입하여 저농도 소스 및 드레인(4)을 형성한다.Next, low concentration impurity ions are implanted into the lower side substrate 1 of the gate 3 to form the low concentration source and drain 4.
그 다음, 도1c에 도시한 바와 같이 상기 저농도 소스 및 드레인(4)과 게이트(3)가 형성된 영역의 상부전면에 질화막등의 절연막을 증착하고, 그 증착된 절연막을 건식식각하여 상기 게이트(3)의 측면 기판(1)의 상부에 게이트측벽(5)을 형성한다.Then, as shown in FIG. 1C, an insulating film such as a nitride film is deposited on the upper surface of the region where the low concentration source and drain 4 and the gate 3 are formed, and the deposited insulating film is etched dry to form the gate 3. The gate side wall 5 is formed on the side substrate 1 of FIG.
그 다음, 도1d에 도시한 바와 같이 상기 게이트측벽(5)의 측면 기판하부에 고농도 불순물을 이온주입하여 고농도 소스 및 드레인(6)을 형성한다.Then, as shown in Fig. 1D, high concentration impurities are implanted under the side substrate of the gate side wall 5 to form a high concentration source and drain 6.
상기한 바와 같이 종래 모스 트랜지스터 제조방법은 모스 트랜지스터의 형성이전에 필드산화막을 형성하여 각 소자간의 절연을 실시하고, 기판 또한 그 모스 트랜지스터의 도전형에 따라 선택적으로 사용해야 하기 때문에 특정 도전형의 웰을 형성해야 함으로써, 제조공정의 단계가 증가하는 문제점과 아울러 상기 필드산화막의 형성으로 소자의 집적도가 감소하는 문제점이 있었다.As described above, in the conventional method of manufacturing a MOS transistor, a field oxide film is formed before the formation of the MOS transistor to insulate the elements, and the substrate also needs to be selectively used according to the conductivity type of the MOS transistor. As a result of the formation, there is a problem in that the step of the manufacturing process is increased and the degree of integration of the device is reduced due to the formation of the field oxide film.
이와 같은 문제점을 감안한 본 발명은 필드산화막을 형성하지 않고, 소자간의 전기적 분리를 가능하게 하며, 기판의 도전형과 관계없이 특정 도전형의 소자를 형성할 수 있는 모스 트랜지스터 제조방법을 제공함에 그 목적이 있다.In view of the above problems, the present invention provides a method of manufacturing a MOS transistor which enables electrical separation between devices without forming a field oxide film and can form devices of a specific conductivity type regardless of the conductivity type of the substrate. There is this.
도1a 내지 도1c는 종래 모스 트랜지스터의 제조공정 수순단면도.1A to 1C are cross-sectional views illustrating a manufacturing process of a conventional MOS transistor.
도2a 내지 도2d는 본 발명 모스 트랜지스터의 제조공정 수순단면도.2A to 2D are cross-sectional views of a manufacturing process of the MOS transistor of the present invention.
***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***
1:기판2:산화막1: Substrate 2: Oxide Film
3:게이트전극4:게이트산화막3: gate electrode 4: gate oxide film
5:단결정실리콘층6:절연층5: single crystal silicon layer 6: insulating layer
7:소스 및 드레인7: Source and Drain
상기와 같은 목적은 기판의 상부에 산화막을 증착하고, 그 산화막의 상부전면에 다결정실리콘을 증착 및 패터닝하여 게이트전극을 형성한 후, 그 게이트전극과 산화막의 상부전면에 게이트산화막을 증착하는 게이트형성단계와; 상기 게이트산화막의 상부전면에 단결정실리콘을 증착하고, 그 다결정실리콘에 문턱전압조절용 불순물 이온을 이온주입하는 기판영역 형성단계와; 상기 단결정실리콘의 상부전면에 산화막을 증착하고, 패터닝하여 상기 단결정실리콘의 일부영역을 노출시키는 패턴을 형성한 후, 그 노출된 단결정실리콘에 불순물 이온을 이온주입하여 소스 및 드레인을 형성하는 소스 및 드레인 형성단계로 구성함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The purpose of the above is to form a gate electrode by depositing an oxide film on top of the substrate, and depositing and patterning polycrystalline silicon on the top surface of the oxide film, and then forming a gate oxide film on the top surface of the gate electrode and the oxide film. Steps; A substrate region forming step of depositing single crystal silicon on the upper surface of the gate oxide film and ion implanting impurity ions for adjusting the threshold voltage into the polycrystalline silicon; An oxide film is deposited on the upper surface of the single crystal silicon and patterned to form a pattern for exposing a portion of the single crystal silicon, and then a source and a drain are formed by implanting impurity ions into the exposed single crystal silicon to form a source and a drain. It is achieved by forming in a forming step, described in detail with reference to the accompanying drawings, the present invention as follows.
도2a 내지 도2d는 본 발명 모스 트랜지스터의 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 산화막(2)을 증착하고, 그 산화막(2)의 상부전면에 다결정실리콘을 증착한 후, 패터닝하여 게이트전극(3)을 형성한 다음, 그 게이트전극(3)과 산화막(2)의 상부전면에 게이트산화막(4)을 증착하는 단계(도2a)와; 상기 게이트산화막(4)의 상부전면에 단결정실리콘층(5)을 성장시키고 그 단결정실리콘층(5)에 문턱전압 조절을 위한 불순물을 주입하는 단계(도2b)와; 상기 단결정실리콘층(5)의 상부전면에 절연층(6)을 형성하고, 그 절연층(6)의 일부를 식각하여 그 하부의 단결정실리콘층(5)의 일부를 노출시키고, 그 노출된 단결정실리콘층(5)에 불순물 이온을 이온주입하여 소스 및 드레인(7)을 형성하는 단계(도2c)와; 상기 절연층(6)을 제거하는 단계(도2d)로 구성된다.2A to 2D are cross-sectional views of a manufacturing process of a MOS transistor according to an embodiment of the present invention, in which an oxide film 2 is deposited on an upper portion of a substrate 1 and polysilicon is deposited on an upper surface of the oxide film 2. Then, patterning to form a gate electrode 3, and then depositing a gate oxide film 4 on the upper surface of the gate electrode 3 and the oxide film 2 (FIG. 2A); Growing a single crystal silicon layer (5) on the upper surface of the gate oxide film (4) and injecting impurities into the single crystal silicon layer (5) for controlling the threshold voltage (FIG. 2B); The insulating layer 6 is formed on the upper surface of the single crystal silicon layer 5, and a part of the insulating layer 6 is etched to expose a part of the single crystal silicon layer 5 below the exposed single crystal. Implanting impurity ions into the silicon layer 5 to form a source and a drain 7 (FIG. 2C); The insulating layer 6 is removed (Fig. 2d).
이하, 상기와 같은 본 발명 모스 트랜지스터 제조방법을 좀 더 상세히 설명한다.Hereinafter, the method of manufacturing the MOS transistor of the present invention as described above will be described in more detail.
먼저, 도2a에 도시한 바와 같이 기판(1)의 상부에 산화막(2)을 증착한다. 이때의 기판은 실제 모스 트랜지스터의 동작에는 관여하지 않은 것으로, 특정 도전형에 제한되지 않는다.First, as shown in FIG. 2A, an oxide film 2 is deposited on the substrate 1. The substrate at this time is not involved in the actual operation of the MOS transistor, and is not limited to a specific conductivity type.
그 다음, 상기 산화막(2)의 상부전면에 다결정실리콘을 증착하고, 사진식각공정을 통해 패터닝하여 게이트전극(3)을 형성한다.Next, polysilicon is deposited on the upper surface of the oxide film 2 and patterned through a photolithography process to form a gate electrode 3.
그 다음, 상기 게이트전극(3)과 산화막(2)의 상부전면에 게이트산화막(4)을 증착한다. 이와 같은 과정에서 알수 있는 바와 같이 본 발명은 기판(1)으로 부터 순차적으로 게이트산화막과 게이트전극을 적층한 게이트를 갖는 구조가 아니며, 종래 일반적인 형상을 역전시킨 형태로 게이트를 형성한다.Next, a gate oxide film 4 is deposited on the upper surface of the gate electrode 3 and the oxide film 2. As can be seen in this process, the present invention does not have a structure in which a gate oxide film and a gate electrode are sequentially stacked from the substrate 1, and forms a gate in a form in which a conventional general shape is reversed.
그 다음, 도2b에 도시한 바와 같이 상기 게이트산화막(4)의 상부전면에 단결정실리콘층(5)을 성장시킨다. 상기 단결정실리콘층(5)은 소스 및 드레인과 채널이 형성되는 영역을 정의하는 것이며, 이때 증착된 단결정실리콘층(5)을 패터닝하여 이웃한 소자와 절연을 하게 된다. 즉, 단결정실리콘층(5)을 종래의 기판역할을 하며, 그 단결정실리콘층(5)이 식각되어 그 하부의 게이트산화막(4)이 노출되는 영역은 종래 필드산화막의 역할과 같이 인접한 소자간의 전기적인 분리를 시키는 것이다.Next, as shown in FIG. 2B, the single crystal silicon layer 5 is grown on the upper front surface of the gate oxide film 4. The single crystal silicon layer 5 defines a region where a source, a drain, and a channel are formed, and in this case, the deposited single crystal silicon layer 5 is patterned to insulate the neighboring device. That is, the single crystal silicon layer 5 serves as a conventional substrate, and the region in which the single crystal silicon layer 5 is etched and the gate oxide film 4 under the exposed portion is exposed to electricity between adjacent elements as in the role of the conventional field oxide film. It is to make a separate separation.
그 다음, 상기 성장된 단결정실리콘층(5)에 불순물 이온을 이온주입하여 모스 트랜지스터의 동작전압인 문턱전압을 설정하게 된다.Then, impurity ions are implanted into the grown single crystal silicon layer 5 to set a threshold voltage which is an operating voltage of the MOS transistor.
그 다음, 도2c에 도시한 바와 같이 상기 단결정실리콘층(5)의 상부전면에 절연층(6)을 증착한 다음, 그 절연층(6)의 상부전면에 포토레지스트(도면 미도시)를 도포하고, 노광 및 현상하여 상기 절연층(6)의 상부일부를 노출시키는 패턴을 형성한후, 그 포토레지스트 패턴을 식각마스크로 하는 식각공정으로, 상기 노출된 절연층(6)을 식각하여 상기 게이트전극(3)의 측면 상부에 위치하는 단결정실리콘층(5)의 상부를 노출시킨다.Next, as illustrated in FIG. 2C, an insulating layer 6 is deposited on the upper surface of the single crystal silicon layer 5, and then a photoresist (not shown) is applied to the upper surface of the insulating layer 6. After exposure and development to form a pattern exposing a portion of the upper portion of the insulating layer 6, an etching process using the photoresist pattern as an etching mask, the exposed insulating layer 6 is etched to the gate An upper portion of the single crystal silicon layer 5 positioned on the upper side of the electrode 3 is exposed.
그 다음, 상기 포토레지스트 패턴을 제거하고, 상기 절연층(6)을 이온주입의 마스크로 사용하는 이온주입공정으로 상기 노출된 단결정실리콘층(5)에 불순물 이온을 이온주입하여 소스 및 드레인(7)을 형성한다.Subsequently, the photoresist pattern is removed and an ion implantation process using the insulating layer 6 as a mask for ion implantation implants impurity ions into the exposed single crystal silicon layer 5 so as to provide a source and a drain 7. ).
그 다음, 도2d에 도시한 바와 같이 상기 절연층(6)을 식각하여 모스 트랜지스터를 형성하게 된다.Next, as shown in FIG. 2D, the insulating layer 6 is etched to form a MOS transistor.
상기한 바와 같이 본 발명은 필드산화막을 형성하지 않고, 웰을 형성할 필요가 없어 제조공정단계를 줄여 비용을 절감하는 효과와 아울러 상기 게이트의 상부측에 증착하는 단결정실리콘의 패터닝을 통해 필드산화막의 역할인 소자간의 분리를 실시하여 필드산화막보다 작은 영역을 사용하며 동일한 효과를 나타내어, 집적도를 향상시키는 효과가 있다.As described above, the present invention does not form a field oxide film and does not need to form a well, thereby reducing the manufacturing process step and reducing the cost, as well as patterning of the field oxide film through patterning of single crystal silicon deposited on the upper side of the gate. The separation between the elements, which is a role, uses a smaller area than that of the field oxide film and has the same effect, thereby improving the degree of integration.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990003961A KR20000055377A (en) | 1999-02-05 | 1999-02-05 | Manufacturing method for mos transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990003961A KR20000055377A (en) | 1999-02-05 | 1999-02-05 | Manufacturing method for mos transistor |
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| KR20000055377A true KR20000055377A (en) | 2000-09-05 |
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1999
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