KR20010035684A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- KR20010035684A KR20010035684A KR1019990042378A KR19990042378A KR20010035684A KR 20010035684 A KR20010035684 A KR 20010035684A KR 1019990042378 A KR1019990042378 A KR 1019990042378A KR 19990042378 A KR19990042378 A KR 19990042378A KR 20010035684 A KR20010035684 A KR 20010035684A
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- gate oxide
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- 238000004519 manufacturing process Methods 0.000 title abstract description 14
- 239000004065 semiconductor Substances 0.000 title abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 32
- 150000004767 nitrides Chemical class 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 16
- 150000002500 ions Chemical class 0.000 claims abstract description 13
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 229920005591 polysilicon Polymers 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 4
- 238000005530 etching Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- -1 boron ions Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 고집적 디램의 셀 트랜지스터 게이트 측벽을 다결정실리콘으로 형성하여 단채널효과의 방지 및 리프레시 특성을 향상시키는데 적당하도록 한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a cell transistor gate sidewall of a highly integrated DRAM is formed of polysilicon to be suitable for preventing short channel effects and improving refresh characteristics.
도1a 내지 도1c는 종래 반도체 소자의 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 문턱전압 조절용 불순물을 이온주입하여 문턱전압조절영역(2)을 형성한 후, 그 문턱전압조절영역(2)이 형성된 기판(1)의 상부에 게이트산화막(3)과 다결정실리콘(4)을 순차적으로 증착하는 단계(도1a)와; 사진식각공정을 통해 상기 다결정실리콘(4)을 패터닝하여 게이트 전극을 형성하고, 그 다결정실리콘(4)의 측면 기판 하부에 불순물 이온을 이온주입하여 소스 및 드레인(5)을 형성하는 단계(도1b)와; 상기 구조의 상부전면에 질화막 또는 산화막을 증착하고, 이를 이방성식각하여 측벽(6)을 형성하는 단계(도1c)로 구성된다.1A to 1C are cross-sectional views of a manufacturing process of a conventional semiconductor device. As shown in FIG. 1, the threshold voltage adjusting region 2 is formed by ion implanting impurities for adjusting the threshold voltage on an upper portion of the substrate 1. Sequentially depositing a gate oxide film 3 and a polysilicon 4 on the substrate 1 on which the voltage regulation region 2 is formed (Fig. 1A); Patterning the polysilicon 4 through a photolithography process to form a gate electrode, and implanting impurity ions into the lower side substrate of the polysilicon 4 to form a source and a drain 5 (FIG. 1B) )Wow; And depositing a nitride film or an oxide film on the upper surface of the structure and anisotropically etching it to form sidewalls 6 (FIG. 1C).
이하, 상기와 같이 구성된 종래 반도체 소자 제조방법을 좀 더 상세히 설명한다.Hereinafter, a conventional semiconductor device manufacturing method configured as described above will be described in more detail.
먼저, 도1a에 도시한 바와 같이 P형의 기판(1)에 붕소이온을 소정의 깊이로 이온주입하여 셀 트랜지스터의 문턱전압을 조절하는 문턱전압조절영역(2)을 형성한다.First, as shown in FIG. 1A, a threshold voltage regulating region 2 for adjusting a threshold voltage of a cell transistor is formed by implanting boron ions into a P-type substrate 1 to a predetermined depth.
그 다음, 상기 기판(1)의 상부에 게이트산화막(3)과 다결정실리콘(4)을 순차적으로 증착한다.Next, the gate oxide film 3 and the polysilicon 4 are sequentially deposited on the substrate 1.
그 다음, 도1b에 도시한 바와 같이 상기 다결정실리콘(4)의 상부에 포토레지스트(도면 미도시)를 도포하고, 노광 및 현상하여 게이트 패턴을 형성한 후, 그 패턴이 형성된 포토레지스트를 식각마스크로 사용하는 식각공정으로 상기 다결정실리콘(4)을 식각하여 게이트 전극을 형성한다.Then, as shown in FIG. 1B, a photoresist (not shown) is applied on the polysilicon 4, exposed and developed to form a gate pattern, and then the photoresist on which the pattern is formed is etched. The polysilicon 4 is etched by an etching process to form a gate electrode.
그 다음, 상기 게이트 전극인 잔존하는 다결정실리콘(4)의 측면 기판(1)하부에 인 또는 비소이온을 이온주입하여 소스 및 드레인(5)을 형성한다.Then, phosphorus or arsenic ions are ion implanted under the side substrate 1 of the remaining polysilicon 4 that is the gate electrode to form a source and a drain 5.
그 다음, 도1c에 도시한 바와 같이 상기 구조의 상부전면에 산화막 또는 질화막을 증착하고, 그 증착된 산화막 또는 질화막을 이방성 식각하여 상기 게이트전극의 측면에 측벽(6)을 형성하여 고집적 디램에서 사용하는 셀트랜지스터를 제조한다.Next, as shown in FIG. 1C, an oxide film or nitride film is deposited on the upper surface of the structure, and the sidewall 6 is formed on the side of the gate electrode by anisotropically etching the deposited oxide film or nitride film to be used in a highly integrated DRAM. To manufacture a cell transistor.
그러나, 상기와 같은 종래 반도체 소자의 제조방법은 게이트전극을 형성한 후 이온주입 및 열처리를 통해 소스 및 드레인을 형성함으로써, 그 소스 및 드레인이 게이트전극의 측면 하부 기판영역으로 확산되어 단채널효과를 발생시키는 문제점과 아울러 기판의 전면에 문턱전압조절용 이온을 주입함으로써 소스 및 드레인과 접하는 게이트 측부에서 전계가 증가하여 디램의 리프레시 특성이 열화되며, 공핍층 폭의 감소에 의한 비트라인과의 접속부에서의 커패시턴스가 증가하여 디램의 특성을 열화시키는 문제점이 있었다.However, in the conventional method of manufacturing a semiconductor device as described above, a source and a drain are formed through ion implantation and heat treatment after the gate electrode is formed, and the source and drain are diffused to the lower substrate region of the side of the gate electrode, thereby providing a short channel effect. In addition to the problem that occurs, by injecting the ions for the threshold voltage on the front surface of the substrate, the electric field increases at the gate side contacting the source and drain, deteriorating the refresh characteristics of the DRAM, and at the connection portion with the bit line due to the reduction of the depletion layer width There is a problem that the capacitance is increased to deteriorate the characteristics of the DRAM.
이와 같은 문제점을 감안한 본 발명은 단채널효과의 발생을 억제함과 아울러 디램의 리프레시 특성을 향상시킬 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.In view of the above problems, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of suppressing occurrence of short channel effects and improving refresh characteristics of a DRAM.
도1a 내지 도1c는 종래 반도체 소자의 제조공정 수순단면도.1A to 1C are cross-sectional views of a manufacturing process of a conventional semiconductor device.
도2a 내지 도2d는 본 발명 반도체 소자의 제조공정 수순단면도.2A to 2D are cross-sectional views of a manufacturing process of the semiconductor device of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
11:기판 12:게이트산화막11: Substrate 12: Gate oxide film
13:다결정실리콘 14:문턱전압조절영역13: Polycrystalline silicon 14: Threshold voltage control area
15:게이트전극 16:다결정실리콘 측벽15: gate electrode 16: polycrystalline silicon sidewall
17:소스 및 드레인17: source and drain
상기와 같은 목적은 기판의 상부에 게이트산화막과 질화막을 순차적으로 증착한 후, 그 질화막을 패터닝하여 상기 게이트산화막의 일부영역을 노출시키는 단계와; 상기 노출된 게이트산화막을 통해 불순물 이온을 이온주입하여 그 노출된 게이트산화막의 하부기판영역에 문턱전압조절영역을 형성하는 단계와; 상기 구조의 전면에 다결정실리콘을 증착하고, 평탄화하여 상기 질화막이 식각된 영역에 위치하는 게이트전극을 형성하는 단계와; 상기 질화막을 모두 제거하고, 그 게이트전극의 측면에 다결정실리콘 측벽을 형성하는 단계와; 불순물 이온주입공정을 통해 상기 다결정실리콘 측벽의 측면 기판하부에 소스 및 드레인을 형성하는 단계로 구성함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is to sequentially deposit a gate oxide film and a nitride film on the substrate, and then pattern the nitride film to expose a portion of the gate oxide film; Implanting impurity ions through the exposed gate oxide film to form a threshold voltage regulation region in the lower substrate region of the exposed gate oxide film; Depositing and planarizing polycrystalline silicon on the entire surface of the structure to form a gate electrode positioned in an area where the nitride film is etched; Removing the nitride film and forming sidewalls of polycrystalline silicon on the side of the gate electrode; It is achieved by forming a source and a drain under the side substrate of the polysilicon sidewall through the impurity ion implantation process, which will be described in detail with reference to the accompanying drawings.
도2a 내지 도2d는 본 발명 반도체 소자 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(11)의 상부전면에 게이트산화막(12)과 질화막(13)을 순차적으로 식각한 후, 사진식각공정을 통해 상기 질화막(13)의 일부를 식각하여 그 하부의 게이트산화막(12)을 노출시킨 후, 그 노출된 게이트산화막(12)의 하부 기판(11)에 문턱전압 조절용 불순물 이온을 이온주입하여 문턱전압조절영역(14)을 형성하는 단계(도2a)와; 상기 구조의 상부전면에 다결정실리콘을 증착하고, 증착된 다결정실리콘을 평탄화하여 상기 질화막(13)의 식각영역 내에 위치하는 게이트전극(15)을 형성하는 단계(도2c)와; 선택적 식각공정으로 상기 질화막(13)을 제거하는 단계(도2c)와; 상기 구조의 상부전면에 다결정실리콘을 증착하고, 증착된 다결정실리콘을 이방성식각하여 상기 게이트전극(15)의 측면에 다결정실리콘 측벽(16)을 형성한 후, 불순물 이온주입공정을 통해 상기 다결정실리콘 측벽(16)의 측면 기판하부에 소스 및 드레인(17)을 형성하는 단계(도2d)로 구성된다.2A to 2D are cross-sectional views of a semiconductor device manufacturing process according to an embodiment of the present invention. After the gate oxide film 12 and the nitride film 13 are sequentially etched on the upper surface of the substrate 11, a photolithography process is performed. A portion of the nitride film 13 is etched to expose the gate oxide film 12 thereunder, and then ion implantation of impurity ions for adjusting the threshold voltage is performed on the lower substrate 11 of the exposed gate oxide film 12. Forming an adjustment region 14 (FIG. 2A); Depositing polysilicon on the upper surface of the structure and planarizing the deposited polysilicon to form a gate electrode 15 positioned in an etching region of the nitride film 13 (FIG. 2C); Removing the nitride film 13 by a selective etching process (FIG. 2C); After depositing polysilicon on the upper surface of the structure, and anisotropically etching the deposited polysilicon to form a polysilicon sidewall 16 on the side of the gate electrode 15, the polysilicon sidewall through an impurity ion implantation process Forming a source and a drain 17 under the side substrate (16) (FIG. 2D).
이하, 상기와 같은 본 발명 반도체 소자 제조방법을 좀 더 상세히 설명한다.Hereinafter, a method of manufacturing the semiconductor device of the present invention as described above will be described in more detail.
먼저, 도2a에 도시한 바와 같이 기판(11)의 상부전면에 게이트산화막(12)을 증착하고, 그 증착된 게이트산화막(12)의 상부에 질화막(13)을 증착한다.First, as shown in FIG. 2A, the gate oxide film 12 is deposited on the upper surface of the substrate 11, and the nitride film 13 is deposited on the deposited gate oxide film 12.
그 다음, 상기 질화막(13)의 상부에 포토레지스트(도면 미도시)를 도포하고 노광 및 현상하여 상기 질화막(13)의 일부영역을 노출시키는 패턴을 형성한다. 이때, 노출되는 질화막(13)의 일부영역은 게이트전극이 위치할 영역과 동일하다.Next, a photoresist (not shown) is applied on the nitride film 13 to expose and develop a pattern to expose a partial region of the nitride film 13. In this case, the partial region of the nitride film 13 exposed is the same as the region where the gate electrode is to be located.
그 다음, 상기 노출된 질화막(13)을 선택적으로 식각하여 그 하부의 게이트산화막(12)을 노출시킨다.Thereafter, the exposed nitride film 13 is selectively etched to expose the gate oxide film 12 thereunder.
그 다음, 상기 노출된 게이트산화막(12)을 이온주입버퍼로 사용하는 이온주입공정으로 불순물 이온을 이온주입하여 상기 노출된 게이트산화막(12)의 하부 기판(11)영역에 문턱전압조절영역(14)을 형성한다. 이때, 문턱전압조절영역(14)을 형성하는 과정은 질화막(13)을 마스크로 사용하기 때문에 기판(11)의 전영역에 불순물 이온이 주입되는 것을 방지하고, 채널영역에만 불순물 이온을 주입하기 때문에 소스 및 드레인과 게이트가 접하는 부분에서의 전계의 발생을 줄일수 있으며, 비트라인과의 접속면의 커패시턴스도 줄일 수 있게 된다.Next, an ion implantation process using the exposed gate oxide film 12 as an ion implantation buffer ion implants impurity ions into the lower substrate 11 region of the exposed gate oxide film 12. ). In this case, since the process of forming the threshold voltage regulating region 14 uses the nitride film 13 as a mask, the impurity ions are prevented from being injected into the entire region of the substrate 11 and the impurity ions are implanted only into the channel region. It is possible to reduce the generation of the electric field at the portion where the source, the drain and the gate contact, and to reduce the capacitance of the connection surface with the bit line.
그 다음, 도2b에 도시한 바와 같이 상기 구조의 상부전면에 다결정실리콘을 증착하고, 화학적 기계적 연마 방법등의 평탄화방법을 사용하여 상기 증착된 다결정실리콘을 평탄화하여 상기 질화막(13)이 식각된 영역에 위치하는 게이트전극(15)을 형성하게 된다.Next, as shown in FIG. 2B, polycrystalline silicon is deposited on the upper surface of the structure, and the deposited polycrystalline silicon is planarized using a planarization method such as a chemical mechanical polishing method to etch the nitride film 13. A gate electrode 15 positioned at is formed.
그 다음, 도2c에 도시한 바와 같이 습식식각공정을 통해 상기 질화막(13)을 선택적으로 제거한다.Next, as illustrated in FIG. 2C, the nitride film 13 is selectively removed through a wet etching process.
그 다음, 도2d에 도시한 바와 같이 상기 구조의 상부전면에 다결정실리콘을 증착하고, 증착된 다결정실리콘을 이방성식각하여 상기 게이트전극(15)의 측면에 다결정실리콘 측벽(16)을 형성한다.Next, as shown in FIG. 2D, polysilicon is deposited on the upper surface of the structure, and the polysilicon sidewall 16 is formed on the side of the gate electrode 15 by anisotropically etching the deposited polysilicon.
그 다음, 불순물 이온주입공정을 통해 상기 다결정실리콘 측벽(16)의 측면 기판(11) 하부에 불순물 이온을 주입하고 열처리하여 소스 및 드레인(17)을 형성한다. 이와 같은 과정으로 게이트전극(15)의 하부측으로 소스 및 드레인(17)의 확산이 없으며, 이에 따라 단채널효과의 발생을 방지하게 된다.Then, impurity ions are implanted into the lower side of the side substrate 11 of the polysilicon sidewall 16 through an impurity ion implantation process and heat treated to form a source and a drain 17. In this manner, there is no diffusion of the source and drain 17 into the lower side of the gate electrode 15, thereby preventing the occurrence of a short channel effect.
상기한 바와 같이 본 발명 반도체 소자 제조방법은 문턱전압조절을 위한 불순물을 질화막을 마스크로 채널영역에만 주입되도록 하여, 기생커패시턴스의 발생을 억제하고, 소스 및 드레인과 게이트의 사이에 전계가 발생되는 것을 억제하여 리프레시 특성을 향상시킴과 아울러 게이트전극의 측면에 다결정실리콘 측벽을 형성한 후, 소스 및 드레인을 형성하여 소스 및 드레인이 게이트전극의 하부측으로 확산되는 것을 방지하여 단채널효과의 발생을 방지하는 효과가 있다.As described above, in the method of manufacturing a semiconductor device of the present invention, the impurity for controlling the threshold voltage is injected into the channel region using a nitride film as a mask to suppress the generation of parasitic capacitance and to generate an electric field between the source, the drain, and the gate. By suppressing to improve the refresh characteristics and to form polysilicon sidewalls on the side of the gate electrode, the source and drain are formed to prevent the source and drain from diffusing to the lower side of the gate electrode to prevent the occurrence of short channel effect It works.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100700204B1 (en) * | 2005-07-18 | 2007-03-27 | (주)삼텍엔지니어링 | Wire Fixing Means with Function for Sensing Tension of Wire and Wire Driving Type Door Apparatus having The Same |
| CN110581168A (en) * | 2018-06-11 | 2019-12-17 | 爱思开海力士系统集成电路有限公司 | High voltage semiconductor device and method of manufacturing the same |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100700204B1 (en) * | 2005-07-18 | 2007-03-27 | (주)삼텍엔지니어링 | Wire Fixing Means with Function for Sensing Tension of Wire and Wire Driving Type Door Apparatus having The Same |
| CN110581168A (en) * | 2018-06-11 | 2019-12-17 | 爱思开海力士系统集成电路有限公司 | High voltage semiconductor device and method of manufacturing the same |
| CN110581168B (en) * | 2018-06-11 | 2024-01-23 | 爱思开海力士系统集成电路有限公司 | High voltage semiconductor device and method of manufacturing the same |
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