KR20000031775A - Printed circuit board - Google Patents
Printed circuit board Download PDFInfo
- Publication number
- KR20000031775A KR20000031775A KR1019980047987A KR19980047987A KR20000031775A KR 20000031775 A KR20000031775 A KR 20000031775A KR 1019980047987 A KR1019980047987 A KR 1019980047987A KR 19980047987 A KR19980047987 A KR 19980047987A KR 20000031775 A KR20000031775 A KR 20000031775A
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- KR
- South Korea
- Prior art keywords
- circuit board
- printed circuit
- region
- ccls
- metal pattern
- Prior art date
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- 239000002184 metal Substances 0.000 claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 22
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 21
- 239000011889 copper foil Substances 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 8
- 239000012790 adhesive layer Substances 0.000 claims description 6
- 230000032798 delamination Effects 0.000 description 16
- 230000007547 defect Effects 0.000 description 5
- 238000003754 machining Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 239000004020 conductor Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
본 발명은 인쇄회로기판에 관한 것으로, 특히 라우터가공시 절삭되는 동박이 제거된 가공영역에 금속패턴을 형성함으로써 층간에 디라미네이션(delamination)이 발생하는 것을 방지할 수 있는 다층 인쇄회로기판에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board, and more particularly, to a multilayer printed circuit board which can prevent delamination between layers by forming a metal pattern in a processing region from which copper foils cut during router processing are removed. .
전자부품과 부품내장기술의 발달과 더불어 회로도체를 중첩하는 다층 인쇄회로기판이 개발된 이래, 최근 다층 인쇄회로기판(Mulit-Layer Board)의 고밀도화에 대한 연구가 더욱 활발히 진행되고 있다. 그중에서도 빌드업(build-up)방식에 의해 다층 인쇄회로기판을 제조하는 방법이 널리 사용되고 있는데, 이 방법은 종래의 일반적인 BHV(blind via hole)공법과는 달리 절연층과 회로도체층을 순차적으로 적층해서 다층회로를 형성하는 방법이다. 따라서, 빌드업에 의한 인쇄회로기판의 제조는 그 방법 자체가 간단할 뿐만 아니라 그에 따라 제조되는 다층 인쇄회로기판(즉, 빌드업 MLB)은 기판의 층간회로의 연결을 이루는 비어홀(via hole)의 형성이 용이하며, 극소경 비어홀의 형성이 가능하고 회로도체의 두께가 얇아 미세회로의 형성이 용이한 잇점을 가진다.Since the development of electronic components and component embedding technology and the development of multilayer printed circuit boards overlapping circuit conductors, research on the densification of multi-layer printed circuit boards (Mulit-Layer Board) has been actively conducted. Among them, a method of manufacturing a multilayer printed circuit board by a build-up method is widely used. Unlike the conventional BHV method, an insulating layer and a circuit conductor layer are sequentially stacked. It is a method of forming a multilayer circuit. Therefore, the manufacturing of the printed circuit board by the build-up is not only simple in itself, but also the multilayer printed circuit board (i.e., the build-up MLB) manufactured accordingly is formed by the via hole forming the connection of the interlayer circuits of the substrate. It is easy to form, it is possible to form the microscopic via hole, and the thickness of the circuit conductor is thin, which has the advantage of easy formation of microcircuits.
그러나, 상기한 빌드업방식 인쇄회로기판에서는 특성이 서로 다른 절연층 사이에서 발생하는 디라미네이션에 의해 라우터가공(route process)시 인쇄회로기판에 불량을 발생시키는 주요한 요인이 될 수 있다.However, the build-up type printed circuit board may be a major factor causing defects in the printed circuit board during the route processing due to the delamination between the insulating layers having different characteristics.
도 1은 종래의 빌드업방식 인쇄회로기판의 개략 평면도이다. 도면에 나타낸 바와 같이, 빌드업방식 인쇄회로기판(1)은 회로가 형성되는 회로형성영역(3)과 회로가 형성되지 않고 절삭되어 제거되는 사영역(dead region;4) 및 동박이 제거되어 라우터가공이 실제 실행되는 가공영역(5)으로 나누어져 있다. 상기 회로형성영역(3)에는 일반적으로 동박 또는 금속층이 에칭되어 회로가 형성되지만, 설명의 편의를 위하여 상기 도면에는 전체가 동박 또는 금속층으로 덮여 있는 회로형성영역(3)을 나타내었다. 동박이 제거된 가공영역(5)은 라우터가공이 실제로 이루어지는 영역으로, 회로형성영역(3)에 회로가 형성된 후 상기 인쇄회로기판(1)을 전자부품에 실장하기 위해 상기 가공영역(5)을 라우터가공하여 그 외부의 사영역(4)을 절단 제거한다.1 is a schematic plan view of a conventional build-up type printed circuit board. As shown in the figure, the build-up type printed circuit board 1 includes a circuit forming region 3 in which a circuit is formed, a dead region 4 in which a circuit is not formed, and a cut and removed copper router. It is divided into the machining area | region 5 in which a machining is actually performed. In the circuit forming region 3, a copper foil or a metal layer is generally etched to form a circuit. However, for convenience of description, the circuit forming region 3 is entirely covered with a copper foil or metal layer. The processing area 5 in which copper foil is removed is an area where router processing is actually performed. The processing area 5 is mounted to mount the printed circuit board 1 on an electronic component after a circuit is formed in the circuit forming area 3. The router machine cuts and removes the dead area 4 outside.
도 2는 도 1에 도시된 인쇄회로기판의 단면도이다. 도 2에는 도 1과는 달리 회로형성영역에 상세한 회로가 도시되어 있다. 도면에 나타낸 바와 같이, 제1 및 제2CCL(Copper Clad Laminate;7a,7b)은 양면CCL로, 에칭에 의해 양면에 회로(3)가 형성되어 있다. 상기 제1 및 제2CCL(7a,7b)은 프리프레그(prepreg)와 같은 접착층(10)을 사이에 두고 압력에 의해 서로 합착되어 있으며, 접착층(10)과 접하지 않는 면에는 각각 제1 및 제2RCC(Resin Coated Copper;9a,9b)가 적층되어 있다. 상기 제1 및 제2RCC(9a,9b)는 한면에만 동박이 적층되어 있으며, 상기 동박을 에칭함에 따라 회로(3)가 형성된다. 상기 인쇄회로기판에는 기계적 가공등에 의해 스루홀(through hole;11)이 형성되어 층간 회로를 접속시킨다.FIG. 2 is a cross-sectional view of the printed circuit board shown in FIG. 1. Unlike FIG. 1, FIG. 2 shows a detailed circuit in a circuit formation region. As shown in the figure, the first and second CCL (Copper Clad Laminate) 7a, 7b are double-sided CCLs, and circuits 3 are formed on both sides by etching. The first and second CCLs 7a and 7b are bonded to each other by pressure with an adhesive layer 10 such as a prepreg interposed therebetween, and the first and second CCLs 7a and 7b may be bonded to each other by a pressure that is not in contact with the adhesive layer 10. 2RCC (Resin Coated Copper; 9a, 9b) is laminated. The first and second RCCs 9a and 9b have copper foils stacked on only one surface thereof, and a circuit 3 is formed by etching the copper foils. Through holes 11 are formed in the printed circuit board by mechanical processing to connect the interlayer circuits.
제1 및 제2RCC(12a,12b)에 회로를 형성할 때, 상기 RCC(12a,12b)위의 동박의 에칭과 동시에 회로가 형성되는 회로형성영역(3)과 회로가 형성되지 않는 사영역(7) 사이에 동박이 존재하지 않는 가공영역(5)이 형성된다. 이 가공영역(5)은 다층 인쇄회로기판을 완성한 후 전자부품에 실장하기 위해 상기 인쇄회로기판을 라우터가공하여 사영역(7)을 제거하는 영역이다.When forming a circuit in the first and second RCCs 12a and 12b, the circuit forming region 3 in which a circuit is formed simultaneously with the etching of the copper foil on the RCCs 12a and 12b and a dead region in which the circuit is not formed ( 7) The processing area | region 5 in which copper foil does not exist is formed between. The processing area 5 is an area in which the dead area 7 is removed by router processing the printed circuit board for mounting on an electronic component after completing the multilayer printed circuit board.
즉, 인쇄회로기판을 완성한 후, 상기 가공영역(5)을 라우터기계로 가공하여 회로가 형성되지 않는 사영역(4)을 제거함으로써 회로(7)가 형성된 회로형성영역(3) 만이 남게 되고, 이 회로형성영역(3)에 부품을 실장한 후 전자기기에 상기 인쇄회로기판을 장착한다.That is, after the printed circuit board is completed, the machining area 5 is processed by a router machine to remove the dead area 4 where no circuit is formed, leaving only the circuit forming area 3 in which the circuit 7 is formed. After the components are mounted in the circuit formation area 3, the printed circuit board is mounted on an electronic device.
그러나, 상기한 구조의 다층 인쇄회로기판에서는 제1 및 제2CCL(9a,9b) 위에 제1 및 제2RCC(12a,12b)가 적층되기 때문에, 상기 CCL(9a,9b) 및 RCC(12a,12b)의 경계면에는 기포가 존재하게 된다. 따라서, CCL(9a,9b) 및 RCC(12a,12b)를 압착할 때, 기포가 회로가 형성되지 않은 영역, 즉 동박이 존재하지 않는 가공영역(5)으로 모이게 되어 CCL(9a,9b) 및 RCC(12a,12b) 사이에 접착이 이루어지지 않은 디라미네이션(65)이 발생하게 된다. 또한, 합착을 위해 압력을 가할 때, CCL(9a,9b)에 형성된 회로(7)에 의해 가공영역(5)의 양측에 단차가 생기며, 이 단차에 의해 상기 가공영역(5)에 압력이 덜 작용하여 상기 CCL(9a,9b)과 RCC(12a,12b) 사이에 층간 접착이 불량한 디라미네이션(15)이 발생한다.However, in the multilayer printed circuit board having the above-described structure, since the first and second RCCs 12a and 12b are stacked on the first and second CCLs 9a and 9b, the CCLs 9a and 9b and the RCCs 12a and 12b are stacked. Bubbles exist at the interface between Therefore, when the CCLs 9a and 9b and the RCCs 12a and 12b are compressed, bubbles are gathered into a region in which no circuit is formed, that is, a processing region 5 in which copper foil does not exist, and thus the CCLs 9a and 9b and De-lamination 65 is not generated between the RCC (12a, 12b). In addition, when pressure is applied for bonding, a step is generated at both sides of the processing region 5 by the circuit 7 formed in the CCLs 9a and 9b, and this step results in less pressure in the processing region 5. This results in the delamination 15 having poor interlayer adhesion between the CCLs 9a and 9b and the RCCs 12a and 12b.
이러한 디라미네이션(5)이 도 2(a)에 나타낸 바와 같이 가공영역(5)에 형성되는 경우, 라우터가공시 라우터기계가 상기 디라미네이션(15)을 절단하게 되어, 결국 가공후에는 도 2(b)에 도시된 바와 같이 인쇄회로기판의 단부에 디라미네이션영역(15a)이 존재하게 된다.When such a delamination 5 is formed in the machining area 5 as shown in Fig. 2 (a), the router machine cuts the delamination 15 during the router processing, so that after processing, As shown in b), the delamination region 15a is present at the end of the printed circuit board.
상기 단부에 형성된 디라미네이션영역(15a)에 의해 층간의 경계가 외부로 노출된다. 따라서, 외부 온도에 의해 온도특성이 서로 다른 두층간에 변형이 발생하게 되고 외부 습기가 상기 층 사이의 경계면에 침투하여 상기 디라이네이션영역(15a)이 점차 커지게 된다. 특히, 외부의 약한 충격에 의해서도 상기 디라미네이션영역(15a)이 점점 커지기 때문에, 인쇄회로기판이 불량으로 되는 문제가 있었다.The boundary between the layers is exposed to the outside by the delamination region 15a formed at the end. Therefore, deformation occurs between two layers having different temperature characteristics due to external temperature, and external moisture penetrates the interface between the layers, thereby gradually increasing the delining region 15a. In particular, since the delamination region 15a is gradually increased even by an external weak impact, there is a problem that the printed circuit board becomes defective.
본 발명은 상기한 문제를 해결하기 위한 것으로, 회로가 형성된 다층 인쇄회로기판에서 회로가 형성되는 회로형성영역과 회로완성후 가공되어 제거되는 사영역 사이의 가공영역에 일정 폭의 금속패턴을 형성함으로써, 라우터가공시 복수의 층 사이의 디라미네이션에 의해 인쇄회로기판에 불량이 발생하는 것을 제거할 수 있는 다층 인쇄회로기판을 제공하는 것을 목적으로 한다.The present invention is to solve the above problems, by forming a metal pattern of a predetermined width in the processing region between the circuit forming region in which the circuit is formed and the dead region to be processed and removed after completion of the circuit in the multilayer printed circuit board is formed Another object of the present invention is to provide a multilayer printed circuit board capable of eliminating defects in a printed circuit board due to delamination between a plurality of layers during router processing.
상기한 목적을 달성하기 위해, 본 발명은 제1 및 제2CCL과, 제1 및 제2CCL 사이에 형성되어 상기 제1 및 제2CCL을 합착하는 접착층과, 상기 제1 및 제2CCL 각각에 부착되는 제1 및 제2RCC로 이루어진 다층 인쇄회로기판에 있어서, 상기 기판을 금속층이 에칭되어 회로가 형성되는 회로형성영역과, 회로형성후 가공되어 제거되는 사영역과, 상기 회로형성영역과 사영역 사이에 형성되어 실제 가공이 이루어지는 가공영역으로 분할하며, 상기 가공영역의 제1 및 제2CCL의 적어도 한면에 일정 폭의 금속패턴이 형성하여 상기 사영역 제거시 금속패턴을 따라 라우터가공하여 CCL과 RCC 사이에 디라미네이션에 의한 불량이 발생하는 것을 방지한다.In order to achieve the above object, the present invention provides an adhesive layer formed between the first and second CCL, the first and second CCL to bond the first and second CCL, and the first and second CCL. A multilayer printed circuit board comprising first and second RCCs, wherein the substrate is formed between a circuit forming region where a metal layer is etched to form a circuit, a dead region that is processed and removed after circuit formation, and between the circuit forming region and the dead region Divided into a processing area where actual processing is performed, and a metal pattern having a predetermined width is formed on at least one surface of the first and second CCLs of the processing area. Prevents defects caused by lamination.
도 1은 종래 다층 인쇄회로기판의 개략 평면도.1 is a schematic plan view of a conventional multilayer printed circuit board.
도 2는 종래 다층 인쇄회로기판의 단면도.2 is a cross-sectional view of a conventional multilayer printed circuit board.
도 3은 본 발명에 따른 다층 인쇄회로기판의 개략 평면도.3 is a schematic plan view of a multilayer printed circuit board according to the present invention;
도 4는 본 발명에 따른 다층 인쇄회로기판의 평면도.4 is a plan view of a multilayer printed circuit board according to the present invention;
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
51 : 인쇄회로기판 53 : 회로형성영역51: printed circuit board 53: circuit formation area
54 : 사영역 55 : 가공영역54: dead zone 55: machining zone
57 : 회로 59a,59b : CCL57: circuit 59a, 59b: CCL
60 : 접착층 62a,62b : RCC60: adhesive layer 62a, 62b: RCC
65 : 디라미네이션 70 : 금속패턴65: Delamination 70: Metal Pattern
이하, 첨부한 도면을 참조하여 본 발명에 따른 인쇄회로기판을 상세히 설명한다. 이때, 종래의 인쇄회로기판과 동일한 구조에 대해서는 상세한 설명을 생략하고 본 발명의 특징에 대해서만 상세히 설명한다.Hereinafter, a printed circuit board according to the present invention will be described in detail with reference to the accompanying drawings. In this case, a detailed description of the same structure as a conventional printed circuit board will be omitted, and only the features of the present invention will be described in detail.
도 3은 본 발명의 일실시예에 따른 다층 인쇄회로기판의 개략 평면도이다. 도면에 나타낸 바와 같이, 인쇄회로기판(51)은 회로가 형성되어 실제 전자기기에 실장되는 회로형성영역(53)과 회로가 형성되지 않고 제거되는 사영역(54)으로 나누어진다. 상기 회로형성영역(53)과 사영역(54) 사이에는 회로완성 후 상기 사영역(54)을 절단 제거하는 동박이 적층되지 않은 라우터 가공영역(55)이 형성되어 있다. 상기 가공영역(55)에는 설정 크기의 금속패턴(70)이 형성되어 있다. 상기 금속패턴(70)은 복수의 층을 합착할 때, 기판(51) 전체에 걸쳐서 균일한 압력을 인가함과 동시에 회로가 형성되지 않은 사영역(55)에 기포가 모이는 것을 방지함으로서 성분이 다른 층 사이에 디라미네이션이 발생하는 것을 방지한다. 이러한 금속패턴(70)은 도면에 도시된 바와 같이, 일정 크기의 원형상으로 형성하는 것이 바람직하지만, 사각형상, 삼각형상 혹은 타원형상과 같이 그 형상에 특별히 한정되지는 않는다.3 is a schematic plan view of a multilayer printed circuit board according to an embodiment of the present invention. As shown in the figure, the printed circuit board 51 is divided into a circuit forming region 53 in which a circuit is formed and mounted on an actual electronic device, and a dead region 54 in which a circuit is not formed and is removed. Between the circuit formation area 53 and the dead area 54, a router processing area 55 in which the copper foil for cutting and removing the dead area 54 after the completion of the circuit is not laminated is formed. A metal pattern 70 having a predetermined size is formed in the processing region 55. When the metal pattern 70 bonds a plurality of layers, the metal pattern 70 applies uniform pressure over the entirety of the substrate 51 and prevents bubbles from collecting in the dead area 55 where the circuit is not formed. Prevents delamination from occurring between layers. As shown in the drawing, the metal pattern 70 is preferably formed in a circular shape having a predetermined size, but is not particularly limited in shape, such as a square shape, a triangular shape, or an elliptical shape.
도 4는 도 3에 도시된 본 발명의 일실시예에 따른 인쇄회로기판의 단면을 나타내는 도면이다. 도 4(a)에 나타낸 바와 같이, 인쇄회로기판은 회로형성영역(53), 사영역(54) 및 가공영역(55)으로 나누어져 있다. 상기 회로형성영역(53)에는, 제1 및 제2CCL(59a,59b)이 프리프레그와 같은 접착층(60)에 의해 서로 접착되어 있으며, 양면에는 동박이 에칭되어 회로(57)가 형성되어 있다. 상기 제1 및 제2CCL(59a,59b)에는 각각 RCC(62a,62)가 적층되어 있고 그 위에는 동박이 에칭되어 역시 회로(57)가 형성되어 있다.4 is a cross-sectional view of the printed circuit board according to the exemplary embodiment of the present invention illustrated in FIG. 3. As shown in Fig. 4A, the printed circuit board is divided into a circuit forming area 53, a dead area 54 and a processing area 55. In the circuit formation region 53, the first and second CCLs 59a and 59b are bonded to each other by an adhesive layer 60 such as a prepreg, and copper foil is etched on both surfaces to form a circuit 57. RCCs 62a and 62 are stacked on the first and second CCLs 59a and 59b, respectively, and copper foil is etched thereon to form a circuit 57, respectively.
또한, 가공영역(55)의 제1 및 제2CCL(59a,59b)에는 일정 폭의 금속패턴(70)이 형성되어 있다. 도면에는 비록 상기 제1 및 제2CCL(59a,59b)의 양면에 상기 금속패턴(70)이 형성되어 있지만, 제1 및 제2RCC(62a,62b)와 접하는 면에만 상기 금속패턴을 형성하는 것도 물론 가능하다. 상기 금속패턴(70)은 통상 제1 및 제2CCL(59a,59b)의 동박을 에칭하여 회로(57)를 형성할 때 상기 동박을 에칭하여 형성하지만, 동박을 에칭하여 회로(57)를 형성한 후 금속을 적층하여 원하는 두께의 금속패턴(70)을 형성하는 것도 물론 가능하다.In addition, a metal pattern 70 having a predetermined width is formed in the first and second CCLs 59a and 59b of the processing region 55. Although the metal patterns 70 are formed on both surfaces of the first and second CCLs 59a and 59b in the drawing, the metal patterns may be formed only on the surfaces in contact with the first and second RCCs 62a and 62b. It is possible. The metal pattern 70 is typically formed by etching the copper foil when etching the copper foils of the first and second CCLs 59a and 59b to form the circuit 57. However, the circuit 57 is formed by etching the copper foil. It is also possible to form a metal pattern 70 of a desired thickness by laminating a metal after the.
상기 금속패턴(70)은 제1 및 제2CCL(59a,59b)과 제1 및 제2RCC(62a,62b)에 압력을 가하여 합착할 때, 서로 다른 물질 사이에 존재하는 기포를 상기 금속패턴(70)의 표면에 균일하게 분포시켜 상기 기포가 한 장소로 모이는 것을 방지하여 상기 층 사이에 디라미네이션이 발생하는 것을 방지한다. 또한, 상기 금속패턴(70)은 제1 및 제2CCL(59a,59b)과 제1 및 제2RCC(62a,62b)에 압력을 가할 때, 회로형성영역(53)과 사영역(54)에 존재하는 회로(57), 즉 금속패턴에 의한 단차를 제거하는 역할을 하므로, 층 표면에 항상 균일한 압력이 가해지도록 한다. 따라서, 불균일한 압력의 인가에 의한 디라미네이션을 방지할 수 있게 된다.When the metal pattern 70 is bonded to each other by applying pressure to the first and second CCLs 59a and 59b and the first and second RCCs 62a and 62b, the metal pattern 70 may form bubbles existing between different materials. It is evenly distributed on the surface of) to prevent the bubbles from gathering in one place to prevent the occurrence of delamination between the layers. In addition, the metal pattern 70 is present in the circuit formation region 53 and the dead zone 54 when pressure is applied to the first and second CCLs 59a and 59b and the first and second RCCs 62a and 62b. Since the circuit 57 serves to remove the step caused by the metal pattern, a uniform pressure is always applied to the surface of the layer. Therefore, it is possible to prevent delamination due to the application of uneven pressure.
상기한 바와 같이, 본 발명의 일실시예에 따른 인쇄회로기판에서는 가공영역(55)에 형성된 금속패턴(70)에 의해 층 사이에 디라미네이션이 발생하는 것이 방지되기 때문에, 도 4(d)에 나타낸 바와 같이 상기 가공영역(55)을 따라 인쇄회로기판을 라우터가공하여 사영역(54)을 제거하는 경우에도 기판 단부에 디라미네이션영역이 존재하지 않게 된다. 그러므로, 외부 온도나 습기, 혹은 외부압력에 의한 불량을 방지할 수 있게 된다.As described above, in the printed circuit board according to the exemplary embodiment of the present invention, since the lamination is prevented from occurring between the layers by the metal pattern 70 formed in the processing region 55, the process shown in FIG. As shown, even when the printed circuit board is router-processed along the processing area 55 to remove the dead area 54, there is no delamination area at the end of the substrate. Therefore, it is possible to prevent defects caused by external temperature, moisture, or external pressure.
본 발명은 상기한 바와 같이, 다층 인쇄회로기판의 회로형성영역과 사영역 사이의 가공영역에 금속패턴을 형성함으로써 층 사이에 디라미네이션이 발생하는 것을 방지할 수 있게 된다. 따라서, 라우터가공후에 인쇄회로기판 단부에 존재하는 디라미네이션영역의 존재에 의한 기판불량을 방지할 수 있게 된다.As described above, the metal pattern is formed in the processing region between the circuit forming region and the dead region of the multilayer printed circuit board to prevent the occurrence of delamination between layers. Therefore, it is possible to prevent a substrate defect due to the presence of the delamination region present at the end of the printed circuit board after the router processing.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980047987A KR20000031775A (en) | 1998-11-10 | 1998-11-10 | Printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980047987A KR20000031775A (en) | 1998-11-10 | 1998-11-10 | Printed circuit board |
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| Publication Number | Publication Date |
|---|---|
| KR20000031775A true KR20000031775A (en) | 2000-06-05 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980047987A KR20000031775A (en) | 1998-11-10 | 1998-11-10 | Printed circuit board |
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| Country | Link |
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| KR (1) | KR20000031775A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01196897A (en) * | 1988-02-01 | 1989-08-08 | Nec Corp | Ceramic multilayer interconnection substrate |
| JPH06244559A (en) * | 1993-02-19 | 1994-09-02 | Ibiden Co Ltd | Manufacture of ceramic multilayered board |
| JPH0730251A (en) * | 1992-03-23 | 1995-01-31 | Ngk Insulators Ltd | Multilayered ceramic wiring board and manufacture thereof |
-
1998
- 1998-11-10 KR KR1019980047987A patent/KR20000031775A/en not_active Application Discontinuation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01196897A (en) * | 1988-02-01 | 1989-08-08 | Nec Corp | Ceramic multilayer interconnection substrate |
| JPH0730251A (en) * | 1992-03-23 | 1995-01-31 | Ngk Insulators Ltd | Multilayered ceramic wiring board and manufacture thereof |
| JPH06244559A (en) * | 1993-02-19 | 1994-09-02 | Ibiden Co Ltd | Manufacture of ceramic multilayered board |
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